Document M32Rx warnings and errors.
Document --warn-explicit-parallel-conflicts.
This commit is contained in:
Nick Clifton
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@ -1,3 +1,16 @@
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start-sanitize-m32rx
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Wed Feb 11 10:32:28 1998 Nick Clifton <nickc@cygnus.com>
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* doc/c-m32r.texi: Document warning and error messages. Add
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descriptions of --warn-explicit-parallel-conflicts.
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* doc/as.texinfo: Add more m32rx command line options.
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end-sanitize-m32rx
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Tue Feb 10 18:31:31 1998 Ian Lance Taylor <ian@cygnus.com>
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* config/tc-i386.c (i386_operand): Change error added Jan 2 1998
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from as_bad to as_warn.
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start-sanitize-sky
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Tue Feb 10 15:15:40 1998 Doug Evans <devans@canuck.cygnus.com>
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@ -1,5 +1,6 @@
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\input texinfo @c -*-Texinfo-*-
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@c Copyright (c) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
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@c Copyright (c) 1991, 92, 93, 94, 95, 96, 97, 1998
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@c Free Software Foundation, Inc.
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@c UPDATE!! On future updates--
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@c (1) check for new machine-dep cmdline options in
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@c md_parse_option definitions in config/tc-*.c
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@ -85,7 +86,7 @@ END-INFO-DIR-ENTRY
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@ifinfo
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This file documents the GNU Assembler "@value{AS}".
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Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
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Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
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Permission is granted to make and distribute verbatim copies of
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this manual provided the copyright notice and this permission notice
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@ -140,7 +141,7 @@ done.
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@end tex
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@vskip 0pt plus 1filll
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Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
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Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
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Permission is granted to make and distribute verbatim copies of
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this manual provided the copyright notice and this permission notice
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@ -246,7 +247,7 @@ Here is a brief summary of how to invoke @code{@value{AS}}. For details,
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@end ifset
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@c start-sanitize-m32rx
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@ifset M32R
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[ --m32rx ]
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[ --m32rx | --[no-]warn-explicit-parallel-conflicts ]
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@end ifset
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@c end-sanitize-m32rx
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@ifset M680X0
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@ -470,6 +471,14 @@ Mitsubishi M32R series.
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Specify which processor in the M32R family is the target. The default
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is normally the M32R, but this option changes it to the M32RX.
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@item --warn-explicit-parallel-conflicts
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Produce warning messages when questionable parallel constructs are
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encountered.
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@item --no-warn-explicit-parallel-conflicts
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Do not produce warning messages when questionable parallel constructs are
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encountered.
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@end table
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@end ifset
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@c end-sanitize-m32rx
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@ -974,6 +983,7 @@ assembler.)
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* o:: -o to name the object file
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* R:: -R to join data and text sections
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* statistics:: --statistics to see statistics about assembly
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* traditional-format:: --traditional-format for compatible output
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* v:: -v to announce version
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* W:: -W to suppress warnings
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* Z:: -Z to make object file even after errors
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@ -1328,6 +1338,17 @@ Use @samp{--statistics} to display two statistics about the resources used by
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(in bytes), and the total execution time taken for the assembly (in @sc{cpu}
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seconds).
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@node traditional-format
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@section Compatible output: @code{--traditional-format}
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@kindex --traditional-format
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For some targets, the output of @code{@value{AS}} is different in some ways
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from the output of some existing assembler. This switch requests
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@code{@value{AS}} to use the traditional format instead.
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For example, it disables the exception frame optimizations which
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@code{@value{AS}} normally does by default on @code{@value{GCC}} output.
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@node v
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@section Announce Version: @code{-v}
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@ -4721,9 +4742,11 @@ subject, see the hardware manufacturer's manual.
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@ifset I960
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* i960-Dependent:: Intel 80960 Dependent Features
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@end ifset
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@c start-sanitize-m32rx
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@ifset M32R
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* M32R-Dependent:: M32R Dependent Features
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@end ifset
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@c end-sanitize-m32rx
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@ifset M680X0
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* M68K-Dependent:: M680x0 Dependent Features
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@end ifset
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@ -4892,9 +4915,11 @@ family.
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@include c-i960.texi
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@end ifset
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@c start-sanitize-m32rx
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@ifset M32R
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@include c-m32r.texi
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@end ifset
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@c end-sanitize-m32rx
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@ifset M680X0
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@include c-m68k.texi
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@ -1,4 +1,4 @@
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@c Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
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@c Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@ -11,9 +11,12 @@
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@chapter M32R Dependent Features
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@end ifclear
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@c start-sanitize-m32rx
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@cindex M32R support
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@menu
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* M32R-Opts:: M32R Options
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* M32R-Warnings:: M32R Warnings
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@end menu
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@node M32R-Opts
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@ -21,17 +24,116 @@
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@cindex options, M32R
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@cindex M32R options
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The Mitsubishi M32R version of @code{@value{AS}} has a few machine
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dependent options.
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@cindex @samp{--m32rx} option, M32R
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@cindex architecture options, M32R
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The Mitsubishi M32R version of @code{@value{AS}} has a few machine
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dependent options:
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@table @code
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@item --m32rx
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@cindex @samp{--m32rx} option, M32RX
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@cindex architecture options, M32RX
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@cindex M32R architecture options
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@code{@value{AS}} can assemble code for several different members of the
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Mitsubishi M32R family. Normally the default is to assemble code for
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the M32R microprocessor. This option may be used to change the default
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to the M32RX microprocessor, which adds some more instructions to the
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basic M32R instruction set.
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basic M32R instruction set, and some additional parameters to some of
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the original instructions.
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@item --warn-explicit-parallel-conflicts
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@cindex @samp{--warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} to produce warning messages when
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questionable parallel instructions are encountered. This option is
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enabled by default, but @code{@value{GCC}} disables it when it invokes
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@code{@value{AS}} directly. Questionable instructions are those whoes
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behaviour would be different if they were executed sequentially. For
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example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
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different result from @samp{mv r1, r2 \n mv r3, r1} since the former
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moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
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and r3.
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@item --no-warn-explicit-parallel-conflicts
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@cindex @samp{--no-warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} not to produce warning messages when
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questionable parallel instructions are encountered.
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@end table
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@node M32R-Warnings
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@section M32R Warnings
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@cindex warnings, M32R
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@cindex M32R warnings
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There are several warning and error messages that can be produced by
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@code{@value{AS}} which are specific to the M32R:
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@table @code
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@item output of first instruction is the same as the input of second instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the left hand instruction is used as an input register in the right hand
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instruction. For example in this code fragment
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@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
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move instruction and the input to the neg instruction.
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@item output of second instruction is the same as the input of first instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the right hand instruction is used as an input register in the left hand
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instruction. For example in this code fragment
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@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
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neg instruction and the input to the move instruction.
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@item instruction @samp{...} is for the M32RX only
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This message is produced when the assembler encounters an instruction
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which is only supported by the M32Rx processor, and the @samp{--m32rx}
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command line flag has not been specified to allow assembly of such
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instructions.
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@item only the NOP instruction can be issued in parallel on the m32r
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This message is produced when the assembler encounters a parallel
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instruction which does not involve a NOP instruction and the
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@samp{--m32rx} command line flag has not been specified. Only the M32Rx
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processor is able to execute two instructions in parallel.
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@item instruction @samp{...} cannot be executed in parallel.
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This message is produced when the assembler encounters a parallel
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instruction which is made up of one or two instructions which cannot be
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executed in parallel.
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@item Instructions share the same execution pipeline
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This message is produced when the assembler encounters a parallel
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instruction whoes components both use the same execution pipeline.
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@item Both instructions write to the link register
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This message is produced when the assembler encounters a parallel
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instruction whoes components both write to the link register, one of
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them as a side effect. For example this code fragment will produce this
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message: @samp{jl r0 || mv r14, r1}
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@item Destination of first instruction written to by side effect of second instruction.
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This message is produced when the assembler encounters a parallel
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instruction whoes right hand component has a side effect which modifes a
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register used as the destination by the left hand component. For
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example this code fragment will produce this message:
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@samp{mv r1, r2 || ld r0, @@r1+}
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@item Destination of second instruction written to by side effect of first instruction.
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This message is produced when the assembler encounters a parallel
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instruction whoes left hand component has a side effect which modifes a
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register used as the destination by the right hand component. For
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example this code fragment will produce this message:
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@samp{st r2, @@-r1 || mv r1, r3}
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@item Instructions write to the same destination register.
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This message is produced when the assembler encounters a parallel
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instruction where both components attempt to modify the same register.
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For example this code fragment will produce this message:
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@samp{mv r1, r2 || neg r1, r3}
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@end table
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@c end-sanitize-m32rx
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