2005-02-02 Paul Brook <paul@codesourcery.com>
gas/ * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND, T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR, T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB, T2_OPCODE_RSB): Define. (thumb32_negate_data_op): New function. (md_apply_fix): Use it. gas/testsuite/ * gas/arm/thumb2_invert.d: New test. * gas/arm/thumb2_invert.s: New test.
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@ -1,3 +1,12 @@
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2005-02-02 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
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T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
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T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
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T2_OPCODE_RSB): Define.
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(thumb32_negate_data_op): New function.
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(md_apply_fix): Use it.
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2006-01-31 Bob Wilson <bob.wilson@acm.org>
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2006-01-31 Bob Wilson <bob.wilson@acm.org>
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* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
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* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
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@ -460,6 +460,9 @@ struct asm_opcode
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#define DATA_OP_SHIFT 21
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#define DATA_OP_SHIFT 21
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#define T2_OPCODE_MASK 0xfe1fffff
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#define T2_DATA_OP_SHIFT 21
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/* Codes to distinguish the arithmetic instructions. */
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/* Codes to distinguish the arithmetic instructions. */
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#define OPCODE_AND 0
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#define OPCODE_AND 0
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#define OPCODE_EOR 1
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#define OPCODE_EOR 1
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@ -478,6 +481,17 @@ struct asm_opcode
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#define OPCODE_BIC 14
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#define OPCODE_BIC 14
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#define OPCODE_MVN 15
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#define OPCODE_MVN 15
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#define T2_OPCODE_AND 0
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#define T2_OPCODE_BIC 1
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#define T2_OPCODE_ORR 2
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#define T2_OPCODE_ORN 3
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#define T2_OPCODE_EOR 4
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#define T2_OPCODE_ADD 8
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#define T2_OPCODE_ADC 10
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#define T2_OPCODE_SBC 11
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#define T2_OPCODE_SUB 13
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#define T2_OPCODE_RSB 14
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#define T_OPCODE_MUL 0x4340
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#define T_OPCODE_MUL 0x4340
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#define T_OPCODE_TST 0x4200
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#define T_OPCODE_TST 0x4200
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#define T_OPCODE_CMN 0x42c0
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#define T_OPCODE_CMN 0x42c0
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@ -11113,6 +11127,82 @@ negate_data_op (unsigned long * instruction,
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return value;
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return value;
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}
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}
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/* Like negate_data_op, but for Thumb-2. */
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static unsigned int
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thumb32_negate_data_op (offsetT *instruction, offsetT value)
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{
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int op, new_inst;
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int rd;
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offsetT negated, inverted;
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negated = encode_thumb32_immediate (-value);
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inverted = encode_thumb32_immediate (~value);
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rd = (*instruction >> 8) & 0xf;
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op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
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switch (op)
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{
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/* ADD <-> SUB. Includes CMP <-> CMN. */
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case T2_OPCODE_SUB:
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new_inst = T2_OPCODE_ADD;
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value = negated;
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break;
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case T2_OPCODE_ADD:
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new_inst = T2_OPCODE_SUB;
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value = negated;
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break;
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/* ORR <-> ORN. Includes MOV <-> MVN. */
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case T2_OPCODE_ORR:
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new_inst = T2_OPCODE_ORN;
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value = inverted;
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break;
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case T2_OPCODE_ORN:
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new_inst = T2_OPCODE_ORR;
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value = inverted;
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break;
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/* AND <-> BIC. TST has no inverted equivalent. */
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case T2_OPCODE_AND:
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new_inst = T2_OPCODE_BIC;
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if (rd == 15)
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value = FAIL;
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else
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value = inverted;
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break;
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case T2_OPCODE_BIC:
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new_inst = T2_OPCODE_AND;
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value = inverted;
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break;
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/* ADC <-> SBC */
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case T2_OPCODE_ADC:
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new_inst = T2_OPCODE_SBC;
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value = inverted;
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break;
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case T2_OPCODE_SBC:
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new_inst = T2_OPCODE_ADC;
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value = inverted;
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break;
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/* We cannot do anything. */
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default:
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return FAIL;
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}
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if (value == FAIL)
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return FAIL;
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*instruction &= T2_OPCODE_MASK;
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*instruction |= new_inst << T2_DATA_OP_SHIFT;
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return value;
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}
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/* Read a 32-bit thumb instruction from buf. */
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/* Read a 32-bit thumb instruction from buf. */
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static unsigned long
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static unsigned long
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get_thumb32_insn (char * buf)
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get_thumb32_insn (char * buf)
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/* FUTURE: Implement analogue of negate_data_op for T32. */
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/* FUTURE: Implement analogue of negate_data_op for T32. */
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if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
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if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
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{
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newimm = encode_thumb32_immediate (value);
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newimm = encode_thumb32_immediate (value);
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if (newimm == (unsigned int) FAIL)
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newimm = thumb32_negate_data_op (&newval, value);
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}
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else
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else
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{
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{
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/* 12 bit immediate for addw/subw. */
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/* 12 bit immediate for addw/subw. */
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@ -1,3 +1,8 @@
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2005-02-02 Paul Brook <paul@codesourcery.com>
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* gas/arm/thumb2_invert.d: New test.
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* gas/arm/thumb2_invert.s: New test.
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2006-01-31 Paul Brook <paul@codesourcery.com>
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2006-01-31 Paul Brook <paul@codesourcery.com>
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* gas/testsuite/gas/arm/iwmmxt-bad.s: Add check for bad register name.
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* gas/testsuite/gas/arm/iwmmxt-bad.s: Add check for bad register name.
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@ -0,0 +1,16 @@
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# as: -march=armv6kt2
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# objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]+> f517 0f80 cmn.w r7, #4194304 ; 0x400000
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0+004 <[^>]+> f5b8 0f80 cmp.w r8, #4194304 ; 0x400000
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0+008 <[^>]+> f5a4 0980 sub.w r9, r4, #4194304 ; 0x400000
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0+00c <[^>]+> f506 0380 add.w r3, r6, #4194304 ; 0x400000
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0+010 <[^>]+> f160 4500 sbc.w r5, r0, #2147483648 ; 0x80000000
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0+014 <[^>]+> f147 4400 adc.w r4, r7, #2147483648 ; 0x80000000
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0+018 <[^>]+> f022 4600 bic.w r6, r2, #2147483648 ; 0x80000000
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0+01c <[^>]+> f002 4800 and.w r8, r2, #2147483648 ; 0x80000000
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0+020 <[^>]+> f06f 4300 mvn.w r3, #2147483648 ; 0x80000000
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0+024 <[^>]+> f04f 4100 mov.w r1, #2147483648 ; 0x80000000
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@ -0,0 +1,14 @@
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.text
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.thumb
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.syntax unified
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thumb2_invert:
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cmp r7, #0xffc00000
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cmn r8, #0xffc00000
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add r9, r4, #0xffc00000
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sub r3, r6, #0xffc00000
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adc r5, r0, #0x7fffffff
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sbc r4, r7, #0x7fffffff
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and r6, r2, #0x7fffffff
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bic r8, r2, #0x7fffffff
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mov r3, 0x7fffffff
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mvn r1, 0x7fffffff
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