[binutils, ARM, 15/16] Add support for VSCCLRM
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types. These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list. The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message. The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests. It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction. Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment. (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR enumerators. (parse_vfp_reg_list): Add new partial_match parameter. Set *partial_match to TRUE if at least one element in the register list has matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR register lists which expect VPR as last element in the list. (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new prototype. (s_arm_unwind_save_vfp): Likewise. (enum operand_parse_code): New OP_VRSDVLST enumerator. (parse_operands): Adapt call to parse_vfp_reg_list to new prototype. Handle new OP_VRSDVLST case. (do_t_vscclrm): New function. (insns): New entry for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM instructions. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations for above instructions. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly for above instructions. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %C format control code. Add new entries for VSCCLRM instruction. (print_insn_coprocessor): Handle new %C format control code.
This commit is contained in:
Andre Vieira
parent
6b0dd09474
commit
efd6b3591b
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@ -1,3 +1,29 @@
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
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(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
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enumerators.
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(parse_vfp_reg_list): Add new partial_match parameter. Set
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*partial_match to TRUE if at least one element in the register list has
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matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
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register lists which expect VPR as last element in the list.
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(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
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prototype.
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(s_arm_unwind_save_vfp): Likewise.
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(enum operand_parse_code): New OP_VRSDVLST enumerator.
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(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
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Handle new OP_VRSDVLST case.
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(do_t_vscclrm): New function.
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(insns): New entry for VSCCLRM instruction.
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* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
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instructions.
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* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
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for above instructions.
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* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
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instruction.
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* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
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for above instructions.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (enum reg_list_els): Define earlier and add
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@ -1609,7 +1609,7 @@ parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
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return reg->number;
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}
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/* Like arm_reg_parse, but allow allow the following extra features:
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/* Like arm_reg_parse, but also allow the following extra features:
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- If RTYPE is non-zero, return the (possibly restricted) type of the
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register (e.g. Neon double or quad reg when either has been requested).
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- If this is a Neon vector type with additional type information, fill
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@ -1695,7 +1695,9 @@ enum reg_list_els
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REGLIST_RN,
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REGLIST_CLRM,
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REGLIST_VFP_S,
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REGLIST_VFP_S_VPR,
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REGLIST_VFP_D,
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REGLIST_VFP_D_VPR,
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REGLIST_NEON_D
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};
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@ -1869,7 +1871,8 @@ parse_reg_list (char ** strp, enum reg_list_els etype)
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bug. */
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static int
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parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
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bfd_boolean *partial_match)
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{
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char *str = *ccp;
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int base_reg;
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@ -1880,6 +1883,9 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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int warned = 0;
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unsigned long mask = 0;
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int i;
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bfd_boolean vpr_seen = FALSE;
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bfd_boolean expect_vpr =
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(etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
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if (skip_past_char (&str, '{') == FAIL)
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{
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@ -1890,11 +1896,13 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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switch (etype)
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{
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case REGLIST_VFP_S:
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case REGLIST_VFP_S_VPR:
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regtype = REG_TYPE_VFS;
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max_regs = 32;
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break;
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case REGLIST_VFP_D:
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case REGLIST_VFP_D_VPR:
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regtype = REG_TYPE_VFD;
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break;
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@ -1906,7 +1914,7 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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gas_assert (0);
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}
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if (etype != REGLIST_VFP_S)
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if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
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{
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/* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
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if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
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@ -1924,19 +1932,54 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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}
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base_reg = max_regs;
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*partial_match = FALSE;
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do
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{
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int setmask = 1, addregs = 1;
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const char vpr_str[] = "vpr";
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int vpr_str_len = strlen (vpr_str);
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new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
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if (new_base == FAIL)
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if (expect_vpr)
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{
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if (new_base == FAIL
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&& !strncasecmp (str, vpr_str, vpr_str_len)
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&& !ISALPHA (*(str + vpr_str_len))
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&& !vpr_seen)
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{
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vpr_seen = TRUE;
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str += vpr_str_len;
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if (count == 0)
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base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
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}
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else if (vpr_seen)
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{
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first_error (_("VPR expected last"));
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return FAIL;
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}
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else if (new_base == FAIL)
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{
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if (regtype == REG_TYPE_VFS)
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first_error (_("VFP single precision register or VPR "
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"expected"));
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else /* regtype == REG_TYPE_VFD. */
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first_error (_("VFP/Neon double precision register or VPR "
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"expected"));
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return FAIL;
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}
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}
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else if (new_base == FAIL)
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{
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first_error (_(reg_expected_msgs[regtype]));
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return FAIL;
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}
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*partial_match = TRUE;
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if (vpr_seen)
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continue;
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if (new_base >= max_regs)
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{
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first_error (_("register out of range in list"));
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@ -1959,7 +2002,7 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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return FAIL;
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}
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if ((mask >> new_base) != 0 && ! warned)
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if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
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{
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as_tsktsk (_("register list not in ascending order"));
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warned = 1;
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@ -2014,11 +2057,17 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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str++;
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/* Sanity check -- should have raised a parse error above. */
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if (count == 0 || count > max_regs)
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if ((!vpr_seen && count == 0) || count > max_regs)
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abort ();
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*pbase = base_reg;
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if (expect_vpr && !vpr_seen)
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{
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first_error (_("VPR expected last"));
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return FAIL;
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}
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/* Final test -- the registers must be consecutive. */
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mask >>= base_reg;
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for (i = 0; i < count; i++)
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@ -4146,8 +4195,10 @@ s_arm_unwind_save_vfp_armv6 (void)
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valueT op;
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int num_vfpv3_regs = 0;
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int num_regs_below_16;
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bfd_boolean partial_match;
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count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
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count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
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&partial_match);
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if (count == FAIL)
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{
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as_bad (_("expected register list"));
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@ -4194,8 +4245,10 @@ s_arm_unwind_save_vfp (void)
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int count;
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unsigned int reg;
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valueT op;
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bfd_boolean partial_match;
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count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
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count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D,
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&partial_match);
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if (count == FAIL)
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{
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as_bad (_("expected register list"));
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@ -6585,6 +6638,7 @@ enum operand_parse_code
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OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
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OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
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OP_NSTRLST, /* Neon element/structure list */
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OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
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OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
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OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
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@ -6694,6 +6748,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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enum arm_reg_type rtype;
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parse_operand_result result;
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unsigned int op_parse_code;
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bfd_boolean partial_match;
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#define po_char_or_fail(chr) \
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do \
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@ -7218,29 +7273,43 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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break;
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case OP_VRSLST:
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
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&partial_match);
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break;
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case OP_VRDLST:
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
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&partial_match);
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break;
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case OP_VRSDLST:
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/* Allow Q registers too. */
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
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REGLIST_NEON_D);
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REGLIST_NEON_D, &partial_match);
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if (val == FAIL)
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{
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inst.error = NULL;
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
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REGLIST_VFP_S);
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REGLIST_VFP_S, &partial_match);
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inst.operands[i].issingle = 1;
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}
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break;
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case OP_VRSDVLST:
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
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REGLIST_VFP_D_VPR, &partial_match);
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if (val == FAIL && !partial_match)
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{
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inst.error = NULL;
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
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REGLIST_VFP_S_VPR, &partial_match);
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inst.operands[i].issingle = 1;
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}
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break;
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case OP_NRDLST:
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
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REGLIST_NEON_D);
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REGLIST_NEON_D, &partial_match);
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break;
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case OP_NSTRLST:
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@ -7344,6 +7413,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_VRSLST:
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case OP_VRDLST:
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case OP_VRSDLST:
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case OP_VRSDVLST:
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case OP_NRDLST:
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case OP_NSTRLST:
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if (val == FAIL)
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@ -12814,6 +12884,24 @@ do_t_clrm (void)
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}
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}
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static void
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do_t_vscclrm (void)
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{
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if (inst.operands[0].issingle)
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{
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inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
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inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
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inst.instruction |= inst.operands[0].imm;
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}
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else
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{
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inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
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inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
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inst.instruction |= 1 << 8;
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inst.instruction |= inst.operands[0].imm << 1;
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}
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}
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static void
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do_t_rbit (void)
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{
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@ -21889,7 +21977,8 @@ static const struct asm_opcode insns[] =
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toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
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toU("le", _le, 2, (oLR, EXP), t_loloop),
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ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm)
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ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
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ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm)
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};
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#undef ARM_VARIANT
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#undef THUMB_VARIANT
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@ -2,3 +2,7 @@
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[^:]*:6: Error: r0-r12, lr or APSR expected -- `clrm {}'
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[^:]*:7: Error: r0-r12, lr or APSR expected -- `clrm {sp}'
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[^:]*:8: Error: r0-r12, lr or APSR expected -- `clrm {pc}'
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[^:]*:10: Error: VFP single precision register or VPR expected -- `vscclrm {}'
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[^:]*:11: Error: VPR expected last -- `vscclrm {s0}'
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[^:]*:12: Error: VFP single precision register or VPR expected -- `vscclrm {s1,d1,VPR}'
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[^:]*:13: Error: VFP single precision register expected -- `vscclrm {s1-d1,VPR}'
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@ -6,3 +6,8 @@ T:
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clrm {} @ Rejects empty list
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clrm {sp} @ Rejects SP in list
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clrm {pc} @ Reject PC in list
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vscclrm {} @ Rejects empty list
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vscclrm {s0} @ Rejects list without VPR
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vscclrm {s1, d1, VPR} @ Reject mix of single and double-precision VFP registers
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vscclrm {s1-d1, VPR} @ Likewise when using a range
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@ -11,4 +11,13 @@ Disassembly of section .text:
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0+.* <[^>]*> e89f 8008 clrm {r3, APSR}
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0+.* <[^>]*> bf08 it eq
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0+.* <[^>]*> e89f 0010 clrmeq {r4}
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0+.* <[^>]*> ec9f 0b00 vscclrm {VPR}
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0+.* <[^>]*> ec9f fa01 vscclrm {s30, VPR}
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0+.* <[^>]*> ec9f eb02 vscclrm {d14, VPR}
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0+.* <[^>]*> ecdf 0a04 vscclrm {s1-s4, VPR}
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0+.* <[^>]*> ec9f 1b08 vscclrm {d1-d4, VPR}
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0+.* <[^>]*> ec9f 0a20 vscclrm {s0-s31, VPR}
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0+.* <[^>]*> ec9f 0b20 vscclrm {d0-d15, VPR}
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0+.* <[^>]*> bf18 it ne
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0+.* <[^>]*> ecdf 1a01 vscclrmne {s3, VPR}
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#...
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@ -7,3 +7,14 @@ clrm {r0, r2} @ Accepts list without APSR
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clrm {APSR} @ Accepts APSR alone
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clrm {r3, APSR} @ Accepts core register and APSR together
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clrmeq {r4} @ Accepts conditional execution
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vscclrm {VPR} @ Accepts list with only VPR
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vscclrm {s30, VPR} @ Accept single-precision VFP register and VPR together
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vscclrm {d14, VPR} @ Likewise for double-precision VFP register
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vscclrm {s1-s4, VPR} @ Accept range of single-precision VFP registers
|
||||
@ and VPR together
|
||||
vscclrm {d1-d4, VPR} @ Likewise for double-precision VFP registers
|
||||
vscclrm {s0-s31, VPR} @ Accept all single-precision VFP registers and VPR
|
||||
@ together
|
||||
vscclrm {d0-d15, VPR} @ Likewise for double-precision VFP registers
|
||||
vscclrmne {s3, VPR} @ Accepts conditional execution
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
|
||||
Add new entries for VSCCLRM instruction.
|
||||
(print_insn_coprocessor): Handle new %C format control code.
|
||||
|
||||
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||||
|
||||
* arm-dis.c (enum isa): New enum.
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@ struct opcode16
|
|||
UNPREDICTABLE if not AL in Thumb)
|
||||
%A print address for ldc/stc/ldf/stf instruction
|
||||
%B print vstm/vldm register list
|
||||
%C print vscclrm register list
|
||||
%I print cirrus signed shift immediate: bits 0..3|4..6
|
||||
%F print the COUNT field of a LFM/SFM instruction.
|
||||
%P print floating point precision in arithmetic insn
|
||||
|
|
@ -425,6 +426,12 @@ static const struct sopcode32 coprocessor_opcodes[] =
|
|||
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
|
||||
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
|
||||
|
||||
/* Armv8.1-M Mainline instructions. */
|
||||
{T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
|
||||
{T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
|
||||
|
||||
/* ARMv8-M Mainline Security Extensions instructions. */
|
||||
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
|
||||
0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
|
||||
|
|
@ -3642,6 +3649,31 @@ print_insn_coprocessor (bfd_vma pc,
|
|||
}
|
||||
break;
|
||||
|
||||
case 'C':
|
||||
{
|
||||
bfd_boolean single = ((given >> 8) & 1) == 0;
|
||||
char reg_prefix = single ? 's' : 'd';
|
||||
int Dreg = (given >> 22) & 0x1;
|
||||
int Vdreg = (given >> 12) & 0xf;
|
||||
int reg = single ? ((Vdreg << 1) | Dreg)
|
||||
: ((Dreg << 4) | Vdreg);
|
||||
int num = (given >> (single ? 0 : 1)) & 0x7f;
|
||||
int maxreg = single ? 31 : 15;
|
||||
int topreg = reg + num - 1;
|
||||
|
||||
if (!num)
|
||||
func (stream, "{VPR}");
|
||||
else if (num == 1)
|
||||
func (stream, "{%c%d, VPR}", reg_prefix, reg);
|
||||
else if (topreg > maxreg)
|
||||
func (stream, "{%c%d-<overflow reg d%d, VPR}",
|
||||
reg_prefix, reg, single ? topreg >> 1 : topreg);
|
||||
else
|
||||
func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
|
||||
reg_prefix, topreg);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'u':
|
||||
if (cond != COND_UNCOND)
|
||||
is_unpredictable = TRUE;
|
||||
|
|
|
|||
Loading…
Reference in New Issue