Compress loads/stores with implicit 0 offset.
gas/ * config/tc-riscv.c (riscv_handle_implicit_zero_offset): New. (riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to riscv_handle_implicit_zero_offset. At label load_store, replace existing code with call to riscv_handle_implicit_zero_offset. * testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New. * testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New. * testsuite/gas/riscv/riscv.exp: Run new tests.
This commit is contained in:
parent
033bfb739b
commit
f0531ed6a4
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@ -1,3 +1,16 @@
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2017-11-27 Andrew Waterman <andrew@sifive.com>
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Palmer Dabbelt <palmer@sifive.com>
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Jim Wilson <jimw@sifive.com>
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gas/
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* config/tc-riscv.c (riscv_handle_implicit_zero_offset): New.
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(riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to
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riscv_handle_implicit_zero_offset. At label load_store, replace
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existing code with call to riscv_handle_implicit_zero_offset.
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* testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New.
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* testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New.
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* testsuite/gas/riscv/riscv.exp: Run new tests.
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2017-11-27 Max Filippov <jcmvbkbc@gmail.com>
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* config/tc-xtensa.c (find_trampoline_seg): Add static variable
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@ -1185,6 +1185,25 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
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return reloc_index;
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}
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/* Detect and handle implicitly zero load-store offsets. For example,
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"lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
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an implicit offset was detected. */
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static bfd_boolean
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riscv_handle_implicit_zero_offset (expressionS *expr, const char *s)
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{
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/* Check whether there is only a single bracketed expression left.
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If so, it must be the base register and the constant must be zero. */
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if (*s == '(' && strchr (s + 1, '(') == 0)
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{
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expr->X_op = O_constant;
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expr->X_add_number = 0;
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return TRUE;
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}
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return FALSE;
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}
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/* This routine assembles an instruction into its binary format. As a
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side effect, it sets the global variable imm_reloc to the type of
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relocation to do if one of the operands is an address expression. */
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@ -1325,6 +1344,8 @@ rvc_imm_done:
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ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
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goto rvc_imm_done;
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case 'k':
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if (riscv_handle_implicit_zero_offset (imm_expr, s))
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continue;
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| !VALID_RVC_LW_IMM (imm_expr->X_add_number))
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@ -1332,6 +1353,8 @@ rvc_imm_done:
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ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
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goto rvc_imm_done;
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case 'l':
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if (riscv_handle_implicit_zero_offset (imm_expr, s))
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continue;
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| !VALID_RVC_LD_IMM (imm_expr->X_add_number))
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@ -1339,6 +1362,8 @@ rvc_imm_done:
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ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
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goto rvc_imm_done;
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case 'm':
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if (riscv_handle_implicit_zero_offset (imm_expr, s))
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continue;
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
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@ -1347,6 +1372,8 @@ rvc_imm_done:
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ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
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goto rvc_imm_done;
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case 'n':
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if (riscv_handle_implicit_zero_offset (imm_expr, s))
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continue;
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
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@ -1380,6 +1407,8 @@ rvc_imm_done:
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ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
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goto rvc_imm_done;
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case 'M':
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if (riscv_handle_implicit_zero_offset (imm_expr, s))
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continue;
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
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@ -1388,6 +1417,8 @@ rvc_imm_done:
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ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
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goto rvc_imm_done;
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case 'N':
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if (riscv_handle_implicit_zero_offset (imm_expr, s))
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continue;
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
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@ -1618,12 +1649,7 @@ rvc_lui:
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p = percent_op_rtype;
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*imm_reloc = BFD_RELOC_UNUSED;
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load_store:
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/* Check whether there is only a single bracketed expression
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left. If so, it must be the base register and the
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constant must be zero. */
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imm_expr->X_op = O_constant;
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imm_expr->X_add_number = 0;
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if (*s == '(' && strchr (s + 1, '(') == 0)
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if (riscv_handle_implicit_zero_offset (imm_expr, s))
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continue;
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alu_op:
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/* If this value won't fit into a 16 bit offset, then go
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@ -0,0 +1,17 @@
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#as: -march=rv64ic
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#objdump: -dr
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+0:[ ]+6108[ ]+ld[ ]+a0,0\(a0\)
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[ ]+2:[ ]+6108[ ]+ld[ ]+a0,0\(a0\)
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[ ]+4:[ ]+e108[ ]+sd[ ]+a0,0\(a0\)
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[ ]+6:[ ]+e108[ ]+sd[ ]+a0,0\(a0\)
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[ ]+8:[ ]+6502[ ]+ld[ ]+a0,0\(sp\)
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[ ]+a:[ ]+6502[ ]+ld[ ]+a0,0\(sp\)
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[ ]+c:[ ]+e02a[ ]+sd[ ]+a0,0\(sp\)
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[ ]+e:[ ]+e02a[ ]+sd[ ]+a0,0\(sp\)
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@ -0,0 +1,9 @@
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target:
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ld a0, (a0) # 'Cl'
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ld a0, 0(a0) # 'Cl'
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sd a0, (a0) # 'Cl'
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sd a0, 0(a0) # 'Cl'
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ld a0, (sp) # 'Cn'
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ld a0, 0(sp) # 'Cn'
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sd a0, (sp) # 'CN'
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sd a0, 0(sp) # 'CN'
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@ -0,0 +1,17 @@
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#as: -march=rv32ic
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#objdump: -dr
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+0:[ ]+4108[ ]+lw[ ]+a0,0\(a0\)
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[ ]+2:[ ]+4108[ ]+lw[ ]+a0,0\(a0\)
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[ ]+4:[ ]+c108[ ]+sw[ ]+a0,0\(a0\)
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[ ]+6:[ ]+c108[ ]+sw[ ]+a0,0\(a0\)
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[ ]+8:[ ]+4502[ ]+lw[ ]+a0,0\(sp\)
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[ ]+a:[ ]+4502[ ]+lw[ ]+a0,0\(sp\)
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[ ]+c:[ ]+c02a[ ]+sw[ ]+a0,0\(sp\)
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[ ]+e:[ ]+c02a[ ]+sw[ ]+a0,0\(sp\)
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@ -0,0 +1,9 @@
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target:
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lw a0, (a0) # 'Ck'
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lw a0, 0(a0) # 'Ck'
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sw a0, (a0) # 'Ck'
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sw a0, 0(a0) # 'Ck'
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lw a0, (sp) # 'Cm'
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lw a0, 0(sp) # 'Cm'
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sw a0, (sp) # 'CM'
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sw a0, 0(sp) # 'CM'
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@ -26,4 +26,6 @@ if [istarget riscv*-*-*] {
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run_dump_test "c-addi16sp-fail"
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run_dump_test "satp"
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run_dump_test "eh-relocs"
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run_dump_test "c-lw"
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run_dump_test "c-ld"
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}
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