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2005-10-26 Paul Brook <paul@codesourcery.com> 

gas/
	* config/tc-arm.c (insns): Correct "sel" entry.
gas/testsuite/
	* gas/arm/archv6.d: Adjust expected output.
opcodes/
	* arm-dis.c (arm_opcodes): Correct "sel" entry.
This commit is contained in:
Paul Brook 2005-10-26 14:09:29 +00:00
parent 4d1bb7955a
commit f1022c90ad
6 changed files with 16 additions and 4 deletions
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4
gas/ChangeLog
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@ -1,3 +1,7 @@
2005-10-26 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (insns): Correct "sel" entry.
2005-10-26 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (i386_operand): Don't check register prefix here.

2
gas/config/tc-arm.c
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@ -8928,7 +8928,7 @@ static const struct asm_opcode insns[] =
TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),

4
gas/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2005-10-26 Paul Brook <paul@codesourcery.com>
* gas/arm/archv6.d: Adjust expected output.
2005-10-26 Jan Beulich <jbeulich@novell.com>
* gas/i386/intel.s: Replace register used in offset expression.

4
gas/testsuite/gas/arm/archv6.d
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@ -64,8 +64,8 @@ Disassembly of section .text:
0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ROR #8
0+0e4 <[^>]*> e6142f37 ? saddaddx r2, r4, r7
0+0e8 <[^>]*> 16142f37 ? saddaddxne r2, r4, r7
0+0ec <[^>]*> e68210b3 ? sel r1, r2, r3
0+0f0 <[^>]*> 168210b3 ? selne r1, r2, r3
0+0ec <[^>]*> e6821fb3 ? sel r1, r2, r3
0+0f0 <[^>]*> 16821fb3 ? selne r1, r2, r3
0+0f4 <[^>]*> f1010200 ? setend be
0+0f8 <[^>]*> f1010000 ? setend le
0+0fc <[^>]*> e6342f17 ? shadd16 r2, r4, r7

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2005-10-26 Paul Brook <paul@codesourcery.com>
* arm-dis.c (arm_opcodes): Correct "sel" entry.
2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* m32r-asm.c: Regenerate.

2
opcodes/arm-dis.c
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@ -557,7 +557,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
{ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
{ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
{ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
{ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},