Enable VREX for AVX512 directives
Enable VREX for AVX512 instructions with upper 16 vector registers. gas/ PR gas/20141 * testsuite/gas/i386/i386.exp: Run x86-64-pr20141. * testsuite/gas/i386/x86-64-pr20141.d: New file. * testsuite/gas/i386/x86-64-pr20141.s: Likewise. opcodes/ PR gas/20141 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. * i386-init.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
293f5f6543
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f1360d5830
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@ -1,3 +1,10 @@
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2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/20141
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* testsuite/gas/i386/i386.exp: Run x86-64-pr20141.
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* testsuite/gas/i386/x86-64-pr20141.d: New file.
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* testsuite/gas/i386/x86-64-pr20141.s: Likewise.
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2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (arch_entry): Remove negated.
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@ -753,6 +753,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-rdpid-intel"
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run_dump_test "x86-64-fence-as-lock-add-yes"
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run_dump_test "x86-64-fence-as-lock-add-no"
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run_dump_test "x86-64-pr20141"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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@ -0,0 +1,10 @@
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#objdump: -dw
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 62 e1 7d 48 e7 21 vmovntdq %zmm20,\(%rcx\)
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#pass
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.text
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.arch corei7
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.arch .avx512f
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_start:
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vmovntdq %zmm20, (%rcx)
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@ -1,3 +1,10 @@
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2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/20141
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* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
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CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
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* i386-init.h: Regenerated.
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2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
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@ -200,13 +200,13 @@ static initializer cpu_flag_init[] =
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{ "CPU_AVX2_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2" },
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{ "CPU_AVX512F_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" },
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"CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" },
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{ "CPU_AVX512CD_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" },
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"CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" },
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{ "CPU_AVX512ER_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" },
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"CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" },
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{ "CPU_AVX512PF_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" },
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"CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" },
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{ "CPU_ANY_AVX_FLAGS",
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"CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" },
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{ "CPU_L1OM_FLAGS",
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@ -575,28 +575,28 @@
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
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0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_AVX512CD_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
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0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_AVX512ER_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
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0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_AVX512PF_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
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0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_ANY_AVX_FLAGS \
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