opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle. gas/testsuite/ * gas/aarch64/fp-const0-parsing.s: New test. * gas/aarch64/fp-const0-parsing.d: Likewise.
This commit is contained in:
Yufeng Zhang
parent
a58549dda5
commit
f17c8bfcc8
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@ -1,3 +1,8 @@
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2014-02-27 Jiong Wang <jiong.wang@arm.com>
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* gas/aarch64/fp-const0-parsing.s: New test.
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* gas/aarch64/fp-const0-parsing.d: Likewise.
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2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/ldst-reg-reg-offset.s: Add tests.
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@ -0,0 +1,37 @@
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0000000000000000 <.*>:
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0: 5ea0dbc0 fcmeq s0, s30, #0.0
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4: 7ea0cba1 fcmge s1, s29, #0.0
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8: 5ea0cb82 fcmgt s2, s28, #0.0
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c: 7ea0db63 fcmle s3, s27, #0.0
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10: 5ea0eb44 fcmlt s4, s26, #0.0
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14: 5ee0dbc0 fcmeq d0, d30, #0.0
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18: 7ee0cba1 fcmge d1, d29, #0.0
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1c: 5ee0cb82 fcmgt d2, d28, #0.0
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20: 7ee0db63 fcmle d3, d27, #0.0
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24: 5ee0eb44 fcmlt d4, d26, #0.0
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28: 0ea0dbc0 fcmeq v0.2s, v30.2s, #0.0
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2c: 6ea0cba1 fcmge v1.4s, v29.4s, #0.0
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30: 4ee0cb82 fcmgt v2.2d, v28.2d, #0.0
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34: 2ea0db63 fcmle v3.2s, v27.2s, #0.0
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38: 4ea0eb44 fcmlt v4.4s, v26.4s, #0.0
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3c: 5ea0dbc0 fcmeq s0, s30, #0.0
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40: 7ea0cba1 fcmge s1, s29, #0.0
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44: 5ea0cb82 fcmgt s2, s28, #0.0
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48: 7ea0db63 fcmle s3, s27, #0.0
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4c: 5ea0eb44 fcmlt s4, s26, #0.0
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50: 5ee0dbc0 fcmeq d0, d30, #0.0
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54: 7ee0cba1 fcmge d1, d29, #0.0
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58: 5ee0cb82 fcmgt d2, d28, #0.0
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5c: 7ee0db63 fcmle d3, d27, #0.0
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60: 5ee0eb44 fcmlt d4, d26, #0.0
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64: 0ea0dbc0 fcmeq v0.2s, v30.2s, #0.0
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68: 6ea0cba1 fcmge v1.4s, v29.4s, #0.0
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6c: 4ee0cb82 fcmgt v2.2d, v28.2d, #0.0
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70: 2ea0db63 fcmle v3.2s, v27.2s, #0.0
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74: 4ea0eb44 fcmlt v4.4s, v26.4s, #0.0
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@ -0,0 +1,60 @@
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/* fp-const0-parse.s Test file For AArch64 float constant 0 parse.
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Copyright 2014 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GAS.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the license, or
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(at your option) any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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.text
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// Check #0 with scalar register.
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fcmeq s0, s30, #0
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fcmge s1, s29, #0
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fcmgt s2, s28, #0
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fcmle s3, s27, #0
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fcmlt s4, s26, #0
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fcmeq d0, d30, #0
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fcmge d1, d29, #0
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fcmgt d2, d28, #0
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fcmle d3, d27, #0
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fcmlt d4, d26, #0
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// Check #0 with vector register.
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fcmeq v0.2s, v30.2s, #0
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fcmge v1.4s, v29.4s, #0
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fcmgt v2.2d, v28.2d, #0
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fcmle v3.2s, v27.2s, #0
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fcmlt v4.4s, v26.4s, #0
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// Check #0.0 with scalar register.
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fcmeq s0, s30, #0.0
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fcmge s1, s29, #0.0
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fcmgt s2, s28, #0.0
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fcmle s3, s27, #0.0
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fcmlt s4, s26, #0.0
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fcmeq d0, d30, #0.0
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fcmge d1, d29, #0.0
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fcmgt d2, d28, #0.0
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fcmle d3, d27, #0.0
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fcmlt d4, d26, #0.0
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// Check #0.0 with vector register.
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fcmeq v0.2s, v30.2s, #0.0
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fcmge v1.4s, v29.4s, #0.0
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fcmgt v2.2d, v28.2d, #0.0
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fcmle v3.2s, v27.2s, #0.0
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fcmlt v4.4s, v26.4s, #0.0
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@ -1,3 +1,8 @@
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2014-02-27 Jiong Wang <jiong.wang@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
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FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
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2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-opc.c (print_register_offset_address): Call
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@ -1403,9 +1403,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
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{"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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{"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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{"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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{"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
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{"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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{"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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{"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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@ -1439,8 +1439,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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{"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS},
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{"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS},
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{"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
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{"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
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{"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
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{"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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{"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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{"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
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@ -1650,9 +1650,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
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{"fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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@ -1669,8 +1669,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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{"fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
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{"fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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{"frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
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