gas/
2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE, EPT and MOVBE. * config/tc-i386.c (cpu_arch): Add .movbe and .ept. (md_show_usage): Add .movbe and .ept. * doc/c-i386.texi: Add movbe and ept to -march=. Document .movbe and .ept. gas/testsuite/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept, ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel, x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and x86-64-inval-ept. * gas/i386/arch-10.s: Add movbe and invept. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/ept.d: New file * gas/i386/ept-intel.d: Likewise. * gas/i386/ept.s: Likewise. * gas/i386/inval-ept.l: Likewise. * gas/i386/inval-ept.s: Likewise. * gas/i386/inval-movbe.l: Likewise. * gas/i386/inval-movbe.s: Likewise. * gas/i386/movbe.d: Likewise. * gas/i386/movbe-intel.d: Likewise. * gas/i386/movbe.s: Likewise. * gas/i386/x86-64-inval-ept.l: Likewise. * gas/i386/x86-64-inval-ept.s: Likewise. * gas/i386/x86-64-inval-movbe.l: Likewise. * gas/i386/x86-64-inval-movbe.s: Likewise. * gas/i386/x86-64-ept.d: Likewise. * gas/i386/x86-64-ept-intel.d: Likewise. * gas/i386/x86-64-ept.s: Likewise. * gas/i386/x86-64-movbe.d: Likewise. * gas/i386/x86-64-movbe-intel.d: Likewise. * gas/i386/x86-64-movbe.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOVBE_Fixup): New. (Mo): Likewise. (PREFIX_0F3880): Likewise. (PREFIX_0F3881): Likewise. (PREFIX_0F38F0): Updated. (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and CPU_EPT_FLAGS. (cpu_flags): Add CpuMovbe and CpuEPT. * i386-opc.h (CpuMovbe): New. (CpuEPT): Likewise. (CpuLM): Updated. (i386_cpu_flags): Add cpumovbe and cpuept. * i386-opc.tbl: Add entries for movbe and EPT instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
237fc4c9cd
commit
f1f8f695c0
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@ -1,3 +1,13 @@
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2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
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* NEWS: Mention XSAVE, EPT and MOVBE.
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* config/tc-i386.c (cpu_arch): Add .movbe and .ept.
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(md_show_usage): Add .movbe and .ept.
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* doc/c-i386.texi: Add movbe and ept to -march=. Document
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.movbe and .ept.
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2008-04-29 David S. Miller <davem@davemloft.net>
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* config/tc-sparc.c (v9a_asr_table): Fix order of softint entries.
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2
gas/NEWS
2
gas/NEWS
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@ -10,7 +10,7 @@
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* New command line option -msse2avx for x86 target to encode SSE
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instructions with VEX prefix.
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* Add Intel XSAVE, AES, PCLMUL, AVX/FMA support for x86 target.
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* Add Intel XSAVE, EPT, MOVBE, AES, PCLMUL, AVX/FMA support for x86 target.
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* New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
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-mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg,
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@ -661,6 +661,10 @@ static const arch_entry cpu_arch[] =
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CPU_PCLMUL_FLAGS },
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{ ".fma", PROCESSOR_UNKNOWN,
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CPU_FMA_FLAGS },
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{ ".movbe", PROCESSOR_UNKNOWN,
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CPU_MOVBE_FLAGS },
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{ ".ept", PROCESSOR_UNKNOWN,
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CPU_EPT_FLAGS },
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{ ".3dnow", PROCESSOR_UNKNOWN,
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CPU_3DNOW_FLAGS },
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{ ".3dnowa", PROCESSOR_UNKNOWN,
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@ -8096,8 +8100,8 @@ md_show_usage (stream)
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generic32, generic64\n\
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EXTENSION is combination of:\n\
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mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
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avx, vmx, smx, xsave, aes, pclmul, fma, 3dnow,\n\
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3dnowa, sse4a, sse5, svme, abm, padlock\n"));
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avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
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3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
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fprintf (stream, _("\
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-mtune=CPU optimize for CPU, CPU is one of:\n\
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i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
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@ -127,6 +127,8 @@ accept various extension mnemonics. For example,
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@code{aes},
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@code{pclmul},
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@code{fma},
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@code{movbe},
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@code{ept},
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@code{3dnow},
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@code{3dnowa},
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@code{sse4a},
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@ -844,7 +846,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
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@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
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@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma}
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@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
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@item @samp{.ept}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.svme} @tab @samp{.abm}
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@item @samp{.padlock}
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@ -1,3 +1,41 @@
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2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept,
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ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel,
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x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and
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x86-64-inval-ept.
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* gas/i386/arch-10.s: Add movbe and invept.
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* gas/i386/x86-64-arch-2.s: Likewise.
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* gas/i386/ept.d: New file
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* gas/i386/ept-intel.d: Likewise.
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* gas/i386/ept.s: Likewise.
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* gas/i386/inval-ept.l: Likewise.
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* gas/i386/inval-ept.s: Likewise.
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* gas/i386/inval-movbe.l: Likewise.
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* gas/i386/inval-movbe.s: Likewise.
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* gas/i386/movbe.d: Likewise.
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* gas/i386/movbe-intel.d: Likewise.
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* gas/i386/movbe.s: Likewise.
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* gas/i386/x86-64-inval-ept.l: Likewise.
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* gas/i386/x86-64-inval-ept.s: Likewise.
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* gas/i386/x86-64-inval-movbe.l: Likewise.
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* gas/i386/x86-64-inval-movbe.s: Likewise.
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* gas/i386/x86-64-ept.d: Likewise.
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* gas/i386/x86-64-ept-intel.d: Likewise.
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* gas/i386/x86-64-ept.s: Likewise.
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* gas/i386/x86-64-movbe.d: Likewise.
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* gas/i386/x86-64-movbe-intel.d: Likewise.
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* gas/i386/x86-64-movbe.s: Likewise.
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* gas/i386/arch-10.d: Updated.
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* gas/i386/arch-10-1.l: Likewise.
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* gas/i386/arch-10-2.l: Likewise.
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* gas/i386/arch-10-3.l: Likewise.
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* gas/i386/arch-10-4.l: Likewise.
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* gas/i386/x86-64-arch-2.d: Likewise.
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2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
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* gas/mips/mips4.s: Split out fp instruction from here ...
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@ -21,6 +21,8 @@
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.*:42: Error: .*
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.*:44: Error: .*
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.*:46: Error: .*
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.*:48: Error: .*
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.*:50: Error: .*
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GAS LISTING .*
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@ -57,17 +59,21 @@ GAS LISTING .*
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*33[ ]+\# 3DNow
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[ ]*34[ ]+pmulhrw %mm4,%mm3
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[ ]*35[ ]+\# 3DNow Extensions
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[ ]*36[ ]+pswapd %mm4,%mm3
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[ ]*37[ ]+\# SSE4a
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[ ]*38[ ]+insertq %xmm2,%xmm1
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[ ]*39[ ]+\# SVME
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[ ]*40[ ]+vmload
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[ ]*41[ ]+\# ABM
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[ ]*42[ ]+lzcnt %ecx,%ebx
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[ ]*43[ ]+\# SSE5
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[ ]*44[ ]+frczss %xmm2, %xmm1
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[ ]*45[ ]+\# PadLock
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[ ]*46[ ]+xstorerng
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[ ]*33[ ]+\# MOVBE
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[ ]*34[ ]+movbe \(%ecx\),%ebx
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[ ]*35[ ]+\# EPT
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[ ]*36[ ]+invept \(%ecx\),%ebx
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[ ]*37[ ]+\# 3DNow
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[ ]*38[ ]+pmulhrw %mm4,%mm3
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[ ]*39[ ]+\# 3DNow Extensions
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[ ]*40[ ]+pswapd %mm4,%mm3
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[ ]*41[ ]+\# SSE4a
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[ ]*42[ ]+insertq %xmm2,%xmm1
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[ ]*43[ ]+\# SVME
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[ ]*44[ ]+vmload
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[ ]*45[ ]+\# ABM
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[ ]*46[ ]+lzcnt %ecx,%ebx
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[ ]*47[ ]+\# SSE5
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[ ]*48[ ]+frczss %xmm2, %xmm1
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[ ]*49[ ]+\# PadLock
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[ ]*50[ ]+xstorerng
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@ -20,6 +20,8 @@
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.*:42: Error: .*
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.*:44: Error: .*
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.*:46: Error: .*
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.*:48: Error: .*
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.*:50: Error: .*
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GAS LISTING .*
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@ -56,17 +58,21 @@ GAS LISTING .*
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*33[ ]+\# 3DNow
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[ ]*34[ ]+pmulhrw %mm4,%mm3
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[ ]*35[ ]+\# 3DNow Extensions
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[ ]*36[ ]+pswapd %mm4,%mm3
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[ ]*37[ ]+\# SSE4a
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[ ]*38[ ]+insertq %xmm2,%xmm1
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[ ]*39[ ]+\# SVME
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[ ]*40[ ]+vmload
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[ ]*41[ ]+\# ABM
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[ ]*42[ ]+lzcnt %ecx,%ebx
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[ ]*43[ ]+\# SSE5
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[ ]*44[ ]+frczss %xmm2, %xmm1
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[ ]*45[ ]+\# PadLock
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[ ]*46[ ]+xstorerng
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[ ]*33[ ]+\# MOVBE
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[ ]*34[ ]+movbe \(%ecx\),%ebx
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[ ]*35[ ]+\# EPT
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[ ]*36[ ]+invept \(%ecx\),%ebx
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[ ]*37[ ]+\# 3DNow
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[ ]*38[ ]+pmulhrw %mm4,%mm3
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[ ]*39[ ]+\# 3DNow Extensions
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[ ]*40[ ]+pswapd %mm4,%mm3
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[ ]*41[ ]+\# SSE4a
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[ ]*42[ ]+insertq %xmm2,%xmm1
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[ ]*43[ ]+\# SVME
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[ ]*44[ ]+vmload
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[ ]*45[ ]+\# ABM
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[ ]*46[ ]+lzcnt %ecx,%ebx
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[ ]*47[ ]+\# SSE5
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[ ]*48[ ]+frczss %xmm2, %xmm1
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[ ]*49[ ]+\# PadLock
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[ ]*50[ ]+xstorerng
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@ -13,6 +13,8 @@
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.*:42: Error: .*
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.*:44: Error: .*
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.*:46: Error: .*
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.*:48: Error: .*
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.*:50: Error: .*
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GAS LISTING .*
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@ -52,17 +54,21 @@ GAS LISTING .*
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*33[ ]+\# 3DNow
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[ ]*34[ ]+pmulhrw %mm4,%mm3
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[ ]*35[ ]+\# 3DNow Extensions
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[ ]*36[ ]+pswapd %mm4,%mm3
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[ ]*37[ ]+\# SSE4a
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[ ]*38[ ]+insertq %xmm2,%xmm1
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[ ]*39[ ]+\# SVME
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[ ]*40[ ]+vmload
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[ ]*41[ ]+\# ABM
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[ ]*42[ ]+lzcnt %ecx,%ebx
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[ ]*43[ ]+\# SSE5
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[ ]*44[ ]+frczss %xmm2, %xmm1
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[ ]*45[ ]+\# PadLock
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[ ]*46[ ]+xstorerng
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[ ]*33[ ]+\# MOVBE
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[ ]*34[ ]+movbe \(%ecx\),%ebx
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[ ]*35[ ]+\# EPT
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[ ]*36[ ]+invept \(%ecx\),%ebx
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[ ]*37[ ]+\# 3DNow
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[ ]*38[ ]+pmulhrw %mm4,%mm3
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[ ]*39[ ]+\# 3DNow Extensions
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[ ]*40[ ]+pswapd %mm4,%mm3
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[ ]*41[ ]+\# SSE4a
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[ ]*42[ ]+insertq %xmm2,%xmm1
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[ ]*43[ ]+\# SVME
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[ ]*44[ ]+vmload
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[ ]*45[ ]+\# ABM
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[ ]*46[ ]+lzcnt %ecx,%ebx
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[ ]*47[ ]+\# SSE5
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[ ]*48[ ]+frczss %xmm2, %xmm1
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[ ]*49[ ]+\# PadLock
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[ ]*50[ ]+xstorerng
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@ -11,6 +11,8 @@
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.*:42: Error: .*
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.*:44: Error: .*
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.*:46: Error: .*
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.*:48: Error: .*
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.*:50: Error: .*
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GAS LISTING .*
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@ -50,17 +52,21 @@ GAS LISTING .*
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*33[ ]+\# 3DNow
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[ ]*34[ ]+pmulhrw %mm4,%mm3
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[ ]*35[ ]+\# 3DNow Extensions
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[ ]*36[ ]+pswapd %mm4,%mm3
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[ ]*37[ ]+\# SSE4a
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[ ]*38[ ]+insertq %xmm2,%xmm1
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[ ]*39[ ]+\# SVME
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[ ]*40[ ]+vmload
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[ ]*41[ ]+\# ABM
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[ ]*42[ ]+lzcnt %ecx,%ebx
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[ ]*43[ ]+\# SSE5
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[ ]*44[ ]+frczss %xmm2, %xmm1
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[ ]*45[ ]+\# PadLock
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[ ]*46[ ]+xstorerng
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[ ]*33[ ]+\# MOVBE
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[ ]*34[ ]+movbe \(%ecx\),%ebx
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[ ]*35[ ]+\# EPT
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[ ]*36[ ]+invept \(%ecx\),%ebx
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[ ]*37[ ]+\# 3DNow
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[ ]*38[ ]+pmulhrw %mm4,%mm3
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[ ]*39[ ]+\# 3DNow Extensions
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[ ]*40[ ]+pswapd %mm4,%mm3
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[ ]*41[ ]+\# SSE4a
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[ ]*42[ ]+insertq %xmm2,%xmm1
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[ ]*43[ ]+\# SVME
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[ ]*44[ ]+vmload
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[ ]*45[ ]+\# ABM
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[ ]*46[ ]+lzcnt %ecx,%ebx
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[ ]*47[ ]+\# SSE5
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[ ]*48[ ]+frczss %xmm2, %xmm1
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[ ]*49[ ]+\# PadLock
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[ ]*50[ ]+xstorerng
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@ -1,4 +1,4 @@
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#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
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#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+sse5+3dnowa+svme+padlock
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#objdump: -dw
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#name: i386 arch 10
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@ -22,6 +22,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
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[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
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[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
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[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
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@ -30,6 +30,10 @@ aesenc (%ecx),%xmm0
|
|||
pclmulqdq $8,%xmm1,%xmm0
|
||||
# FMA
|
||||
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
# MOVBE
|
||||
movbe (%ecx),%ebx
|
||||
# EPT
|
||||
invept (%ecx),%ebx
|
||||
# 3DNow
|
||||
pmulhrw %mm4,%mm3
|
||||
# 3DNow Extensions
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
#objdump: -dwMintel
|
||||
#name: i386 EPT (Intel disassembly)
|
||||
#source: ept.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept ebx,OWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid ebx,OWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept ebx,OWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid ebx,OWORD PTR \[ecx\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#objdump: -dw
|
||||
#name: i386 EPT
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid \(%ecx\),%ebx
|
||||
#pass
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
# Check EPT instructions
|
||||
.text
|
||||
_start:
|
||||
invept (%ecx), %ebx
|
||||
invvpid (%ecx), %ebx
|
||||
|
||||
.intel_syntax noprefix
|
||||
invept ebx, oword ptr [ecx]
|
||||
invvpid ebx, oword ptr [ecx]
|
||||
|
|
@ -128,6 +128,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "sse-check-warn"
|
||||
run_list_test "sse-check-error" "-msse-check=error -I${srcdir}/$subdir -al"
|
||||
run_dump_test "sse-noavx"
|
||||
run_dump_test "movbe"
|
||||
run_dump_test "movbe-intel"
|
||||
run_list_test "inval-movbe" "-al"
|
||||
run_dump_test "ept"
|
||||
run_dump_test "ept-intel"
|
||||
run_list_test "inval-ept" "-al"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
# so we only run them for ELF and COFF targets.
|
||||
|
|
@ -258,6 +264,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-sse-check-warn"
|
||||
run_list_test "x86-64-sse-check-error" "-msse-check=error -I${srcdir}/$subdir -al"
|
||||
run_dump_test "x86-64-sse-noavx"
|
||||
run_dump_test "x86-64-movbe"
|
||||
run_dump_test "x86-64-movbe-intel"
|
||||
run_list_test "x86-64-inval-movbe" "-al"
|
||||
run_dump_test "x86-64-ept"
|
||||
run_dump_test "x86-64-ept-intel"
|
||||
run_list_test "x86-64-inval-ept" "-al"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,33 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:16: Error: .*
|
||||
.*:17: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check illegal EPT instructions
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+_start:
|
||||
[ ]*4[ ]+invept \(%ecx\), %bx
|
||||
[ ]*5[ ]+invept %ebx, \(%ecx\)
|
||||
[ ]*6[ ]+invept %ebx, %ecx
|
||||
[ ]*7[ ]+invvpid \(%ecx\), %bx
|
||||
[ ]*8[ ]+invvpid %ebx, \(%ecx\)
|
||||
[ ]*9[ ]+invvpid %ebx, %ecx
|
||||
[ ]*10[ ]+
|
||||
[ ]*11[ ]+\.intel_syntax noprefix
|
||||
[ ]*12[ ]+invept bx, oword ptr \[ecx\]
|
||||
[ ]*13[ ]+invept oword ptr \[ecx\], ebx
|
||||
[ ]*14[ ]+invept ecx, ebx
|
||||
[ ]*15[ ]+invvpid bx, oword ptr \[ecx\]
|
||||
[ ]*16[ ]+invvpid oword ptr \[ecx\], ebx
|
||||
[ ]*17[ ]+invvpid ecx, ebx
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# Check illegal EPT instructions
|
||||
.text
|
||||
_start:
|
||||
invept (%ecx), %bx
|
||||
invept %ebx, (%ecx)
|
||||
invept %ebx, %ecx
|
||||
invvpid (%ecx), %bx
|
||||
invvpid %ebx, (%ecx)
|
||||
invvpid %ebx, %ecx
|
||||
|
||||
.intel_syntax noprefix
|
||||
invept bx, oword ptr [ecx]
|
||||
invept oword ptr [ecx], ebx
|
||||
invept ecx, ebx
|
||||
invvpid bx, oword ptr [ecx]
|
||||
invvpid oword ptr [ecx], ebx
|
||||
invvpid ecx, ebx
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:10: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check illegal movbe
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+foo:
|
||||
[ ]*4[ ]+movbe \(%ecx\),%bl
|
||||
[ ]*5[ ]+movbe %ecx,%ebx
|
||||
[ ]*6[ ]+movbe %bx,%ecx
|
||||
[ ]*7[ ]+movbe %bl,\(%ecx\)
|
||||
[ ]*8[ ]+
|
||||
[ ]*9[ ]+\.intel_syntax noprefix
|
||||
[ ]*10[ ]+movbe bl, byte ptr \[ecx\]
|
||||
[ ]*11[ ]+movbe ebx, ecx
|
||||
[ ]*12[ ]+movbe ecx, bx
|
||||
[ ]*13[ ]+movbe byte ptr \[ecx\], bl
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
# Check illegal movbe
|
||||
.text
|
||||
foo:
|
||||
movbe (%ecx),%bl
|
||||
movbe %ecx,%ebx
|
||||
movbe %bx,%ecx
|
||||
movbe %bl,(%ecx)
|
||||
|
||||
.intel_syntax noprefix
|
||||
movbe bl, byte ptr [ecx]
|
||||
movbe ebx, ecx
|
||||
movbe ecx, bx
|
||||
movbe byte ptr [ecx], bl
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
#objdump: -dwMintel
|
||||
#name: i386 movbe (Intel disassembly)
|
||||
#source: movbe.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe bx,WORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe ebx,DWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe WORD PTR \[ecx\],bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe DWORD PTR \[ecx\],ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe bx,WORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe ebx,DWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe WORD PTR \[ecx\],bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe DWORD PTR \[ecx\],ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe bx,WORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe ebx,DWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe WORD PTR \[ecx\],bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe DWORD PTR \[ecx\],ebx
|
||||
#pass
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
#objdump: -dw
|
||||
#name: i386 movbe
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe \(%ecx\),%bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe %bx,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe %ebx,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe \(%ecx\),%bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe %bx,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe %ebx,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe \(%ecx\),%bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe %bx,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe %ebx,\(%ecx\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# Check movbe
|
||||
.text
|
||||
foo:
|
||||
movbe (%ecx),%bx
|
||||
movbe (%ecx),%ebx
|
||||
movbe %bx,(%ecx)
|
||||
movbe %ebx,(%ecx)
|
||||
movbew (%ecx),%bx
|
||||
movbel (%ecx),%ebx
|
||||
movbew %bx,(%ecx)
|
||||
movbel %ebx,(%ecx)
|
||||
|
||||
.intel_syntax noprefix
|
||||
movbe bx, word ptr [ecx]
|
||||
movbe ebx, dword ptr [ecx]
|
||||
movbe word ptr [ecx], bx
|
||||
movbe dword ptr [ecx], ebx
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
|
||||
#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+sse5+3dnowa+svme+padlock
|
||||
#objdump: -dw
|
||||
#name: x86-64 arch 2
|
||||
|
||||
|
|
@ -22,6 +22,8 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
|
|
|
|||
|
|
@ -30,6 +30,10 @@ aesenc (%rcx),%xmm0
|
|||
pclmulqdq $8,%xmm1,%xmm0
|
||||
# FMA
|
||||
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
# MOVBE
|
||||
movbe (%rcx),%ebx
|
||||
# EPT
|
||||
invept (%rcx),%rbx
|
||||
# 3DNow
|
||||
pmulhrw %mm4,%mm3
|
||||
# 3DNow Extensions
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
#objdump: -drwMintel
|
||||
#name: x86-64 EPT (Intel mode)
|
||||
#source: x86-64-ept.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept rbx,OWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 80 19 invept r11,OWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid rbx,OWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 81 19 invvpid r11,OWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept rbx,OWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 80 19 invept r11,OWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid rbx,OWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 81 19 invvpid r11,OWORD PTR \[rcx\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 EPT
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 80 19 invept \(%rcx\),%r11
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 81 19 invvpid \(%rcx\),%r11
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 80 19 invept \(%rcx\),%r11
|
||||
[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 66 44 0f 38 81 19 invvpid \(%rcx\),%r11
|
||||
#pass
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
# Check 64bit EPT instructions
|
||||
.text
|
||||
_start:
|
||||
invept (%rcx), %rbx
|
||||
invept (%rcx), %r11
|
||||
invvpid (%rcx), %rbx
|
||||
invvpid (%rcx), %r11
|
||||
|
||||
.intel_syntax noprefix
|
||||
invept rbx, oword ptr [rcx]
|
||||
invept r11, oword ptr [rcx]
|
||||
invvpid rbx, oword ptr [rcx]
|
||||
invvpid r11, oword ptr [rcx]
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:10: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:16: Error: .*
|
||||
.*:17: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:21: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check illegal EPT instructions in 64bit mode\.
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+_start:
|
||||
[ ]*4[ ]+invept \(%rcx\), %bx
|
||||
[ ]*5[ ]+invept \(%rcx\), %ebx
|
||||
[ ]*6[ ]+invept %rbx, \(%rcx\)
|
||||
[ ]*7[ ]+invept %rbx, %rcx
|
||||
[ ]*8[ ]+invvpid \(%rcx\), %bx
|
||||
[ ]*9[ ]+invvpid \(%rcx\), %ebx
|
||||
[ ]*10[ ]+invvpid %rbx, \(%rcx\)
|
||||
[ ]*11[ ]+invvpid %rbx, %rcx
|
||||
[ ]*12[ ]+
|
||||
[ ]*13[ ]+\.intel_syntax noprefix
|
||||
[ ]*14[ ]+invept bx, oword ptr \[rcx\]
|
||||
[ ]*15[ ]+invept ebx, oword ptr \[rcx\]
|
||||
[ ]*16[ ]+invept oword ptr \[rcx\], rbx
|
||||
[ ]*17[ ]+invept rcx, rbx
|
||||
[ ]*18[ ]+invvpid bx, oword ptr \[rcx\]
|
||||
[ ]*19[ ]+invvpid ebx, oword ptr \[rcx\]
|
||||
[ ]*20[ ]+invvpid oword ptr \[rcx\], rbx
|
||||
[ ]*21[ ]+invvpid rcx, rbx
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# Check illegal EPT instructions in 64bit mode.
|
||||
.text
|
||||
_start:
|
||||
invept (%rcx), %bx
|
||||
invept (%rcx), %ebx
|
||||
invept %rbx, (%rcx)
|
||||
invept %rbx, %rcx
|
||||
invvpid (%rcx), %bx
|
||||
invvpid (%rcx), %ebx
|
||||
invvpid %rbx, (%rcx)
|
||||
invvpid %rbx, %rcx
|
||||
|
||||
.intel_syntax noprefix
|
||||
invept bx, oword ptr [rcx]
|
||||
invept ebx, oword ptr [rcx]
|
||||
invept oword ptr [rcx], rbx
|
||||
invept rcx, rbx
|
||||
invvpid bx, oword ptr [rcx]
|
||||
invvpid ebx, oword ptr [rcx]
|
||||
invvpid oword ptr [rcx], rbx
|
||||
invvpid rcx, rbx
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check illegal movbe in 64bit mode\.
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+foo:
|
||||
[ ]*4[ ]+movbe \(%rcx\),%bl
|
||||
[ ]*5[ ]+movbe %ecx,%ebx
|
||||
[ ]*6[ ]+movbe %bx,%rcx
|
||||
[ ]*7[ ]+movbe %rbx,%rcx
|
||||
[ ]*8[ ]+movbe %bl,\(%rcx\)
|
||||
[ ]*9[ ]+
|
||||
[ ]*10[ ]+\.intel_syntax noprefix
|
||||
[ ]*11[ ]+movbe bl, byte ptr \[rcx\]
|
||||
[ ]*12[ ]+movbe ebx, ecx
|
||||
[ ]*13[ ]+movbe rcx, bx
|
||||
[ ]*14[ ]+movbe rcx, rbx
|
||||
[ ]*15[ ]+movbe byte ptr \[rcx\], bl
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Check illegal movbe in 64bit mode.
|
||||
.text
|
||||
foo:
|
||||
movbe (%rcx),%bl
|
||||
movbe %ecx,%ebx
|
||||
movbe %bx,%rcx
|
||||
movbe %rbx,%rcx
|
||||
movbe %bl,(%rcx)
|
||||
|
||||
.intel_syntax noprefix
|
||||
movbe bl, byte ptr [rcx]
|
||||
movbe ebx, ecx
|
||||
movbe rcx, bx
|
||||
movbe rcx, rbx
|
||||
movbe byte ptr [rcx], bl
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
#objdump: -drwMintel
|
||||
#name: x86-64 movbe (Intel mode)
|
||||
#source: x86-64-movbe.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f0 29 movbe r13w,WORD PTR \[r9\]
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f0 29 movbe r13d,DWORD PTR \[r9\]
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f0 29 movbe r13,QWORD PTR \[r9\]
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f1 29 movbe WORD PTR \[r9\],r13w
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f1 29 movbe DWORD PTR \[r9\],r13d
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f1 29 movbe QWORD PTR \[r9\],r13
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f0 29 movbe r13w,WORD PTR \[r9\]
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f0 29 movbe r13d,DWORD PTR \[r9\]
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f0 29 movbe r13,QWORD PTR \[r9\]
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f1 29 movbe WORD PTR \[r9\],r13w
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f1 29 movbe DWORD PTR \[r9\],r13d
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f1 29 movbe QWORD PTR \[r9\],r13
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe bx,WORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe ebx,DWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 48 0f 38 f0 19 movbe rbx,QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe WORD PTR \[rcx\],bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe DWORD PTR \[rcx\],ebx
|
||||
[ ]*[a-f0-9]+: 48 0f 38 f1 19 movbe QWORD PTR \[rcx\],rbx
|
||||
#pass
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 movbe
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f0 29 movbe \(%r9\),%r13w
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f0 29 movbe \(%r9\),%r13d
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f0 29 movbe \(%r9\),%r13
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f1 29 movbe %r13w,\(%r9\)
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f1 29 movbe %r13d,\(%r9\)
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f1 29 movbe %r13,\(%r9\)
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f0 29 movbe \(%r9\),%r13w
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f0 29 movbe \(%r9\),%r13d
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f0 29 movbe \(%r9\),%r13
|
||||
[ ]*[a-f0-9]+: 66 45 0f 38 f1 29 movbe %r13w,\(%r9\)
|
||||
[ ]*[a-f0-9]+: 45 0f 38 f1 29 movbe %r13d,\(%r9\)
|
||||
[ ]*[a-f0-9]+: 4d 0f 38 f1 29 movbe %r13,\(%r9\)
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f0 19 movbe \(%rcx\),%bx
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
|
||||
[ ]*[a-f0-9]+: 48 0f 38 f0 19 movbe \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f1 19 movbe %bx,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: 0f 38 f1 19 movbe %ebx,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: 48 0f 38 f1 19 movbe %rbx,\(%rcx\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
# Check 64bit movbe
|
||||
.text
|
||||
foo:
|
||||
movbe (%r9),%r13w
|
||||
movbe (%r9),%r13d
|
||||
movbe (%r9),%r13
|
||||
movbe %r13w,(%r9)
|
||||
movbe %r13d,(%r9)
|
||||
movbe %r13,(%r9)
|
||||
movbew (%r9),%r13w
|
||||
movbel (%r9),%r13d
|
||||
movbeq (%r9),%r13
|
||||
movbew %r13w,(%r9)
|
||||
movbel %r13d,(%r9)
|
||||
movbeq %r13,(%r9)
|
||||
|
||||
.intel_syntax noprefix
|
||||
movbe bx, word ptr [rcx]
|
||||
movbe ebx, dword ptr [rcx]
|
||||
movbe rbx, qword ptr [rcx]
|
||||
movbe word ptr [rcx], bx
|
||||
movbe dword ptr [rcx], ebx
|
||||
movbe qword ptr [rcx], rbx
|
||||
|
|
@ -1,3 +1,27 @@
|
|||
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (MOVBE_Fixup): New.
|
||||
(Mo): Likewise.
|
||||
(PREFIX_0F3880): Likewise.
|
||||
(PREFIX_0F3881): Likewise.
|
||||
(PREFIX_0F38F0): Updated.
|
||||
(prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
|
||||
PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
|
||||
(three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
|
||||
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
|
||||
CPU_EPT_FLAGS.
|
||||
(cpu_flags): Add CpuMovbe and CpuEPT.
|
||||
|
||||
* i386-opc.h (CpuMovbe): New.
|
||||
(CpuEPT): Likewise.
|
||||
(CpuLM): Updated.
|
||||
(i386_cpu_flags): Add cpumovbe and cpuept.
|
||||
|
||||
* i386-opc.tbl: Add entries for movbe and EPT instructions.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
|
||||
|
||||
* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
|
||||
|
|
|
|||
|
|
@ -121,6 +121,7 @@ static void OP_DREX4 (int, int);
|
|||
static void OP_DREX3 (int, int);
|
||||
static void OP_DREX_ICMP (int, int);
|
||||
static void OP_DREX_FCMP (int, int);
|
||||
static void MOVBE_Fixup (int, int);
|
||||
|
||||
struct dis_private {
|
||||
/* Points to first byte not fetched. */
|
||||
|
|
@ -254,6 +255,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define Ma { OP_M, a_mode }
|
||||
#define Mb { OP_M, b_mode }
|
||||
#define Md { OP_M, d_mode }
|
||||
#define Mo { OP_M, o_mode }
|
||||
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
|
||||
#define Mq { OP_M, q_mode }
|
||||
#define Mx { OP_M, x_mode }
|
||||
|
|
@ -745,7 +747,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define PREFIX_0F383F (PREFIX_0F383E + 1)
|
||||
#define PREFIX_0F3840 (PREFIX_0F383F + 1)
|
||||
#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
|
||||
#define PREFIX_0F38DB (PREFIX_0F3841 + 1)
|
||||
#define PREFIX_0F3880 (PREFIX_0F3841 + 1)
|
||||
#define PREFIX_0F3881 (PREFIX_0F3880 + 1)
|
||||
#define PREFIX_0F38DB (PREFIX_0F3881 + 1)
|
||||
#define PREFIX_0F38DC (PREFIX_0F38DB + 1)
|
||||
#define PREFIX_0F38DD (PREFIX_0F38DC + 1)
|
||||
#define PREFIX_0F38DE (PREFIX_0F38DD + 1)
|
||||
|
|
@ -3003,6 +3007,22 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_0F3880 */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "invept", { Gm, Mo } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_0F3881 */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "invvpid", { Gm, Mo } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_0F38DB */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -3045,17 +3065,17 @@ static const struct dis386 prefix_table[][4] = {
|
|||
|
||||
/* PREFIX_0F38F0 */
|
||||
{
|
||||
{ "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
|
||||
{ "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
|
||||
},
|
||||
|
||||
/* PREFIX_0F38F1 */
|
||||
{
|
||||
{ "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
|
||||
{ "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
|
||||
},
|
||||
|
||||
|
|
@ -5832,8 +5852,8 @@ static const struct dis386 three_byte_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 80 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ PREFIX_TABLE (PREFIX_0F3880) },
|
||||
{ PREFIX_TABLE (PREFIX_0F3881) },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -13700,3 +13720,36 @@ VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
|
|||
scratchbuf[0] = '\0';
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
MOVBE_Fixup (int bytemode, int sizeflag)
|
||||
{
|
||||
/* Add proper suffix to "movbe". */
|
||||
char *p = obuf + strlen (obuf);
|
||||
|
||||
switch (bytemode)
|
||||
{
|
||||
case v_mode:
|
||||
if (intel_syntax)
|
||||
break;
|
||||
|
||||
USED_REX (REX_W);
|
||||
if (sizeflag & SUFFIX_ALWAYS)
|
||||
{
|
||||
if (rex & REX_W)
|
||||
*p++ = 'q';
|
||||
else if (sizeflag & DFLAG)
|
||||
*p++ = 'l';
|
||||
else
|
||||
*p++ = 'w';
|
||||
}
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
break;
|
||||
default:
|
||||
oappend (INTERNAL_DISASSEMBLER_ERROR);
|
||||
break;
|
||||
}
|
||||
*p = '\0';
|
||||
|
||||
OP_M (bytemode, sizeflag);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -108,6 +108,10 @@ static initializer cpu_flag_init [] =
|
|||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" },
|
||||
{ "CPU_FMA_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
|
||||
{ "CPU_MOVBE_FLAGS",
|
||||
"CpuMovbe" },
|
||||
{ "CPU_EPT_FLAGS",
|
||||
"CpuEPT" },
|
||||
{ "CPU_3DNOW_FLAGS",
|
||||
"CpuMMX|Cpu3dnow" },
|
||||
{ "CPU_3DNOWA_FLAGS",
|
||||
|
|
@ -266,6 +270,8 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuPCLMUL),
|
||||
BITFIELD (CpuFMA),
|
||||
BITFIELD (CpuLM),
|
||||
BITFIELD (CpuMovbe),
|
||||
BITFIELD (CpuEPT),
|
||||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
#ifdef CpuUnused
|
||||
|
|
|
|||
|
|
@ -20,171 +20,179 @@
|
|||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE5_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -90,8 +90,12 @@
|
|||
#define CpuPCLMUL (CpuAES + 1)
|
||||
/* FMA support required */
|
||||
#define CpuFMA (CpuPCLMUL + 1)
|
||||
/* MOVBE Instuction support required */
|
||||
#define CpuMovbe (CpuFMA + 1)
|
||||
/* EPT Instructions required */
|
||||
#define CpuEPT (CpuMovbe + 1)
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
#define CpuLM (CpuFMA + 1)
|
||||
#define CpuLM (CpuEPT + 1)
|
||||
/* 64bit support required */
|
||||
#define Cpu64 (CpuLM + 1)
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -144,6 +148,8 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuaes:1;
|
||||
unsigned int cpupclmul:1;
|
||||
unsigned int cpufma:1;
|
||||
unsigned int cpumovbe:1;
|
||||
unsigned int cpuept:1;
|
||||
unsigned int cpulm:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
|
|
|
|||
|
|
@ -53,6 +53,10 @@ mov, 2, 0xf24, None, 2, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sS
|
|||
movabs, 2, 0xa0, None, 1, Cpu64, D|W|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
|
||||
movabs, 2, 0xb0, None, 1, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Imm64, Reg64 }
|
||||
|
||||
// Move after swapping the bytes
|
||||
movbe, 2, 0x0f38f0, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
movbe, 2, 0x0f38f1, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
||||
// Move with sign extend.
|
||||
// "movsbl" & "movsbw" must not be unified into "movsb" to avoid
|
||||
// conflict with the "movs" string move instruction.
|
||||
|
|
@ -1531,6 +1535,13 @@ vmxon, 1, 0xf30fc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_
|
|||
|
||||
getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
// EPT instructions.
|
||||
|
||||
invept, 2, 0x660f3880, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
|
||||
invept, 2, 0x660f3880, None, 3, CpuEPT|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
|
||||
invvpid, 2, 0x660f3881, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
|
||||
invvpid, 2, 0x660f3881, None, 3, CpuEPT|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
|
||||
|
||||
// SSSE3 instructions.
|
||||
|
||||
phaddw, 2, 0x6601, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
|
|
|
|||
4942
opcodes/i386-tbl.h
4942
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue