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include/opcode/ 

* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
	(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
	(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
	(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
	(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
	(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
	(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
	(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
	(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
	(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
	(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
	(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
	(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
	Rename to...
	(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
	(M_USD_AB): ...these.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
	and SD A(B) macros up.
	* micromips-opc.c (micromips_opcodes): Likewise.

gas/
	* config/tc-mips.c (gprel16_reloc_p): New function.
	(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
	BFD_RELOC_UNUSED.
	(offset_high_part, small_offset_p): New functions.
	(nacro): Use them.  Remove *_OB and *_DOB cases.  For single-
	register load and store macros, handle the 16-bit offset case first.
	If a 16-bit offset is not suitable for the instruction we're
	generating, load it into the temporary register using
	ADDRESS_ADDI_INSN.  Make the M_LI_DD code fall through into the
	M_L_DAB code once the address has been constructed.  For double load
	and store macros, again handle the 16-bit offset case first.
	If the second register cannot be accessed from the same high
	part as the first, load it into AT using ADDRESS_ADDI_INSN.
	Fix the handling of LD in cases where the first register is the
	same as the base.  Also handle the case where the offset is
	not 16 bits and the second register cannot be accessed from the
	same high part as the first.  For unaligned loads and stores,
	fuse the offbits == 12 and old "ab" handling.  Apply this handling
	whenever the second offset needs a different high part from the first.
	Construct the offset using ADDRESS_ADDI_INSN where possible,
	for offbits == 16 as well as offbits == 12.  Use offset_reloc
	when constructing the individual loads and stores.
	(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
	and offset_reloc before matching against a particular opcode.
	Handle elided 'A' constants.  Allow 'A' constants to use
	relocation operators.

gas/testsuite/
	* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
	truncated constants.
	* gas/mips/ldstla-32-shared.d: Likewise.
	* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
	16-bit constants to the base.
	* gas/mips/micromips@mcu.d: Likewise.
	* gas/mips/micromips@cache.d: Likewise.
	* gas/mips/micromips@pref.d: Likewise.
	* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
	gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
	Allow the full 16-bit offset range to be used for SB, LB and LBU in
	USH and ULH sequences.  Fix the expected output for LD and SD when
	the two LW and SW offsets need different high parts.
	* gas/mips/eva.s: Test PREFE with relocation operators.
	* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
	constants.  Update after eva.s change.
	* gas/mips/micromips@eva.d: Likewise.
	* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
	gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
	gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
	gas/mips/ulh-reloc.d: New tests.
	* gas/mips/mips.exp: Run them.
This commit is contained in:
Richard Sandiford 2013-07-07 11:32:32 +00:00
parent d070d2a253
commit f2ae14a1cc
31 changed files with 3520 additions and 3920 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
gas/ChangeLog
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@ -1,3 +1,32 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.

562
gas/config/tc-mips.c
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25
gas/testsuite/ChangeLog
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@ -1,3 +1,28 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/eva.d, gas/mips/micromips@eva.d: Remove hard-coded

1236
gas/testsuite/gas/mips/eva.d
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1
gas/testsuite/gas/mips/eva.s
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@ -610,3 +610,4 @@ test_eva:
prefe 10,2147483647
prefe 11,($12)
prefe 13,MYDATA
prefe 5,%lo(foo)($6)

86
gas/testsuite/gas/mips/l_d-reloc.d Normal file
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@ -0,0 +1,86 @@
#as: -32 -EB -mips1
#objdump: -dr --prefix-addresses -Mgpr-names=numeric
#name: LDC1 with relocation operators
.*file format.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$5\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$5\)
[0-9a-f]+ <[^>]*> lwc1 \$f5,32763\(\$5\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,32767\(\$5\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32764
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32767
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x1
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lwc1 \$f5,-32768\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,-32764\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lwc1 \$f5,32763\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,32767\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffc
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7fff
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x4
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lwc1 \$f5,-32768\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,-32764\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$0\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$0\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> li \$1,-30875
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,4661
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$5\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$5\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
[0-9a-f]+ <[^>]*> lwc1 \$f4,4\(\$1\)
#pass

26
gas/testsuite/gas/mips/l_d-reloc.s Normal file
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@ -0,0 +1,26 @@
.ent func
func:
l.d $f4,($5)
l.d $f4,0x7ffb($5)
l.d $f4,0x7ffc($5)
l.d $f4,0x7fff($5)
l.d $f4,0x8000($5)
l.d $f4,0x37ffb($5)
l.d $f4,0x37ffc($5)
l.d $f4,0x37fff($5)
l.d $f4,0x38000($5)
l.d $f4,%lo(foo)
l.d $f4,%hi(foo)
l.d $f4,%gp_rel(foo)
l.d $f4,%lo(0x12348765)
l.d $f4,%hi(0x12348765)
l.d $f4,%lo(foo)($5)
l.d $f4,%hi(foo)($5)
l.d $f4,%gp_rel(foo)($5)
l.d $f4,%lo(0x12348765)($5)
l.d $f4,%hi(0x12348765)($5)
l.d $f4,%lo(foo+0x12348765)($5)
l.d $f4,%hi(foo+0x12348765)($5)
.end func

114
gas/testsuite/gas/mips/ld-reloc.d Normal file
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@ -0,0 +1,114 @@
#as: -32
#objdump: -dr --prefix-addresses -Mgpr-names=numeric
#name: LD with relocation operators
.*file format.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> lw \$5,4\(\$4\)
[0-9a-f]+ <[^>]*> lw \$4,0\(\$4\)
[0-9a-f]+ <[^>]*> lw \$5,32767\(\$4\)
[0-9a-f]+ <[^>]*> lw \$4,32763\(\$4\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32764
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32767
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x1
[0-9a-f]+ <[^>]*> addu \$1,\$4,\$1
[0-9a-f]+ <[^>]*> lw \$4,-32768\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,-32764\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> lw \$4,0\(\$5\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$5\)
[0-9a-f]+ <[^>]*> lw \$4,32763\(\$5\)
[0-9a-f]+ <[^>]*> lw \$5,32767\(\$5\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32764
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32767
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x1
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lw \$4,-32768\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,-32764\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lw \$4,32763\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,32767\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffc
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7fff
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x4
[0-9a-f]+ <[^>]*> addu \$1,\$5,\$1
[0-9a-f]+ <[^>]*> lw \$4,-32768\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,-32764\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> lw \$4,0\(\$0\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lw \$5,4\(\$0\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> li \$1,-30875
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,4661
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$4\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$4\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> lw \$4,0\(\$5\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lw \$5,4\(\$5\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lw \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lw \$5,4\(\$1\)
#pass

36
gas/testsuite/gas/mips/ld-reloc.s Normal file
View File

@ -0,0 +1,36 @@
.ent func
func:
ld $4,($4)
ld $4,0x7ffb($4)
ld $4,0x7ffc($4)
ld $4,0x7fff($4)
ld $4,0x8000($4)
ld $4,($5)
ld $4,0x7ffb($5)
ld $4,0x7ffc($5)
ld $4,0x7fff($5)
ld $4,0x8000($5)
ld $4,0x37ffb($5)
ld $4,0x37ffc($5)
ld $4,0x37fff($5)
ld $4,0x38000($5)
ld $4,%lo(foo)
ld $4,%hi(foo)
ld $4,%gp_rel(foo)
ld $4,%lo(0x12348765)
ld $4,%hi(0x12348765)
ld $4,%lo(foo)($4)
ld $4,%hi(foo)($4)
ld $4,%gp_rel(foo)($4)
ld $4,%lo(foo)($5)
ld $4,%hi(foo)($5)
ld $4,%gp_rel(foo)($5)
ld $4,%lo(0x12348765)($5)
ld $4,%hi(0x12348765)($5)
ld $4,%lo(foo+0x12348765)($5)
ld $4,%hi(foo+0x12348765)($5)
.end func

44
gas/testsuite/gas/mips/ldstla-32-shared.d
View File

@ -26,14 +26,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c224567 lw v0,17767\(at\)
[ 0-9a-f]+: 8c23456b lw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c220000 lw v0,0\(at\)
[ 0-9a-f]+: 8c230004 lw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c22ffff lw v0,-1\(at\)
[ 0-9a-f]+: 8c230003 lw v1,3\(at\)
[ 0-9a-f]+: 8c820000 lw v0,0\(a0\)
[ 0-9a-f]+: 8c830004 lw v1,4\(a0\)
[ 0-9a-f]+: 8c82ffff lw v0,-1\(a0\)
[ 0-9a-f]+: 8c830003 lw v1,3\(a0\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c22ef01 lw v0,-4351\(at\)
@ -66,12 +62,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 3c010123 lui at,0x123
[ 0-9a-f]+: 8c224567 lw v0,17767\(at\)
[ 0-9a-f]+: 8c23456b lw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 8c220000 lw v0,0\(at\)
[ 0-9a-f]+: 8c230004 lw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 8c22ffff lw v0,-1\(at\)
[ 0-9a-f]+: 8c230003 lw v1,3\(at\)
[ 0-9a-f]+: 8c020000 lw v0,0\(zero\)
[ 0-9a-f]+: 8c030004 lw v1,4\(zero\)
[ 0-9a-f]+: 8c02ffff lw v0,-1\(zero\)
[ 0-9a-f]+: 8c030003 lw v1,3\(zero\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: 8c22ef01 lw v0,-4351\(at\)
[ 0-9a-f]+: 8c23ef05 lw v1,-4347\(at\)
@ -104,14 +98,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac224567 sw v0,17767\(at\)
[ 0-9a-f]+: ac23456b sw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac220000 sw v0,0\(at\)
[ 0-9a-f]+: ac230004 sw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac22ffff sw v0,-1\(at\)
[ 0-9a-f]+: ac230003 sw v1,3\(at\)
[ 0-9a-f]+: ac820000 sw v0,0\(a0\)
[ 0-9a-f]+: ac830004 sw v1,4\(a0\)
[ 0-9a-f]+: ac82ffff sw v0,-1\(a0\)
[ 0-9a-f]+: ac830003 sw v1,3\(a0\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac22ef01 sw v0,-4351\(at\)
@ -144,12 +134,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 3c010123 lui at,0x123
[ 0-9a-f]+: ac224567 sw v0,17767\(at\)
[ 0-9a-f]+: ac23456b sw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: ac220000 sw v0,0\(at\)
[ 0-9a-f]+: ac230004 sw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: ac22ffff sw v0,-1\(at\)
[ 0-9a-f]+: ac230003 sw v1,3\(at\)
[ 0-9a-f]+: ac020000 sw v0,0\(zero\)
[ 0-9a-f]+: ac030004 sw v1,4\(zero\)
[ 0-9a-f]+: ac02ffff sw v0,-1\(zero\)
[ 0-9a-f]+: ac030003 sw v1,3\(zero\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: ac22ef01 sw v0,-4351\(at\)
[ 0-9a-f]+: ac23ef05 sw v1,-4347\(at\)

44
gas/testsuite/gas/mips/ldstla-32.d
View File

@ -26,14 +26,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c224567 lw v0,17767\(at\)
[ 0-9a-f]+: 8c23456b lw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c220000 lw v0,0\(at\)
[ 0-9a-f]+: 8c230004 lw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c22ffff lw v0,-1\(at\)
[ 0-9a-f]+: 8c230003 lw v1,3\(at\)
[ 0-9a-f]+: 8c820000 lw v0,0\(a0\)
[ 0-9a-f]+: 8c830004 lw v1,4\(a0\)
[ 0-9a-f]+: 8c82ffff lw v0,-1\(a0\)
[ 0-9a-f]+: 8c830003 lw v1,3\(a0\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: 8c22ef01 lw v0,-4351\(at\)
@ -66,12 +62,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 3c010123 lui at,0x123
[ 0-9a-f]+: 8c224567 lw v0,17767\(at\)
[ 0-9a-f]+: 8c23456b lw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 8c220000 lw v0,0\(at\)
[ 0-9a-f]+: 8c230004 lw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 8c22ffff lw v0,-1\(at\)
[ 0-9a-f]+: 8c230003 lw v1,3\(at\)
[ 0-9a-f]+: 8c020000 lw v0,0\(zero\)
[ 0-9a-f]+: 8c030004 lw v1,4\(zero\)
[ 0-9a-f]+: 8c02ffff lw v0,-1\(zero\)
[ 0-9a-f]+: 8c030003 lw v1,3\(zero\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: 8c22ef01 lw v0,-4351\(at\)
[ 0-9a-f]+: 8c23ef05 lw v1,-4347\(at\)
@ -104,14 +98,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac224567 sw v0,17767\(at\)
[ 0-9a-f]+: ac23456b sw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac220000 sw v0,0\(at\)
[ 0-9a-f]+: ac230004 sw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac22ffff sw v0,-1\(at\)
[ 0-9a-f]+: ac230003 sw v1,3\(at\)
[ 0-9a-f]+: ac820000 sw v0,0\(a0\)
[ 0-9a-f]+: ac830004 sw v1,4\(a0\)
[ 0-9a-f]+: ac82ffff sw v0,-1\(a0\)
[ 0-9a-f]+: ac830003 sw v1,3\(a0\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: 00810821 addu at,a0,at
[ 0-9a-f]+: ac22ef01 sw v0,-4351\(at\)
@ -144,12 +134,10 @@ Disassembly of section \.text:
[ 0-9a-f]+: 3c010123 lui at,0x123
[ 0-9a-f]+: ac224567 sw v0,17767\(at\)
[ 0-9a-f]+: ac23456b sw v1,17771\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: ac220000 sw v0,0\(at\)
[ 0-9a-f]+: ac230004 sw v1,4\(at\)
[ 0-9a-f]+: 3c010000 lui at,0x0
[ 0-9a-f]+: ac22ffff sw v0,-1\(at\)
[ 0-9a-f]+: ac230003 sw v1,3\(at\)
[ 0-9a-f]+: ac020000 sw v0,0\(zero\)
[ 0-9a-f]+: ac030004 sw v1,4\(zero\)
[ 0-9a-f]+: ac02ffff sw v0,-1\(zero\)
[ 0-9a-f]+: ac030003 sw v1,3\(zero\)
[ 0-9a-f]+: 3c01abce lui at,0xabce
[ 0-9a-f]+: ac22ef01 sw v0,-4351\(at\)
[ 0-9a-f]+: ac23ef05 sw v1,-4347\(at\)

52
gas/testsuite/gas/mips/mcu.d
View File

@ -23,17 +23,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 07e77000 aclr 0x7,0\(ra\)
[ 0-9a-f]+: 07e777ff aclr 0x7,2047\(ra\)
[ 0-9a-f]+: 07e77800 aclr 0x7,-2048\(ra\)
[ 0-9a-f]+: 24011000 li at,4096
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 04277800 aclr 0x7,-2048\(at\)
[ 0-9a-f]+: 2401f000 li at,-4096
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 042777ff aclr 0x7,2047\(at\)
[ 0-9a-f]+: 34018000 li at,0x8000
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 04277fff aclr 0x7,-1\(at\)
[ 0-9a-f]+: 24018000 li at,-32768
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 27e10800 addiu at,ra,2048
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 27e1f7ff addiu at,ra,-2049
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 27e17fff addiu at,ra,32767
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 27e18000 addiu at,ra,-32768
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 3c010001 lui at,0x1
[ 0-9a-f]+: 00240821 addu at,at,a0
@ -44,15 +40,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 3c01ffff lui at,0xffff
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 24018000 li at,-32768
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 24818000 addiu at,a0,-32768
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 3c01ffff lui at,0xffff
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 04277001 aclr 0x7,1\(at\)
[ 0-9a-f]+: 24018000 li at,-32768
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 04277001 aclr 0x7,1\(at\)
[ 0-9a-f]+: 24818001 addiu at,a0,-32767
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 3c01f000 lui at,0xf000
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 04277000 aclr 0x7,0\(at\)
@ -81,17 +75,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 07e7f000 aset 0x7,0\(ra\)
[ 0-9a-f]+: 07e7f7ff aset 0x7,2047\(ra\)
[ 0-9a-f]+: 07e7f800 aset 0x7,-2048\(ra\)
[ 0-9a-f]+: 24011000 li at,4096
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 0427f800 aset 0x7,-2048\(at\)
[ 0-9a-f]+: 2401f000 li at,-4096
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 0427f7ff aset 0x7,2047\(at\)
[ 0-9a-f]+: 34018000 li at,0x8000
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 0427ffff aset 0x7,-1\(at\)
[ 0-9a-f]+: 24018000 li at,-32768
[ 0-9a-f]+: 003f0821 addu at,at,ra
[ 0-9a-f]+: 27e10800 addiu at,ra,2048
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)
[ 0-9a-f]+: 27e1f7ff addiu at,ra,-2049
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)
[ 0-9a-f]+: 27e17fff addiu at,ra,32767
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)
[ 0-9a-f]+: 27e18000 addiu at,ra,-32768
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)
[ 0-9a-f]+: 3c010001 lui at,0x1
[ 0-9a-f]+: 00240821 addu at,at,a0
@ -102,15 +92,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 3c01ffff lui at,0xffff
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)
[ 0-9a-f]+: 24018000 li at,-32768
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 24818000 addiu at,a0,-32768
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)
[ 0-9a-f]+: 3c01ffff lui at,0xffff
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 0427f001 aset 0x7,1\(at\)
[ 0-9a-f]+: 24018000 li at,-32768
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 0427f001 aset 0x7,1\(at\)
[ 0-9a-f]+: 24818001 addiu at,a0,-32767
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)
[ 0-9a-f]+: 3c01f000 lui at,0xf000
[ 0-9a-f]+: 00240821 addu at,at,a0
[ 0-9a-f]+: 0427f000 aset 0x7,0\(at\)

769
gas/testsuite/gas/mips/micromips-insn32.d
View File

File diff suppressed because it is too large Load Diff

769
gas/testsuite/gas/mips/micromips-noinsn32.d
View File

File diff suppressed because it is too large Load Diff

769
gas/testsuite/gas/mips/micromips-trap.d
View File

File diff suppressed because it is too large Load Diff

769
gas/testsuite/gas/mips/micromips.d
View File

File diff suppressed because it is too large Load Diff

18
gas/testsuite/gas/mips/micromips@cache.d
View File

@ -10,17 +10,13 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 20a2 67ff cache 0x5,2047\(v0\)
[0-9a-f]+ <[^>]*> 20a3 6800 cache 0x5,-2048\(v1\)
[0-9a-f]+ <[^>]*> 3020 1000 li at,4096
[0-9a-f]+ <[^>]*> 0081 0950 addu at,at,a0
[0-9a-f]+ <[^>]*> 20a1 6800 cache 0x5,-2048\(at\)
[0-9a-f]+ <[^>]*> 3020 f000 li at,-4096
[0-9a-f]+ <[^>]*> 00a1 0950 addu at,at,a1
[0-9a-f]+ <[^>]*> 20a1 67ff cache 0x5,2047\(at\)
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 00c1 0950 addu at,at,a2
[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\)
[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
[0-9a-f]+ <[^>]*> 00e1 0950 addu at,at,a3
[0-9a-f]+ <[^>]*> 3024 0800 addiu at,a0,2048
[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 3025 f7ff addiu at,a1,-2049
[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 3026 7fff addiu at,a2,32767
[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 3027 8000 addiu at,a3,-32768
[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 0101 0950 addu at,at,t0

1236
gas/testsuite/gas/mips/micromips@eva.d
View File

File diff suppressed because it is too large Load Diff

52
gas/testsuite/gas/mips/micromips@mcu.d
View File

@ -23,17 +23,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 20ff b000 aclr 0x7,0\(ra\)
[ 0-9a-f]+: 20ff b7ff aclr 0x7,2047\(ra\)
[ 0-9a-f]+: 20ff b800 aclr 0x7,-2048\(ra\)
[ 0-9a-f]+: 3020 1000 li at,4096
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 20e1 b800 aclr 0x7,-2048\(at\)
[ 0-9a-f]+: 3020 f000 li at,-4096
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 20e1 b7ff aclr 0x7,2047\(at\)
[ 0-9a-f]+: 5020 8000 li at,0x8000
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 20e1 bfff aclr 0x7,-1\(at\)
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 303f 0800 addiu at,ra,2048
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 303f f7ff addiu at,ra,-2049
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 303f 7fff addiu at,ra,32767
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 303f 8000 addiu at,ra,-32768
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 41a1 0001 lui at,0x1
[ 0-9a-f]+: 0081 0950 addu at,at,a0
@ -44,15 +40,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 41a1 ffff lui at,0xffff
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 41a1 ffff lui at,0xffff
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 b001 aclr 0x7,1\(at\)
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 b001 aclr 0x7,1\(at\)
[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
[ 0-9a-f]+: 41a1 f000 lui at,0xf000
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
@ -81,17 +75,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 20ff 3000 aset 0x7,0\(ra\)
[ 0-9a-f]+: 20ff 37ff aset 0x7,2047\(ra\)
[ 0-9a-f]+: 20ff 3800 aset 0x7,-2048\(ra\)
[ 0-9a-f]+: 3020 1000 li at,4096
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 20e1 3800 aset 0x7,-2048\(at\)
[ 0-9a-f]+: 3020 f000 li at,-4096
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 20e1 37ff aset 0x7,2047\(at\)
[ 0-9a-f]+: 5020 8000 li at,0x8000
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 20e1 3fff aset 0x7,-1\(at\)
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 03e1 0950 addu at,at,ra
[ 0-9a-f]+: 303f 0800 addiu at,ra,2048
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
[ 0-9a-f]+: 303f f7ff addiu at,ra,-2049
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
[ 0-9a-f]+: 303f 7fff addiu at,ra,32767
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
[ 0-9a-f]+: 303f 8000 addiu at,ra,-32768
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
[ 0-9a-f]+: 41a1 0001 lui at,0x1
[ 0-9a-f]+: 0081 0950 addu at,at,a0
@ -102,15 +92,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 41a1 ffff lui at,0xffff
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
[ 0-9a-f]+: 41a1 ffff lui at,0xffff
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 3001 aset 0x7,1\(at\)
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 3001 aset 0x7,1\(at\)
[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
[ 0-9a-f]+: 41a1 f000 lui at,0xf000
[ 0-9a-f]+: 0081 0950 addu at,at,a0
[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)

18
gas/testsuite/gas/mips/micromips@pref.d
View File

@ -10,17 +10,13 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 60a2 27ff pref 0x5,2047\(v0\)
[0-9a-f]+ <[^>]*> 60a3 2800 pref 0x5,-2048\(v1\)
[0-9a-f]+ <[^>]*> 3020 1000 li at,4096
[0-9a-f]+ <[^>]*> 0081 0950 addu at,at,a0
[0-9a-f]+ <[^>]*> 60a1 2800 pref 0x5,-2048\(at\)
[0-9a-f]+ <[^>]*> 3020 f000 li at,-4096
[0-9a-f]+ <[^>]*> 00a1 0950 addu at,at,a1
[0-9a-f]+ <[^>]*> 60a1 27ff pref 0x5,2047\(at\)
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 00c1 0950 addu at,at,a2
[0-9a-f]+ <[^>]*> 60a1 2fff pref 0x5,-1\(at\)
[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
[0-9a-f]+ <[^>]*> 00e1 0950 addu at,at,a3
[0-9a-f]+ <[^>]*> 3024 0800 addiu at,a0,2048
[0-9a-f]+ <[^>]*> 60a1 2000 pref 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 3025 f7ff addiu at,a1,-2049
[0-9a-f]+ <[^>]*> 60a1 2000 pref 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 3026 7fff addiu at,a2,32767
[0-9a-f]+ <[^>]*> 60a1 2000 pref 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 3027 8000 addiu at,a3,-32768
[0-9a-f]+ <[^>]*> 60a1 2000 pref 0x5,0\(at\)
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 0101 0950 addu at,at,t0

144
gas/testsuite/gas/mips/micromips@ulw-reloc.d Normal file
View File

@ -0,0 +1,144 @@
#as: -32 -EB
#objdump: -dr --prefix-addresses -Mgpr-names=numeric
#name: ULW with relocation operators
#source: ulw-reloc.s
.*file format.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> lwl \$1,0\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,3\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> lwl \$1,2044\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,2047\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$4,2045
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,2047
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,2048
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32764
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32765
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32767
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$4
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$5\)
[0-9a-f]+ <[^>]*> lwl \$4,2044\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,2047\(\$5\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,2045
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,2047
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,2048
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32764
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32765
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32767
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffc
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffd
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7fff
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
# Would be more efficient to apply the offset to the base register.
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_MICROMIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,-30875
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,4661
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_MICROMIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_MICROMIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[ ]*[0-9a-f]+: R_MICROMIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#pass

12
gas/testsuite/gas/mips/mips.exp
View File

@ -1114,4 +1114,16 @@ if { [istarget mips*-*-vxworks*] } {
run_list_test "ase-errors-2" "-mabi=o64 -march=mips3" "ASE errors (2)"
run_list_test "ase-errors-3" "-mabi=32 -march=mips1" "ASE errors (3)"
run_list_test "ase-errors-4" "-mabi=o64 -march=mips3" "ASE errors (4)"
run_dump_test_arches "la-reloc" [mips_arch_list_matching mips1]
if { $has_newabi } {
run_dump_test_arches "dla-reloc" [mips_arch_list_matching mips3]
}
# Start with MIPS II to avoid load delay nops.
run_dump_test_arches "ld-reloc" [mips_arch_list_matching mips2]
run_dump_test_arches "ulw-reloc" [mips_arch_list_matching mips2]
run_dump_test_arches "ulh-reloc" [mips_arch_list_matching mips2]
run_dump_test "l_d-reloc"
}

160
gas/testsuite/gas/mips/ulh-reloc.d Normal file
View File

@ -0,0 +1,160 @@
#as: -32 -EB
#objdump: -dr --prefix-addresses -Mgpr-names=numeric
#name: ULH with relocation operators
.*file format.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> lb \$1,0\(\$4\)
[0-9a-f]+ <[^>]*> lbu \$4,1\(\$4\)
[0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> lb \$1,32766\(\$4\)
[0-9a-f]+ <[^>]*> lbu \$4,32767\(\$4\)
[0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32767
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> li \$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$4
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> lb \$1,0\(\$5\)
[0-9a-f]+ <[^>]*> lbu \$4,1\(\$5\)
[0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> lb \$1,32766\(\$5\)
[0-9a-f]+ <[^>]*> lbu \$4,32767\(\$5\)
[0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32767
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> li \$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
# Would be more efficient to apply the offset to the base register.
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffe
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
# This one must use LUI/ORI
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7fff
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
# Would be more efficient to apply the offset to the base register.
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> lb \$1,0\(\$0\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lbu \$4,1\(\$0\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> li \$1,-30875
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> li \$1,4661
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> lb \$1,0\(\$4\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lbu \$4,1\(\$4\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> lb \$1,0\(\$5\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lbu \$4,1\(\$5\)
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[ ]*[0-9a-f]+: R_(MICRO|)MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lb \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lbu \$1,1\(\$1\)
[0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[0-9a-f]+ <[^>]*> or \$4,\$4,\$1
#pass

33
gas/testsuite/gas/mips/ulh-reloc.s Normal file
View File

@ -0,0 +1,33 @@
.ent func
func:
ulh $4,($4)
ulh $4,0x7ffe($4)
ulh $4,0x7fff($4)
ulh $4,0x8000($4)
ulh $4,($5)
ulh $4,0x7ffe($5)
ulh $4,0x7fff($5)
ulh $4,0x8000($5)
ulh $4,0x37ffe($5)
ulh $4,0x37fff($5)
ulh $4,0x38000($5)
ulh $4,%lo(foo)
ulh $4,%hi(foo)
ulh $4,%gp_rel(foo)
ulh $4,%lo(0x12348765)
ulh $4,%hi(0x12348765)
ulh $4,%lo(foo)($4)
ulh $4,%hi(foo)($4)
ulh $4,%gp_rel(foo)($4)
ulh $4,%lo(foo)($5)
ulh $4,%hi(foo)($5)
ulh $4,%gp_rel(foo)($5)
ulh $4,%lo(0x12348765)($5)
ulh $4,%hi(0x12348765)($5)
ulh $4,%lo(foo+0x12348765)($5)
ulh $4,%hi(foo+0x12348765)($5)
.end func

143
gas/testsuite/gas/mips/ulw-reloc.d Normal file
View File

@ -0,0 +1,143 @@
#as: -32 -EB
#objdump: -dr --prefix-addresses -Mgpr-names=numeric
#name: ULW with relocation operators
.*file format.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> lwl \$1,0\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,3\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> lwl \$1,2044\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,2047\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> lwl \$1,2045\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,2048\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> lwl \$1,2047\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,2050\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> lwl \$1,2048\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,2051\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> lwl \$1,32764\(\$4\)
[0-9a-f]+ <[^>]*> lwr \$1,32767\(\$4\)
[0-9a-f]+ <[^>]*> move \$4,\$1
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32765
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,32767
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$4
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$5\)
[0-9a-f]+ <[^>]*> lwl \$4,2044\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,2047\(\$5\)
[0-9a-f]+ <[^>]*> lwl \$4,2045\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,2048\(\$5\)
[0-9a-f]+ <[^>]*> lwl \$4,2047\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,2050\(\$5\)
[0-9a-f]+ <[^>]*> lwl \$4,2048\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,2051\(\$5\)
[0-9a-f]+ <[^>]*> lwl \$4,32764\(\$5\)
[0-9a-f]+ <[^>]*> lwr \$4,32767\(\$5\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32765
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,32767
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
# Would be more efficient to apply the offset to the base register.
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffc
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
# This one must use LUI/ORI
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffd
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
# This one must use LUI/ORI
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x7fff
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
# Would be more efficient to apply the offset to the base register.
[0-9a-f]+ <[^>]*> lui \$1,0x3
[0-9a-f]+ <[^>]*> ori \$1,\$1,0x8000
[0-9a-f]+ <[^>]*> addu \$1,\$1,\$5
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,0
[ ]*[0-9a-f]+: R_MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$0\)
[ ]*[0-9a-f]+: R_MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$0\)
[ ]*[0-9a-f]+: R_MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> li \$1,-30875
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> li \$1,4661
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$4,0
[ ]*[0-9a-f]+: R_MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> lwl \$1,0\(\$4\)
[ ]*[0-9a-f]+: R_MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwr \$1,3\(\$4\)
[ ]*[0-9a-f]+: R_MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> move \$4,\$1
#--------------------------------------------------------------------
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,0
[ ]*[0-9a-f]+: R_MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$5\)
[ ]*[0-9a-f]+: R_MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$5\)
[ ]*[0-9a-f]+: R_MIPS_GPREL16 foo
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,-30875
[ ]*[0-9a-f]+: R_MIPS_LO16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
[0-9a-f]+ <[^>]*> addiu \$1,\$5,4661
[ ]*[0-9a-f]+: R_MIPS_HI16 foo
[0-9a-f]+ <[^>]*> lwl \$4,0\(\$1\)
[0-9a-f]+ <[^>]*> lwr \$4,3\(\$1\)
#pass

44
gas/testsuite/gas/mips/ulw-reloc.s Normal file
View File

@ -0,0 +1,44 @@
.ent func
func:
ulw $4,($4)
ulw $4,0x7fc($4)
ulw $4,0x7fd($4)
ulw $4,0x7ff($4)
ulw $4,0x800($4)
ulw $4,0x7ffc($4)
ulw $4,0x7ffd($4)
ulw $4,0x7fff($4)
ulw $4,0x8000($4)
ulw $4,($5)
ulw $4,0x7fc($5)
ulw $4,0x7fd($5)
ulw $4,0x7ff($5)
ulw $4,0x800($5)
ulw $4,0x7ffc($5)
ulw $4,0x7ffd($5)
ulw $4,0x7fff($5)
ulw $4,0x8000($5)
ulw $4,0x37ffc($5)
ulw $4,0x37ffd($5)
ulw $4,0x37fff($5)
ulw $4,0x38000($5)
ulw $4,%lo(foo)
ulw $4,%hi(foo)
ulw $4,%gp_rel(foo)
ulw $4,%lo(0x12348765)
ulw $4,%hi(0x12348765)
ulw $4,%lo(foo)($4)
ulw $4,%hi(foo)($4)
ulw $4,%gp_rel(foo)($4)
ulw $4,%lo(foo)($5)
ulw $4,%hi(foo)($5)
ulw $4,%gp_rel(foo)($5)
ulw $4,%lo(0x12348765)($5)
ulw $4,%hi(0x12348765)($5)
ulw $4,%lo(foo+0x12348765)($5)
ulw $4,%hi(foo+0x12348765)($5)
.end func

19
include/opcode/ChangeLog
View File

@ -1,3 +1,22 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Remove documentation of "[" and "]". Update documentation

99
include/opcode/mips.h
View File

@ -947,8 +947,8 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
/* This is a list of macro expanded instructions.
_I appended means immediate
_A appended means address
_AB appended means address with base register
_A appended means target address of a jump
_AB appended means address with (possibly zero) base register
_D appended means 64 bit floating point constant
_S appended means 32 bit floating point constant. */
@ -956,12 +956,10 @@ enum
{
M_ABS,
M_ACLR_AB,
M_ACLR_OB,
M_ADD_I,
M_ADDU_I,
M_AND_I,
M_ASET_AB,
M_ASET_OB,
M_BALIGN,
M_BC1FL,
M_BC1TL,
@ -1018,9 +1016,7 @@ enum
M_BNE_I,
M_BNEL_I,
M_CACHE_AB,
M_CACHE_OB,
M_CACHEE_AB,
M_CACHEE_OB,
M_DABS,
M_DADD_I,
M_DADDU_I,
@ -1059,41 +1055,25 @@ enum
M_JALS_A,
M_JRADDIUSP,
M_JRC,
M_L_DOB,
M_L_DAB,
M_LA_AB,
M_LB_A,
M_LB_AB,
M_LBE_OB,
M_LBE_AB,
M_LBU_A,
M_LBU_AB,
M_LBUE_OB,
M_LBUE_AB,
M_LCA_AB,
M_LD_A,
M_LD_OB,
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
M_LDC2_OB,
M_LQC2_AB,
M_LDC3_AB,
M_LDL_AB,
M_LDL_OB,
M_LDM_AB,
M_LDM_OB,
M_LDP_AB,
M_LDP_OB,
M_LDR_AB,
M_LDR_OB,
M_LH_A,
M_LH_AB,
M_LHE_OB,
M_LHE_AB,
M_LHU_A,
M_LHU_AB,
M_LHUE_OB,
M_LHUE_AB,
M_LI,
M_LI_D,
@ -1101,42 +1081,22 @@ enum
M_LI_S,
M_LI_SS,
M_LL_AB,
M_LL_OB,
M_LLD_AB,
M_LLD_OB,
M_LLE_AB,
M_LLE_OB,
M_LQ_AB,
M_LS_A,
M_LW_A,
M_LW_AB,
M_LWE_OB,
M_LWE_AB,
M_LWC0_A,
M_LWC0_AB,
M_LWC1_A,
M_LWC1_AB,
M_LWC2_A,
M_LWC2_AB,
M_LWC2_OB,
M_LWC3_A,
M_LWC3_AB,
M_LWL_A,
M_LWL_AB,
M_LWL_OB,
M_LWLE_AB,
M_LWLE_OB,
M_LWM_AB,
M_LWM_OB,
M_LWP_AB,
M_LWP_OB,
M_LWR_A,
M_LWR_AB,
M_LWR_OB,
M_LWRE_AB,
M_LWRE_OB,
M_LWU_AB,
M_LWU_OB,
M_MSGSND,
M_MSGLD,
M_MSGLD_T,
@ -1153,9 +1113,7 @@ enum
M_NOR_I,
M_OR_I,
M_PREF_AB,
M_PREF_OB,
M_PREFE_AB,
M_PREFE_OB,
M_REM_3,
M_REM_3I,
M_REMU_3,
@ -1169,35 +1127,22 @@ enum
M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
M_S_DAB,
M_S_S,
M_SAA_AB,
M_SAA_OB,
M_SAAD_AB,
M_SAAD_OB,
M_SC_AB,
M_SC_OB,
M_SCD_AB,
M_SCD_OB,
M_SCE_AB,
M_SCE_OB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
M_SDC2_OB,
M_SQC2_AB,
M_SDC3_AB,
M_SDL_AB,
M_SDL_OB,
M_SDM_AB,
M_SDM_OB,
M_SDP_AB,
M_SDP_OB,
M_SDR_AB,
M_SDR_OB,
M_SEQ,
M_SEQ_I,
M_SGE,
@ -1216,42 +1161,23 @@ enum
M_SLTU_I,
M_SNE,
M_SNE_I,
M_SB_A,
M_SB_AB,
M_SBE_OB,
M_SBE_AB,
M_SH_A,
M_SH_AB,
M_SHE_OB,
M_SHE_AB,
M_SQ_AB,
M_SW_A,
M_SW_AB,
M_SWE_OB,
M_SWE_AB,
M_SWC0_A,
M_SWC0_AB,
M_SWC1_A,
M_SWC1_AB,
M_SWC2_A,
M_SWC2_AB,
M_SWC2_OB,
M_SWC3_A,
M_SWC3_AB,
M_SWL_A,
M_SWL_AB,
M_SWL_OB,
M_SWLE_AB,
M_SWLE_OB,
M_SWM_AB,
M_SWM_OB,
M_SWP_AB,
M_SWP_OB,
M_SWR_A,
M_SWR_AB,
M_SWR_OB,
M_SWRE_AB,
M_SWRE_OB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
@ -1263,20 +1189,13 @@ enum
M_TNE_I,
M_TRUNCWD,
M_TRUNCWS,
M_ULD,
M_ULD_A,
M_ULH,
M_ULH_A,
M_ULHU,
M_ULHU_A,
M_ULW,
M_ULW_A,
M_USH,
M_USH_A,
M_USW,
M_USW_A,
M_USD,
M_USD_A,
M_ULD_AB,
M_ULH_AB,
M_ULHU_AB,
M_ULW_AB,
M_USH_AB,
M_USW_AB,
M_USD_AB,
M_XOR_I,
M_COP0,
M_COP1,

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips16-opc.c: Add entries for argumentless "entry" and "exit"

76
opcodes/micromips-opc.c
View File

@ -127,7 +127,6 @@ const struct mips_opcode micromips_opcodes[] =
instruction name anyhow. */
/* name, args, match, mask, pinfo, pinfo2, membership, [ase], [exclusions] */
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I1 },
{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1 },
@ -160,7 +159,6 @@ const struct mips_opcode micromips_opcodes[] =
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, 0, MC },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC },
{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
@ -195,7 +193,6 @@ const struct mips_opcode micromips_opcodes[] =
{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, WR_md|RD_mc, I1 },
{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, 0, MC },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC },
/* b is at the top of the table. */
/* bal is at the top of the table. */
@ -383,7 +380,6 @@ const struct mips_opcode micromips_opcodes[] =
{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_b, 0, I1 },
{"cache", "k,o(b)", 0, (int) M_CACHE_OB, INSN_MACRO, 0, I1 },
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1 },
{"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
@ -596,29 +592,23 @@ const struct mips_opcode micromips_opcodes[] =
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
/* The macro has to be first to handle o32 correctly. */
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b|WR_t, 0, I3 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b|WR_t, 0, I3 },
{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
{"ldc2", "E,o(b)", 0, (int) M_LDC2_OB, INSN_MACRO, 0, I1 },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1 },
{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 }, /* ldc1 */
{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_t|RD_b, 0, I3 },
{"ldl", "t,o(b)", 0, (int) M_LDL_OB, INSN_MACRO, 0, I3 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_b, 0, I3 },
{"ldm", "n,o(b)", 0, (int) M_LDM_OB, INSN_MACRO, 0, I3 },
{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3 },
{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, RD_b|WR_t, 0, I3 },
{"ldp", "t,o(b)", 0, (int) M_LDP_OB, INSN_MACRO, 0, I3 },
{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3 },
{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_t|RD_b, 0, I3 },
{"ldr", "t,o(b)", 0, (int) M_LDR_OB, INSN_MACRO, 0, I3 },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
{"lh", "t,o(b)", 0x3c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
@ -632,10 +622,8 @@ const struct mips_opcode micromips_opcodes[] =
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 },
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 },
{"ll", "t,~(b)", 0x60003000, 0xfc00f000, RD_b|WR_t, 0, I1 },
{"ll", "t,o(b)", 0, (int) M_LL_OB, INSN_MACRO, 0, I1 },
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1 },
{"lld", "t,~(b)", 0x60007000, 0xfc00f000, RD_b|WR_t, 0, I3 },
{"lld", "t,o(b)", 0, (int) M_LLD_OB, INSN_MACRO, 0, I3 },
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
{"lui", "s,u", 0x41a00000, 0xffe00000, WR_s, 0, I1 },
{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
@ -649,32 +637,24 @@ const struct mips_opcode micromips_opcodes[] =
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
{"lwc2", "E,o(b)", 0, (int) M_LWC2_OB, INSN_MACRO, 0, I1 },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 },
{"lwl", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
{"lcache", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, NODS, RD_sp, I1 },
{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_b|NODS, 0, I1 },
{"lwm", "n,o(b)", 0, (int) M_LWM_OB, INSN_MACRO, 0, I1 },
{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1 },
{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, RD_b|WR_t|NODS, 0, I1 },
{"lwp", "t,o(b)", 0, (int) M_LWP_OB, INSN_MACRO, 0, I1 },
{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1 },
{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 },
{"lwr", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, RD_b|WR_t, 0, I3 },
{"lwu", "t,o(b)", 0, (int) M_LWU_OB, INSN_MACRO, 0, I3 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_D|RD_t|RD_b|FP_S, 0, I1 },
{"flush", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
{"flush", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 },
{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
@ -819,15 +799,12 @@ const struct mips_opcode micromips_opcodes[] =
{"sb", "t,o(b)", 0x18000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I1 },
{"sc", "t,o(b)", 0, (int) M_SC_OB, INSN_MACRO, 0, I1 },
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1 },
{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I3 },
{"scd", "t,o(b)", 0, (int) M_SCD_OB, INSN_MACRO, 0, I3 },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
/* The macro has to be first to handle o32 correctly. */
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
{"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
{"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1 },
{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1 },
{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1 },
@ -837,21 +814,16 @@ const struct mips_opcode micromips_opcodes[] =
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
{"sdc2", "E,o(b)", 0, (int) M_SDC2_OB, INSN_MACRO, 0, I1 },
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1 },
{"s.d", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 }, /* sdc1 */
{"s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
{"sdl", "t,o(b)", 0, (int) M_SDL_OB, INSN_MACRO, 0, I3 },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
{"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, SM|RD_b, 0, I3 },
{"sdm", "n,o(b)", 0, (int) M_SDM_OB, INSN_MACRO, 0, I3 },
{"sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3 },
{"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
{"sdp", "t,o(b)", 0, (int) M_SDP_OB, INSN_MACRO, 0, I3 },
{"sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3 },
{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
{"sdr", "t,o(b)", 0, (int) M_SDR_OB, INSN_MACRO, 0, I3 },
{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
{"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
@ -913,28 +885,21 @@ const struct mips_opcode micromips_opcodes[] =
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
{"swc2", "E,o(b)", 0, (int) M_SWC2_OB, INSN_MACRO, 0, I1 },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
{"s.s", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swl", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 },
{"swl", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"scache", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 }, /* same */
{"scache", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, NODS, RD_sp, I1 },
{"swm", "n,~(b)", 0x2000d000, 0xfc00f000, SM|RD_b|NODS, 0, I1 },
{"swm", "n,o(b)", 0, (int) M_SWM_OB, INSN_MACRO, 0, I1 },
{"swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1 },
{"swp", "t,~(b)", 0x20009000, 0xfc00f000, SM|RD_t|RD_b|NODS, 0, I1 },
{"swp", "t,o(b)", 0, (int) M_SWP_OB, INSN_MACRO, 0, I1 },
{"swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1 },
{"swr", "t,~(b)", 0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 },
{"swr", "t,o(b)", 0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
{"invalidate", "t,~(b)",0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 }, /* same */
{"invalidate", "t,o(b)",0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, SM|RD_t|RD_b|FP_S, RD_D, I1 },
{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1 },
@ -993,20 +958,13 @@ const struct mips_opcode micromips_opcodes[] =
{"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
{"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
{"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I1 },
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I1 },
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3 },
{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1 },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1 },
{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1 },
{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I1 },
{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1 },
{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1 },
{"wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1 },
{"wait", "B", 0x0000937c, 0xfc00ffff, NODS, 0, I1 },
{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_s, 0, I1 },
@ -1018,52 +976,36 @@ const struct mips_opcode micromips_opcodes[] =
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* microMIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, SM|RD_t|WR_t|RD_b, 0, 0, EVA },
{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA },
{"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA },
{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_b, 0, 0, EVA },
{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA },
{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_b, 0, 0, EVA },
{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA },
/* MIPS DSP ASE. */
{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },

49
opcodes/mips-opc.c
View File

@ -300,7 +300,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F },
{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E },
{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC },
{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, 0, MC },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC },
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
@ -340,7 +339,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC },
{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, 0, MC },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC },
{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
/* b is at the top of the table. */
@ -869,9 +867,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
/* The macro has to be first to handle o32 correctly. */
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
@ -880,7 +877,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, 0, SF }, /* ldc1 */
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
@ -1397,10 +1393,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, SB1, MX },
{"rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_D|RD_S|RD_T, 0, N54 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX },
{"saa", "t,o(b)", 0, (int) M_SAA_OB, INSN_MACRO, 0, IOCTP },
{"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP },
{"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
{"saad", "t,o(b)", 0, (int) M_SAAD_OB, INSN_MACRO, 0, IOCTP },
{"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP },
{"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
@ -1410,9 +1404,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3, 0, EE },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE },
/* The macro has to be first to handle o32 correctly. */
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
@ -1427,7 +1420,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, 0, SF },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
@ -1636,20 +1628,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE },
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE },
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE },
{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3 },
{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1 },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1 },
{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1 },
{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3 },
{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1 },
{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1 },
{"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
@ -2258,52 +2243,36 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
/* MIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, SM|RD_t|WR_t|RD_b, 0, 0, EVA },
{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA },
{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA },
{"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_b, 0, 0, EVA },
{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA },
{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_b, 0, 0, EVA },
{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the