Debug tx19 built from igen sources.
Rework ifetch{16,32} to match the more recent do_load function.
This commit is contained in:
Andrew Cagney
parent
7acc4e98d2
commit
f3bdd368ea
@ -1,3 +1,29 @@
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Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* m16run.c (sim_engine_run): Restore CIA after handling an event.
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start-sanitize-tx19
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* mips.igen (mtc0): Valid tx19 instruction.
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end-sanitize-tx19
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* sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
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functions.
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* mips.igen (delayslot32, nullify_next_insn): New functions.
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(m16.igen): Always include.
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(do_*): Add more tracing.
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* m16.igen (delayslot16): Add NIA argument, could be called by a
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32 bit MIPS16 instruction.
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* interp.c (ifetch16): Move function from here.
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* sim-main.c (ifetch16): To here.
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* sim-main.c (ifetch16, ifetch32): Update to match current
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implementations of LH, LW.
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(signal_exception): Don't print out incorrect hex value of illegal
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instruction.
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Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
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@ -1551,29 +1551,6 @@ ColdReset (SIM_DESC sd)
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}
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}
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unsigned16
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ifetch16 (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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address_word vaddr)
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{
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/* Copy the action of the LW instruction */
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address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
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address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
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unsigned64 value;
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address_word paddr;
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unsigned16 instruction;
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unsigned byte;
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int cca;
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AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
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paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
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LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
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byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
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instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
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return instruction;
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}
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/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
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/* Signal an exception condition. This will result in an exception
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that aborts the instruction. The instruction operation pseudocode
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@ -1677,7 +1654,7 @@ signal_exception (SIM_DESC sd,
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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/* else fall through to normal exception processing */
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sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
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sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
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}
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case BreakPoint:
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File diff suppressed because it is too large
Load Diff
@ -71,6 +71,33 @@
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// Helper:
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//
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// Simulate a 32 bit delayslot instruction
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//
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:function:::address_word:delayslot32:address_word target
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{
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instruction_word delay_insn;
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sim_events_slip (SD, 1);
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DSPC = CIA;
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CIA = CIA + 4; /* NOTE not mips16 */
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STATE |= simDELAYSLOT;
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delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
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idecode_issue (CPU_, delay_insn, (CIA));
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STATE &= ~simDELAYSLOT;
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return target;
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}
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:function:::address_word:nullify_next_insn32:
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{
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sim_events_slip (SD, 1);
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dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
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return CIA + 8;
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}
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//
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// Mips Architecture:
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//
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@ -131,12 +158,13 @@
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:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
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{
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signed32 temp = GPR[rs] + EXTEND16 (immediate);
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GPR[rt] = EXTEND32 (temp);
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TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
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GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
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TRACE_ALU_RESULT (GPR[rt]);
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}
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001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
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"addu r<RT>, r<RS>, <IMMEDIATE>"
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"addiu r<RT>, r<RS>, <IMMEDIATE>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr5000:
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// start-sanitize-vr4320
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@ -160,8 +188,9 @@
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:function:::void:do_addu:int rs, int rt, int rd
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{
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signed32 temp = GPR[rs] + GPR[rt];
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
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@ -189,7 +218,9 @@
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:function:::void:do_and:int rs, int rt, int rd
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = GPR[rs] & GPR[rt];
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
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@ -776,7 +807,9 @@
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:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
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{
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TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
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GPR[rt] = GPR[rs] + EXTEND16 (immediate);
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TRACE_ALU_RESULT (GPR[rt]);
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}
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011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
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@ -804,7 +837,9 @@
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:function:::void:do_daddu:int rs, int rt, int rd
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = GPR[rs] + GPR[rt];
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
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@ -832,6 +867,7 @@
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:function:64::void:do_ddiv:int rs, int rt
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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CHECKHILO ("Division");
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{
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signed64 n = GPR[rs];
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@ -852,6 +888,7 @@
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HI = (n % d);
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}
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}
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
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@ -879,6 +916,7 @@
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:function:64::void:do_ddivu:int rs, int rt
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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CHECKHILO ("Division");
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{
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unsigned64 n = GPR[rs];
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@ -894,6 +932,7 @@
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HI = (n % d);
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}
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}
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
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@ -918,6 +957,7 @@
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:function:::void:do_div:int rs, int rt
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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CHECKHILO("Division");
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{
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signed32 n = GPR[rs];
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@ -938,6 +978,7 @@
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HI = EXTEND32 (n % d);
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}
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}
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
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@ -965,6 +1006,7 @@
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:function:::void:do_divu:int rs, int rt
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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CHECKHILO ("Division");
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{
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unsigned32 n = GPR[rs];
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@ -980,6 +1022,7 @@
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HI = EXTEND32 (n % d);
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}
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}
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
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@ -1017,6 +1060,7 @@
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int sign;
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unsigned64 op1 = GPR[rs];
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unsigned64 op2 = GPR[rt];
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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CHECKHILO ("Multiplication");
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/* make signed multiply unsigned */
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sign = 0;
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@ -1061,6 +1105,7 @@
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HI = hi;
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if (rd != 0)
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GPR[rd] = lo;
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TRACE_ALU_RESULT2 (HI, LO);
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}
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:function:::void:do_dmult:int rs, int rt, int rd
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@ -1245,7 +1290,9 @@
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:function:::void:do_srav:int rs, int rt, int rd
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{
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int s = MASKED64 (GPR[rs], 5, 0);
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TRACE_ALU_INPUT2 (GPR[rt], s);
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GPR[rd] = ((signed64) GPR[rt]) >> s;
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
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@ -1365,7 +1412,9 @@
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:function:::void:do_dsubu:int rs, int rt, int rd
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = GPR[rs] - GPR[rt];
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
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@ -1983,7 +2032,9 @@
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:function:::void:do_mfhi:int rd
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{
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TRACE_ALU_INPUT1 (HI);
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GPR[rd] = HI;
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TRACE_ALU_RESULT (GPR[rd]);
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#if 0
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HIACCESS = 3;
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#endif
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@ -2014,7 +2065,9 @@
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:function:::void:do_mflo:int rd
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{
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TRACE_ALU_INPUT1 (LO);
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GPR[rd] = LO;
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TRACE_ALU_RESULT (GPR[rd]);
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#if 0
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LOACCESS = 3; /* 3rd instruction will be safe */
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#endif
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@ -2146,6 +2199,7 @@
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:function:::void:do_mult:int rs, int rt, int rd
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{
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signed64 prod;
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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CHECKHILO ("Multiplication");
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prod = (((signed64)(signed32) GPR[rs])
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* ((signed64)(signed32) GPR[rt]));
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@ -2153,6 +2207,7 @@
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HI = EXTEND32 (VH4_8 (prod));
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if (rd != 0)
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GPR[rd] = LO;
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
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@ -2187,6 +2242,7 @@
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:function:::void:do_multu:int rs, int rt, int rd
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{
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unsigned64 prod;
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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CHECKHILO ("Multiplication");
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prod = (((unsigned64)(unsigned32) GPR[rs])
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* ((unsigned64)(unsigned32) GPR[rt]));
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@ -2194,6 +2250,7 @@
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HI = EXTEND32 (VH4_8 (prod));
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if (rd != 0)
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GPR[rd] = LO;
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
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@ -2226,7 +2283,9 @@
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:function:::void:do_nor:int rs, int rt, int rd
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = ~ (GPR[rs] | GPR[rt]);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
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@ -2253,7 +2312,9 @@
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:function:::void:do_or:int rs, int rt, int rd
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = (GPR[rs] | GPR[rt]);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
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@ -2278,6 +2339,14 @@
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}
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:function:::void:do_ori:int rs, int rt, unsigned immediate
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{
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TRACE_ALU_INPUT2 (GPR[rs], immediate);
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GPR[rt] = (GPR[rs] | immediate);
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TRACE_ALU_RESULT (GPR[rt]);
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}
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001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
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"ori r<RT>, r<RS>, <IMMEDIATE>"
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*mipsI,mipsII,mipsIII,mipsIV:
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@ -2296,7 +2365,7 @@
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*tx19:
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// end-sanitize-tx19
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{
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GPR[RT] = (GPR[RS] | IMMEDIATE);
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do_ori (SD_, RS, RT, IMMEDIATE);
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}
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@ -2583,7 +2652,9 @@
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:function:::void:do_sll:int rt, int rd, int shift
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{
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unsigned32 temp = (GPR[rt] << shift);
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TRACE_ALU_INPUT2 (GPR[rt], shift);
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
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@ -2612,7 +2683,9 @@
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{
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int s = MASKED (GPR[rs], 4, 0);
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unsigned32 temp = (GPR[rt] << s);
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TRACE_ALU_INPUT2 (GPR[rt], s);
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
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@ -2639,7 +2712,9 @@
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:function:::void:do_slt:int rs, int rt, int rd
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
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@ -2666,7 +2741,9 @@
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:function:::void:do_slti:int rs, int rt, unsigned16 immediate
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{
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TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
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GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
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TRACE_ALU_RESULT (GPR[rt]);
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}
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001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
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@ -2693,7 +2770,9 @@
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:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
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{
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TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
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GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
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TRACE_ALU_RESULT (GPR[rt]);
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}
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001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
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@ -2721,7 +2800,9 @@
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:function:::void:do_sltu:int rs, int rt, int rd
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{
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
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@ -2742,14 +2823,16 @@
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*tx19:
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// end-sanitize-tx19
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{
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do_sltiu (SD_, RS, RT, RD);
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do_sltu (SD_, RS, RT, RD);
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}
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:function:::void:do_sra:int rt, int rd, int shift
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{
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signed32 temp = (signed32) GPR[rt] >> shift;
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TRACE_ALU_INPUT2 (GPR[rt], shift);
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
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@ -2801,7 +2884,9 @@
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:function:::void:do_srl:int rt, int rd, int shift
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{
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unsigned32 temp = (unsigned32) GPR[rt] >> shift;
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TRACE_ALU_INPUT2 (GPR[rt], shift);
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GPR[rd] = EXTEND32 (temp);
|
||||
TRACE_ALU_RESULT (GPR[rd]);
|
||||
}
|
||||
|
||||
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
|
||||
@ -2830,7 +2915,9 @@
|
||||
{
|
||||
int s = MASKED (GPR[rs], 4, 0);
|
||||
unsigned32 temp = (unsigned32) GPR[rt] >> s;
|
||||
TRACE_ALU_INPUT2 (GPR[rt], s);
|
||||
GPR[rd] = EXTEND32 (temp);
|
||||
TRACE_ALU_RESULT (GPR[rd]);
|
||||
}
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
|
||||
@ -2881,8 +2968,9 @@
|
||||
|
||||
:function:::void:do_subu:int rs, int rt, int rd
|
||||
{
|
||||
signed32 temp = GPR[rs] - GPR[rt];
|
||||
GPR[rd] = EXTEND32 (temp);
|
||||
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
||||
GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
|
||||
TRACE_ALU_RESULT (GPR[rd]);
|
||||
}
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
|
||||
@ -3376,7 +3464,9 @@
|
||||
|
||||
:function:::void:do_xor:int rs, int rt, int rd
|
||||
{
|
||||
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
||||
GPR[rd] = GPR[rs] ^ GPR[rt];
|
||||
TRACE_ALU_RESULT (GPR[rd]);
|
||||
}
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
|
||||
@ -3403,7 +3493,9 @@
|
||||
|
||||
:function:::void:do_xori:int rs, int rt, unsigned16 immediate
|
||||
{
|
||||
TRACE_ALU_INPUT2 (GPR[rs], immediate);
|
||||
GPR[rt] = GPR[rs] ^ immediate;
|
||||
TRACE_ALU_RESULT (GPR[rt]);
|
||||
}
|
||||
|
||||
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
|
||||
@ -5143,6 +5235,9 @@
|
||||
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
|
||||
"mtc0 r<RT>, r<RD> # <REGX>"
|
||||
*mipsI,mipsII,mipsIII,mipsIV:
|
||||
// start-sanitize-tx19
|
||||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
*r3900:
|
||||
// start-sanitize-vr4320
|
||||
*vr4320:
|
||||
@ -5219,7 +5314,7 @@
|
||||
// end-sanitize-r5900
|
||||
|
||||
|
||||
:include:16::m16.igen
|
||||
:include:::m16.igen
|
||||
// start-sanitize-vr4320
|
||||
:include::vr4320:vr4320.igen
|
||||
// end-sanitize-vr4320
|
||||
|
||||
@ -435,6 +435,7 @@ struct _sim_cpu {
|
||||
address_word dspc; /* delay-slot PC */
|
||||
#define DSPC ((CPU)->dspc)
|
||||
|
||||
#if !WITH_IGEN
|
||||
/* Issue a delay slot instruction immediatly by re-calling
|
||||
idecode_issue */
|
||||
#define DELAY_SLOT(TARGET) \
|
||||
@ -455,6 +456,11 @@ struct _sim_cpu {
|
||||
dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
|
||||
NIA = CIA + 8; \
|
||||
} while (0)
|
||||
#else
|
||||
#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
|
||||
#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
|
||||
#endif
|
||||
|
||||
|
||||
/* State of the simulator */
|
||||
unsigned int state;
|
||||
@ -866,7 +872,7 @@ prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
|
||||
|
||||
INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
||||
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
|
||||
unsigned16 ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
||||
INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
||||
#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
|
||||
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user