2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com> * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) (fp_nmsub): New prototypes. (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) (NegMultiplySub): New defines. * mips.igen (RSQRT.fmt): Use RSquareRoot(). (MADD.D, MADD.S): Replace with... (MADD.fmt): New instruction. (MSUB.D, MSUB.S): Replace with... (MSUB.fmt): New instruction. (NMADD.D, NMADD.S): Replace with... (NMADD.fmt): New instruction. (NMSUB.D, MSUB.S): Replace with... (NMSUB.fmt): New instruction.
This commit is contained in:
Chris Demetriou
parent
986b7daaef
commit
f3c08b7e16
@ -1,3 +1,22 @@
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2002-06-07 Chris Demetriou <cgd@broadcom.com>
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Ed Satterthwaite <ehs@broadcom.com>
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* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
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(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
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* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
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(fp_nmsub): New prototypes.
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(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
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(NegMultiplySub): New defines.
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* mips.igen (RSQRT.fmt): Use RSquareRoot().
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(MADD.D, MADD.S): Replace with...
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(MADD.fmt): New instruction.
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(MSUB.D, MSUB.S): Replace with...
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(MSUB.fmt): New instruction.
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(NMADD.D, NMADD.S): Replace with...
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(NMADD.fmt): New instruction.
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(NMSUB.D, MSUB.S): Replace with...
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(NMSUB.fmt): New instruction.
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2002-06-07 Chris Demetriou <cgd@broadcom.com>
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Ed Satterthwaite <ehs@broadcom.com>
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253
sim/mips/cp1.c
253
sim/mips/cp1.c
@ -672,6 +672,206 @@ fp_binary(sim_cpu *cpu,
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return result;
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}
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/* Common MAC code for single operands (.s or .d), defers setting FCSR. */
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static sim_fpu_status
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inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
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unsigned64 op1,
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unsigned64 op2,
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unsigned64 op3,
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int scale,
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int negate,
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FP_formats fmt,
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sim_fpu_round round,
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sim_fpu_denorm denorm,
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unsigned64 *result)
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu ans;
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sim_fpu_status status = 0;
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sim_fpu_status op_status;
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unsigned64 temp = 0;
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switch (fmt)
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{
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case fmt_single:
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{
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unsigned32 res;
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sim_fpu_32to (&wop1, op1);
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sim_fpu_32to (&wop2, op2);
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status |= sim_fpu_mul (&ans, &wop1, &wop2);
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if (scale != 0 && sim_fpu_is_number (&ans)) /* number or denorm */
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ans.normal_exp += scale;
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status |= sim_fpu_round_32 (&ans, round, denorm);
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wop1 = ans;
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op_status = 0;
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sim_fpu_32to (&wop2, op3);
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op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
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op_status |= sim_fpu_round_32 (&ans, round, denorm);
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status |= op_status;
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if (negate)
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{
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wop1 = ans;
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op_status = sim_fpu_neg (&ans, &wop1);
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op_status |= sim_fpu_round_32 (&ans, round, denorm);
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status |= op_status;
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}
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sim_fpu_to32 (&res, &ans);
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temp = res;
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break;
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}
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case fmt_double:
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{
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unsigned64 res;
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sim_fpu_64to (&wop1, op1);
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sim_fpu_64to (&wop2, op2);
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status |= sim_fpu_mul (&ans, &wop1, &wop2);
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if (scale != 0 && sim_fpu_is_number (&ans)) /* number or denorm */
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ans.normal_exp += scale;
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status |= sim_fpu_round_64 (&ans, round, denorm);
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wop1 = ans;
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op_status = 0;
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sim_fpu_64to (&wop2, op3);
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op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
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op_status |= sim_fpu_round_64 (&ans, round, denorm);
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status |= op_status;
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if (negate)
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{
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wop1 = ans;
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op_status = sim_fpu_neg (&ans, &wop1);
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op_status |= sim_fpu_round_64 (&ans, round, denorm);
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status |= op_status;
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}
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sim_fpu_to64 (&res, &ans);
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temp = res;
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break;
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}
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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*result = temp;
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return status;
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}
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/* Common implementation of madd, nmadd, msub, nmsub that does
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intermediate rounding per spec. Also used for recip2 and rsqrt2,
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which are transformed into equivalent nmsub operations. The scale
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argument is an adjustment to the exponent of the intermediate
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product op1*op2. It is currently non-zero for rsqrt2 (-1), which
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requires an effective division by 2. */
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static unsigned64
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fp_mac(sim_cpu *cpu,
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address_word cia,
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int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
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unsigned64 op1,
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unsigned64 op2,
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unsigned64 op3,
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int scale,
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int negate,
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FP_formats fmt)
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{
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sim_fpu_round round = rounding_mode (GETRM());
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sim_fpu_denorm denorm = denorm_mode (cpu);
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sim_fpu_status status = 0;
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unsigned64 result = 0;
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/* The format type has already been checked: */
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switch (fmt)
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{
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case fmt_single:
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case fmt_double:
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status = inner_mac(sim_fpu_op, op1, op2, op3, scale,
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negate, fmt, round, denorm, &result);
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break;
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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}
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update_fcsr (cpu, cia, status);
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return result;
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}
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/* Common rsqrt code for single operands (.s or .d), intermediate rounding. */
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static sim_fpu_status
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inner_rsqrt(unsigned64 op1,
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FP_formats fmt,
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sim_fpu_round round,
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sim_fpu_denorm denorm,
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unsigned64 *result)
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{
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sim_fpu wop1;
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sim_fpu ans;
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sim_fpu_status status = 0;
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sim_fpu_status op_status;
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unsigned64 temp = 0;
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switch (fmt)
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{
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case fmt_single:
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{
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unsigned32 res;
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sim_fpu_32to (&wop1, op1);
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status |= sim_fpu_sqrt (&ans, &wop1);
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status |= sim_fpu_round_32 (&ans, status, round);
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wop1 = ans;
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op_status = sim_fpu_inv (&ans, &wop1);
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op_status |= sim_fpu_round_32 (&ans, round, denorm);
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sim_fpu_to32 (&res, &ans);
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temp = res;
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status |= op_status;
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break;
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}
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case fmt_double:
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{
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unsigned64 res;
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sim_fpu_64to (&wop1, op1);
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status |= sim_fpu_sqrt (&ans, &wop1);
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status |= sim_fpu_round_64 (&ans, round, denorm);
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wop1 = ans;
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op_status = sim_fpu_inv (&ans, &wop1);
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op_status |= sim_fpu_round_64 (&ans, round, denorm);
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sim_fpu_to64 (&res, &ans);
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temp = res;
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status |= op_status;
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break;
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}
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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*result = temp;
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return status;
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}
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static unsigned64
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fp_inv_sqrt(sim_cpu *cpu,
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address_word cia,
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unsigned64 op1,
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FP_formats fmt)
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{
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sim_fpu_round round = rounding_mode (GETRM());
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sim_fpu_round denorm = denorm_mode (cpu);
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sim_fpu_status status = 0;
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unsigned64 result = 0;
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/* The format type has already been checked: */
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switch (fmt)
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{
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case fmt_single:
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case fmt_double:
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status = inner_rsqrt (op1, fmt, round, denorm, &result);
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break;
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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}
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update_fcsr (cpu, cia, status);
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return result;
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}
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unsigned64
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fp_abs(sim_cpu *cpu,
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@ -749,6 +949,59 @@ fp_sqrt(sim_cpu *cpu,
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return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt);
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}
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unsigned64
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fp_rsqrt(sim_cpu *cpu,
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address_word cia,
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unsigned64 op,
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FP_formats fmt)
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{
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return fp_inv_sqrt(cpu, cia, op, fmt);
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}
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unsigned64
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fp_madd(sim_cpu *cpu,
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address_word cia,
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unsigned64 op1,
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unsigned64 op2,
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unsigned64 op3,
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FP_formats fmt)
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{
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return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 0, fmt);
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}
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unsigned64
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fp_msub(sim_cpu *cpu,
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address_word cia,
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unsigned64 op1,
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unsigned64 op2,
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unsigned64 op3,
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FP_formats fmt)
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{
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return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt);
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}
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unsigned64
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fp_nmadd(sim_cpu *cpu,
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address_word cia,
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unsigned64 op1,
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unsigned64 op2,
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unsigned64 op3,
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FP_formats fmt)
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{
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return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 1, fmt);
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}
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unsigned64
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fp_nmsub(sim_cpu *cpu,
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address_word cia,
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unsigned64 op1,
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unsigned64 op2,
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unsigned64 op3,
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FP_formats fmt)
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{
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return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 1, fmt);
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}
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/* Conversion operations. */
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@ -4198,34 +4198,19 @@
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//
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// FIXME: Not correct for mips*
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//
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010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
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"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
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010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
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"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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int fmt = FMT;
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check_fpu (SD_);
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{
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StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
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}
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}
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010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
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"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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check_fpu (SD_);
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{
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StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
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}
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
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ValueFPR (FR, fmt), fmt));
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}
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@ -4354,29 +4339,19 @@
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}
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// MSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
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"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
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010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
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"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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int fmt = FMT;
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check_fpu (SD_);
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StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
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}
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// MSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
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"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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check_fpu (SD_);
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StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
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ValueFPR (FR, fmt), fmt));
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}
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@ -4449,55 +4424,35 @@
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}
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// NMADD.fmt
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010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
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"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
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010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
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"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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int fmt = FMT;
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check_fpu (SD_);
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StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
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ValueFPR (FR, fmt), fmt));
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}
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// NMADD.fmt
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010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
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"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
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010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
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"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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int fmt = FMT;
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check_fpu (SD_);
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StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
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}
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// NMSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
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"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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check_fpu (SD_);
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StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
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}
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// NMSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
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"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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*mips64:
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*vr5000:
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{
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check_fpu (SD_);
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StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
|
||||
StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
||||
ValueFPR (FR, fmt), fmt));
|
||||
}
|
||||
|
||||
|
||||
@ -4579,7 +4534,7 @@
|
||||
int fmt = FMT;
|
||||
check_fpu (SD_);
|
||||
check_fmt (SD_, fmt, instruction_0);
|
||||
StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
|
||||
StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -704,6 +704,20 @@ unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
|
||||
#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
|
||||
unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
|
||||
#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
|
||||
unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
|
||||
#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
|
||||
unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
|
||||
unsigned64 op3, FP_formats fmt);
|
||||
#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
|
||||
unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
|
||||
unsigned64 op3, FP_formats fmt);
|
||||
#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
|
||||
unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
|
||||
unsigned64 op3, FP_formats fmt);
|
||||
#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
|
||||
unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
|
||||
unsigned64 op3, FP_formats fmt);
|
||||
#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
|
||||
unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
|
||||
#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user