Add 128 bit transfers to sim core.
This commit is contained in:
Andrew Cagney
parent
635ae9cb7c
commit
f45dd42b32
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@ -1,3 +1,17 @@
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Mon Oct 27 12:00:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-endian.c (_SWAP_16): Define. Generate 126 bit swap code.
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* sim-n-core.h (sim_core_trace_N): New function.
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(sim_core_read_aligned_N, sim_core_write_aligned_N): Use,
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(sim_core_read_unaligned_N): Do not retyrn bogus value wden error.
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* sim-endian.h: Add 128 bit variant.
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* sim-core.h, sim-core.c: Add 128 bit variant.
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* sim-types.h: Add signed128 and unsigned128 types using a struct.
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Fri Oct 24 11:33:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-events.c (sim_events_process): Clear events->work_pending.
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@ -760,7 +760,7 @@ sim_core_xor_write_buffer (SIM_DESC sd,
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/* define the read/write 1/2/4/8/word functions */
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/* define the read/write 1/2/4/8/16/word functions */
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#define N 1
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#include "sim-n-core.h"
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@ -778,6 +778,10 @@ sim_core_xor_write_buffer (SIM_DESC sd,
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#include "sim-n-core.h"
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#undef N
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#define N 16
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#include "sim-n-core.h"
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#undef N
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#define N word
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#include "sim-n-core.h"
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#undef N
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@ -247,18 +247,20 @@ DECLARE_SIM_CORE_WRITE_N(aligned,1)
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DECLARE_SIM_CORE_WRITE_N(aligned,2)
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DECLARE_SIM_CORE_WRITE_N(aligned,4)
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DECLARE_SIM_CORE_WRITE_N(aligned,8)
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DECLARE_SIM_CORE_WRITE_N(aligned,16)
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DECLARE_SIM_CORE_WRITE_N(aligned,word)
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DECLARE_SIM_CORE_WRITE_N(unaligned,1)
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DECLARE_SIM_CORE_WRITE_N(unaligned,2)
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DECLARE_SIM_CORE_WRITE_N(unaligned,4)
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DECLARE_SIM_CORE_WRITE_N(unaligned,8)
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DECLARE_SIM_CORE_WRITE_N(unaligned,16)
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DECLARE_SIM_CORE_WRITE_N(unaligned,word)
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#define sim_core_write_1 sim_core_write_aligned_1
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#define sim_core_write_2 sim_core_write_aligned_2
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#define sim_core_write_4 sim_core_write_aligned_4
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#define sim_core_write_8 sim_core_write_aligned_8
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#define sim_core_write_16 sim_core_write_aligned_16
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#undef DECLARE_SIM_CORE_WRITE_N
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@ -275,18 +277,21 @@ DECLARE_SIM_CORE_READ_N(aligned,1)
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DECLARE_SIM_CORE_READ_N(aligned,2)
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DECLARE_SIM_CORE_READ_N(aligned,4)
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DECLARE_SIM_CORE_READ_N(aligned,8)
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DECLARE_SIM_CORE_READ_N(aligned,16)
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DECLARE_SIM_CORE_READ_N(aligned,word)
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DECLARE_SIM_CORE_READ_N(unaligned,1)
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DECLARE_SIM_CORE_READ_N(unaligned,2)
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DECLARE_SIM_CORE_READ_N(unaligned,4)
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DECLARE_SIM_CORE_READ_N(unaligned,8)
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DECLARE_SIM_CORE_READ_N(unaligned,16)
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DECLARE_SIM_CORE_READ_N(unaligned,word)
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#define sim_core_read_1 sim_core_read_aligned_1
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#define sim_core_read_2 sim_core_read_aligned_2
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#define sim_core_read_4 sim_core_read_aligned_4
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#define sim_core_read_8 sim_core_read_aligned_8
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#define sim_core_read_16 sim_core_read_aligned_16
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#undef DECLARE_SIM_CORE_READ_N
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@ -23,6 +23,8 @@
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#define _SIM_ENDIAN_C_
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#include "sim-basics.h"
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#include "sim-assert.h"
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#include "sim-io.h"
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#if !defined(_SWAP_1)
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@ -54,6 +56,17 @@
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SET out.dword;
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#endif
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#ifndef _SWAP_16
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#define _SWAP_16(SET,RAW) \
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union { unsigned_16 word; unsigned_4 words[4]; } in, out; \
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in.word = (RAW); \
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_SWAP_4 (out.words[0] =, in.words[3]); \
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_SWAP_4 (out.words[1] =, in.words[2]); \
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_SWAP_4 (out.words[2] =, in.words[1]); \
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_SWAP_4 (out.words[3] =, in.words[0]); \
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SET out.word;
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#endif
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#define N 1
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#include "sim-n-endian.h"
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@ -71,4 +84,8 @@
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#include "sim-n-endian.h"
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#undef N
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#define N 16
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#include "sim-n-endian.h"
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#undef N
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#endif /* _SIM_ENDIAN_C_ */
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@ -30,41 +30,49 @@ INLINE_SIM_ENDIAN(unsigned_1) endian_h2t_1(unsigned_1 x);
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INLINE_SIM_ENDIAN(unsigned_2) endian_h2t_2(unsigned_2 x);
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INLINE_SIM_ENDIAN(unsigned_4) endian_h2t_4(unsigned_4 x);
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INLINE_SIM_ENDIAN(unsigned_8) endian_h2t_8(unsigned_8 x);
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INLINE_SIM_ENDIAN(unsigned_16) endian_h2t_16(unsigned_16 x);
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INLINE_SIM_ENDIAN(unsigned_1) endian_t2h_1(unsigned_1 x);
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INLINE_SIM_ENDIAN(unsigned_2) endian_t2h_2(unsigned_2 x);
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INLINE_SIM_ENDIAN(unsigned_4) endian_t2h_4(unsigned_4 x);
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INLINE_SIM_ENDIAN(unsigned_8) endian_t2h_8(unsigned_8 x);
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INLINE_SIM_ENDIAN(unsigned_16) endian_t2h_16(unsigned_16 x);
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INLINE_SIM_ENDIAN(unsigned_1) swap_1(unsigned_1 x);
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INLINE_SIM_ENDIAN(unsigned_2) swap_2(unsigned_2 x);
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INLINE_SIM_ENDIAN(unsigned_4) swap_4(unsigned_4 x);
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INLINE_SIM_ENDIAN(unsigned_8) swap_8(unsigned_8 x);
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INLINE_SIM_ENDIAN(unsigned_16) swap_16(unsigned_16 x);
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INLINE_SIM_ENDIAN(unsigned_1) endian_h2be_1(unsigned_1 x);
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INLINE_SIM_ENDIAN(unsigned_2) endian_h2be_2(unsigned_2 x);
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INLINE_SIM_ENDIAN(unsigned_4) endian_h2be_4(unsigned_4 x);
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INLINE_SIM_ENDIAN(unsigned_8) endian_h2be_8(unsigned_8 x);
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INLINE_SIM_ENDIAN(unsigned_16) endian_h2be_16(unsigned_16 x);
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INLINE_SIM_ENDIAN(unsigned_1) endian_be2h_1(unsigned_1 x);
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INLINE_SIM_ENDIAN(unsigned_2) endian_be2h_2(unsigned_2 x);
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INLINE_SIM_ENDIAN(unsigned_4) endian_be2h_4(unsigned_4 x);
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INLINE_SIM_ENDIAN(unsigned_8) endian_be2h_8(unsigned_8 x);
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INLINE_SIM_ENDIAN(unsigned_16) endian_be2h_16(unsigned_16 x);
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INLINE_SIM_ENDIAN(unsigned_1) endian_h2le_1(unsigned_1 x);
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INLINE_SIM_ENDIAN(unsigned_2) endian_h2le_2(unsigned_2 x);
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INLINE_SIM_ENDIAN(unsigned_4) endian_h2le_4(unsigned_4 x);
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INLINE_SIM_ENDIAN(unsigned_8) endian_h2le_8(unsigned_8 x);
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INLINE_SIM_ENDIAN(unsigned_16) endian_h2le_16(unsigned_16 x);
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INLINE_SIM_ENDIAN(unsigned_1) endian_le2h_1(unsigned_1 x);
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INLINE_SIM_ENDIAN(unsigned_2) endian_le2h_2(unsigned_2 x);
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INLINE_SIM_ENDIAN(unsigned_4) endian_le2h_4(unsigned_4 x);
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INLINE_SIM_ENDIAN(unsigned_8) endian_le2h_8(unsigned_8 x);
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INLINE_SIM_ENDIAN(unsigned_16) endian_le2h_16(unsigned_16 x);
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INLINE_SIM_ENDIAN(void*) offset_1(unsigned_1 *x, int ws, int w);
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INLINE_SIM_ENDIAN(void*) offset_2(unsigned_2 *x, int ws, int w);
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INLINE_SIM_ENDIAN(void*) offset_4(unsigned_4 *x, int ws, int w);
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INLINE_SIM_ENDIAN(void*) offset_8(unsigned_8 *x, int ws, int w);
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INLINE_SIM_ENDIAN(void*) offset_1(unsigned_1 *x, unsigned ws, unsigned w);
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INLINE_SIM_ENDIAN(void*) offset_2(unsigned_2 *x, unsigned ws, unsigned w);
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INLINE_SIM_ENDIAN(void*) offset_4(unsigned_4 *x, unsigned ws, unsigned w);
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INLINE_SIM_ENDIAN(void*) offset_8(unsigned_8 *x, unsigned ws, unsigned w);
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INLINE_SIM_ENDIAN(void*) offset_16(unsigned_16 *x, unsigned ws, unsigned w);
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/* SWAP */
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@ -73,6 +81,7 @@ INLINE_SIM_ENDIAN(void*) offset_8(unsigned_8 *x, int ws, int w);
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#define SWAP_2(X) swap_2(X)
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#define SWAP_4(X) swap_4(X)
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#define SWAP_8(X) swap_8(X)
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#define SWAP_16(X) swap_16(X)
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/* HOST to BE */
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@ -81,10 +90,12 @@ INLINE_SIM_ENDIAN(void*) offset_8(unsigned_8 *x, int ws, int w);
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#define H2BE_2(X) endian_h2be_2(X)
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#define H2BE_4(X) endian_h2be_4(X)
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#define H2BE_8(X) endian_h2be_8(X)
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#define H2BE_16(X) endian_h2be_16(X)
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#define BE2H_1(X) endian_be2h_1(X)
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#define BE2H_2(X) endian_be2h_2(X)
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#define BE2H_4(X) endian_be2h_4(X)
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#define BE2H_8(X) endian_be2h_8(X)
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#define BE2H_16(X) endian_be2h_16(X)
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/* HOST to LE */
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@ -93,10 +104,12 @@ INLINE_SIM_ENDIAN(void*) offset_8(unsigned_8 *x, int ws, int w);
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#define H2LE_2(X) endian_h2le_2(X)
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#define H2LE_4(X) endian_h2le_4(X)
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#define H2LE_8(X) endian_h2le_8(X)
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#define H2LE_16(X) endian_h2le_16(X)
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#define LE2H_1(X) endian_le2h_1(X)
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#define LE2H_2(X) endian_le2h_2(X)
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#define LE2H_4(X) endian_le2h_4(X)
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#define LE2H_8(X) endian_le2h_8(X)
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#define LE2H_16(X) endian_le2h_16(X)
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/* HOST to TARGET */
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@ -105,10 +118,12 @@ INLINE_SIM_ENDIAN(void*) offset_8(unsigned_8 *x, int ws, int w);
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#define H2T_2(X) endian_h2t_2(X)
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#define H2T_4(X) endian_h2t_4(X)
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#define H2T_8(X) endian_h2t_8(X)
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#define H2T_16(X) endian_h2t_16(X)
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#define T2H_1(X) endian_t2h_1(X)
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#define T2H_2(X) endian_t2h_2(X)
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#define T2H_4(X) endian_t2h_4(X)
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#define T2H_8(X) endian_t2h_8(X)
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#define T2H_16(X) endian_t2h_16(X)
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/* CONVERT IN PLACE
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@ -123,6 +138,7 @@ do { \
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case 2: VARIABLE = H2T_2(VARIABLE); break; \
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case 4: VARIABLE = H2T_4(VARIABLE); break; \
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case 8: VARIABLE = H2T_8(VARIABLE); break; \
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case 16: VARIABLE = H2T_16(VARIABLE); break; \
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} \
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} while (0)
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@ -133,6 +149,7 @@ do { \
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case 2: VARIABLE = T2H_2(VARIABLE); break; \
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case 4: VARIABLE = T2H_4(VARIABLE); break; \
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case 8: VARIABLE = T2H_8(VARIABLE); break; \
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case 16: VARIABLE = T2H_16(VARIABLE); break; \
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} \
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} while (0)
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@ -143,6 +160,7 @@ do { \
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case 2: VARIABLE = SWAP_2(VARIABLE); break; \
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case 4: VARIABLE = SWAP_4(VARIABLE); break; \
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case 8: VARIABLE = SWAP_8(VARIABLE); break; \
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case 16: VARIABLE = SWAP_16(VARIABLE); break; \
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} \
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} while (0)
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@ -153,6 +171,7 @@ do { \
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case 2: VARIABLE = H2BE_2(VARIABLE); break; \
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case 4: VARIABLE = H2BE_4(VARIABLE); break; \
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case 8: VARIABLE = H2BE_8(VARIABLE); break; \
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case 16: VARIABLE = H2BE_16(VARIABLE); break; \
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} \
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} while (0)
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@ -163,6 +182,7 @@ do { \
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case 2: VARIABLE = BE2H_2(VARIABLE); break; \
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case 4: VARIABLE = BE2H_4(VARIABLE); break; \
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case 8: VARIABLE = BE2H_8(VARIABLE); break; \
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case 16: VARIABLE = BE2H_16(VARIABLE); break; \
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} \
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} while (0)
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@ -173,6 +193,7 @@ do { \
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case 2: VARIABLE = H2LE_2(VARIABLE); break; \
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case 4: VARIABLE = H2LE_4(VARIABLE); break; \
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case 8: VARIABLE = H2LE_8(VARIABLE); break; \
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case 16: VARIABLE = H2LE_16(VARIABLE); break; \
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} \
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} while (0)
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@ -183,6 +204,7 @@ do { \
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case 2: VARIABLE = LE2H_2(VARIABLE); break; \
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case 4: VARIABLE = LE2H_4(VARIABLE); break; \
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case 8: VARIABLE = LE2H_8(VARIABLE); break; \
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case 16: VARIABLE = LE2H_16(VARIABLE); break; \
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} \
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} while (0)
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@ -243,6 +265,9 @@ do { \
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#define AH4_8(X) (unsigned_4*)offset_8((X), 4, 0)
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#define AL4_8(X) (unsigned_4*)offset_8((X), 4, 1)
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#define AH8_16(X) (unsigned_8*)offset_16((X), 8, 0)
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#define AL8_16(X) (unsigned_8*)offset_16((X), 8, 1)
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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#define AH_word(X) AH4_8(X)
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#define AL_word(X) AL4_8(X)
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@ -262,6 +287,10 @@ do { \
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#define A2_8(X,N) (unsigned_2*)offset_8((X), 2, (N))
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#define A4_8(X,N) (unsigned_4*)offset_8((X), 4, (N))
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#define A1_16(X,N) (unsigned_1*)offset_16((X), 1, (N))
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#define A2_16(X,N) (unsigned_2*)offset_16((X), 2, (N))
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#define A4_16(X,N) (unsigned_4*)offset_16((X), 4, (N))
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#define A8_16(X,N) (unsigned_8*)offset_16((X), 8, (N))
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#define VH4_8(X) ((unsigned_4)((unsigned_8)(X) >> 32))
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#define VL4_8(X) ((unsigned_4)(X))
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#define VH8_16(X) ((unsigned_8)((unsigned_16)(X) >> 64))
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#define VL8_16(X) ((unsigned_8)(X))
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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#define VH_word(X) VH4_8(X)
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#define VL_word(X) VL4_8(X)
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#define V1_2(X,N) ((unsigned_1)((unsigned_2)(X) >> ( 8 * (1 - (N)))))
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#define V1_4(X,N) ((unsigned_1)((unsigned_4)(X) >> ( 8 * (3 - (N)))))
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#define V1_8(X,N) ((unsigned_1)((unsigned_8)(X) >> ( 8 * (7 - (N)))))
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#define V2_4(X,N) ((unsigned_2)((unsigned_4)(X) >> (16 * (1 - (N)))))
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#define V2_8(X,N) ((unsigned_2)((unsigned_8)(X) >> (16 * (3 - (N)))))
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#define V1_8(X,N) ((unsigned_1)((unsigned_8)(X) >> ( 8 * (7 - (N)))))
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#define V2_8(X,N) ((unsigned_2)((unsigned_8)(X) >> (16 * (3 - (N)))))
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#define V4_8(X,N) ((unsigned_4)((unsigned_8)(X) >> (32 * (1 - (N)))))
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#define V1_16(X,N) (*A1_16 (&(X),N))
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#define V2_16(X,N) (*A2_16 (&(X),N))
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#define V4_16(X,N) (*A4_16 (&(X),N))
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#define V8_16(X,N) (*A8_16 (&(X),N))
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/* Reverse - insert sub-word into word quantity */
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@ -310,16 +347,24 @@ do { \
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#define V8_H4(X) ((unsigned_8)(unsigned_4)(X) << 32)
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#define V8_L4(X) ((unsigned_8)(unsigned_4)(X))
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#define V16_H8(X) ((unsigned_16)(unsigned_8)(X) << 64)
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#define V16_L8(X) ((unsigned_16)(unsigned_8)(X))
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#define V2_1(X,N) ((unsigned_2)(unsigned_1)(X) << ( 8 * (1 - (N))))
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#define V4_1(X,N) ((unsigned_4)(unsigned_1)(X) << ( 8 * (3 - (N))))
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#define V8_1(X,N) ((unsigned_8)(unsigned_1)(X) << ( 8 * (7 - (N))))
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#define V4_2(X,N) ((unsigned_4)(unsigned_2)(X) << (16 * (1 - (N))))
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#define V8_2(X,N) ((unsigned_8)(unsigned_2)(X) << (16 * (3 - (N))))
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#define V8_1(X,N) ((unsigned_8)(unsigned_1)(X) << ( 8 * (7 - (N))))
|
||||
#define V8_2(X,N) ((unsigned_8)(unsigned_2)(X) << (16 * (3 - (N))))
|
||||
#define V8_4(X,N) ((unsigned_8)(unsigned_4)(X) << (32 * (1 - (N))))
|
||||
|
||||
#define V16_1(X,N) ((unsigned_16)(unsigned_1)(X) << ( 8 * (15 - (N))))
|
||||
#define V16_2(X,N) ((unsigned_16)(unsigned_2)(X) << (16 * (7 - (N))))
|
||||
#define V16_4(X,N) ((unsigned_16)(unsigned_4)(X) << (32 * (3 - (N))))
|
||||
#define V16_8(X,N) ((unsigned_16)(unsigned_8)(X) << (64 * (1 - (N))))
|
||||
|
||||
|
||||
/* Reverse - insert N sub-words into single word quantity */
|
||||
|
||||
|
|
@ -328,11 +373,22 @@ do { \
|
|||
#define U8_1(I0,I1,I2,I3,I4,I5,I6,I7) \
|
||||
(V8_1(I0,0) | V8_1(I1,1) | V8_1(I2,2) | V8_1(I3,3) \
|
||||
| V8_1(I4,4) | V8_1(I5,5) | V8_1(I6,6) | V8_1(I7,7))
|
||||
#define U16_1(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15) \
|
||||
(V16_1(I0,0) | V16_1(I1,1) | V16_1(I2,2) | V16_1(I3,3) \
|
||||
| V16_1(I4,4) | V16_1(I5,5) | V16_1(I6,6) | V16_1(I7,7) \
|
||||
| V16_1(I8,8) | V16_1(I9,9) | V16_1(I10,10) | V16_1(I11,11) \
|
||||
| V16_1(I12,12) | V16_1(I13,13) | V16_1(I14,14) | V16_1(I15,15))
|
||||
|
||||
#define U4_2(I0,I1) (V4_2(I0,0) | V4_2(I1,1))
|
||||
#define U8_2(I0,I1,I2,I3) (V8_2(I0,0) | V8_2(I1,1) | V8_2(I2,2) | V8_2(I3,3))
|
||||
#define U16_2(I0,I1,I2,I3,I4,I5,I6,I7) \
|
||||
(V16_2(I0,0) | V16_2(I1,1) | V16_2(I2,2) | V16_2(I3,3) \
|
||||
| V16_2(I4,4) | V16_2(I5,5) | V16_2(I6,6) | V16_2(I7,7) )
|
||||
|
||||
#define U8_4(I0,I1) (V8_4(I0,0) | V8_4(I1,1))
|
||||
#define U16_4(I0,I1,I2,I3) (V16_4(I0,0) | V16_4(I1,1) | V16_4(I2,2) | V16_4(I3,3))
|
||||
|
||||
#define U16_8(I0,I1) (V16_8(I0,0) | V16_8(I1,1))
|
||||
|
||||
|
||||
#if (WITH_TARGET_WORD_BITSIZE == 64)
|
||||
|
|
@ -347,8 +403,6 @@ do { \
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
#if (SIM_ENDIAN_INLINE & INCLUDE_MODULE)
|
||||
# include "sim-endian.c"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -34,10 +34,59 @@
|
|||
#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
|
||||
#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
|
||||
#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
|
||||
#define sim_core_trace_N XCONCAT2(sim_core_trace_,N)
|
||||
|
||||
|
||||
/* TAGS: sim_core_trace_1 sim_core_trace_2 */
|
||||
/* TAGS: sim_core_trace_4 sim_core_trace_8 */
|
||||
/* TAGS: sim_core_trace_6 sim_core_trace_word */
|
||||
|
||||
STATIC_SIM_CORE(void)
|
||||
sim_core_trace_N (sim_cpu *cpu,
|
||||
sim_cia cia,
|
||||
char *transfer,
|
||||
sim_core_maps map,
|
||||
address_word addr,
|
||||
unsigned_N val)
|
||||
{
|
||||
#if (N == 16)
|
||||
trace_printf (CPU_STATE (cpu), cpu,
|
||||
"sim-n-core.h:%d: %s-%d %s:0x%08lx -> 0x%08lx%08lx%08lx%08lx\n",
|
||||
__LINE__,
|
||||
transfer, sizeof (unsigned_N),
|
||||
sim_core_map_to_str (map),
|
||||
(unsigned long) addr,
|
||||
(unsigned long) V4_16 (val, 0),
|
||||
(unsigned long) V4_16 (val, 1),
|
||||
(unsigned long) V4_16 (val, 2),
|
||||
(unsigned long) V4_16 (val, 3));
|
||||
#endif
|
||||
#if (N == 8)
|
||||
trace_printf (CPU_STATE (cpu), cpu,
|
||||
"sim-n-core.h:%d: %s-%d %s:0x%08lx -> 0x%08lx%08lx\n",
|
||||
__LINE__,
|
||||
transfer, sizeof (unsigned_N),
|
||||
sim_core_map_to_str (map),
|
||||
(unsigned long) addr,
|
||||
(unsigned long) V4_8 (val, 0),
|
||||
(unsigned long) V4_8 (val, 1));
|
||||
#endif
|
||||
#if (N == 4)
|
||||
trace_printf (CPU_STATE (cpu), cpu,
|
||||
"sim-n-core.h:%d: %s-%d %s:0x%08lx -> 0x%0*lx\n",
|
||||
__LINE__,
|
||||
transfer, sizeof (unsigned_N),
|
||||
sim_core_map_to_str (map),
|
||||
(unsigned long) addr,
|
||||
sizeof (unsigned_N) * 2,
|
||||
(unsigned long) val);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
|
||||
/* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
|
||||
/* TAGS: sim_core_read_aligned_word */
|
||||
/* TAGS: sim_core_read_aligned_16 sim_core_read_aligned_word */
|
||||
|
||||
INLINE_SIM_CORE(unsigned_N)
|
||||
sim_core_read_aligned_N(sim_cpu *cpu,
|
||||
|
|
@ -78,30 +127,13 @@ sim_core_read_aligned_N(sim_cpu *cpu,
|
|||
val = T2H_N (*(unsigned_N*) sim_core_translate (mapping, addr));
|
||||
PROFILE_COUNT_CORE (cpu, addr, sizeof (unsigned_N), map);
|
||||
if (TRACE_P (cpu, TRACE_CORE_IDX))
|
||||
if (sizeof (unsigned_N) > 4)
|
||||
trace_printf (CPU_STATE (cpu), cpu,
|
||||
"sim-n-core.h:%d: read-%d %s:0x%08lx -> 0x%08lx%08lx\n",
|
||||
__LINE__,
|
||||
sizeof (unsigned_N),
|
||||
sim_core_map_to_str (map),
|
||||
(unsigned long) addr,
|
||||
(unsigned long) (((unsigned64)(val)) >> 32),
|
||||
(unsigned long) val);
|
||||
else
|
||||
trace_printf (CPU_STATE (cpu), cpu,
|
||||
"sim-n-core.h:%d: read-%d %s:0x%08lx -> 0x%0*lx\n",
|
||||
__LINE__,
|
||||
sizeof (unsigned_N),
|
||||
sim_core_map_to_str (map),
|
||||
(unsigned long) addr,
|
||||
sizeof (unsigned_N) * 2,
|
||||
(unsigned long) val);
|
||||
sim_core_trace_N (cpu, __LINE__, "read", map, addr, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
/* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
|
||||
/* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
|
||||
/* TAGS: sim_core_read_unaligned_word */
|
||||
/* TAGS: sim_core_read_unaligned_16 sim_core_read_unaligned_word */
|
||||
|
||||
INLINE_SIM_CORE(unsigned_N)
|
||||
sim_core_read_unaligned_N(sim_cpu *cpu,
|
||||
|
|
@ -122,7 +154,6 @@ sim_core_read_unaligned_N(sim_cpu *cpu,
|
|||
SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map,
|
||||
sizeof (unsigned_N), addr,
|
||||
read_transfer, sim_core_unaligned_signal);
|
||||
return -1;
|
||||
case NONSTRICT_ALIGNMENT:
|
||||
{
|
||||
unsigned_N val;
|
||||
|
|
@ -142,18 +173,16 @@ sim_core_read_unaligned_N(sim_cpu *cpu,
|
|||
sim_engine_abort (CPU_STATE (cpu), cpu, cia,
|
||||
"internal error - %s - mixed alignment",
|
||||
XSTRING (sim_core_read_unaligned_N));
|
||||
return 0;
|
||||
default:
|
||||
sim_engine_abort (CPU_STATE (cpu), cpu, cia,
|
||||
"internal error - %s - bad switch",
|
||||
XSTRING (sim_core_read_unaligned_N));
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
|
||||
/* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
|
||||
/* TAGS: sim_core_write_aligned_word */
|
||||
/* TAGS: sim_core_write_aligned_16 sim_core_write_aligned_word */
|
||||
|
||||
INLINE_SIM_CORE(void)
|
||||
sim_core_write_aligned_N(sim_cpu *cpu,
|
||||
|
|
@ -195,29 +224,12 @@ sim_core_write_aligned_N(sim_cpu *cpu,
|
|||
*(unsigned_N*) sim_core_translate (mapping, addr) = H2T_N (val);
|
||||
PROFILE_COUNT_CORE (cpu, addr, sizeof (unsigned_N), map);
|
||||
if (TRACE_P (cpu, TRACE_CORE_IDX))
|
||||
if (sizeof (unsigned_N) > 4)
|
||||
trace_printf (CPU_STATE (cpu), cpu,
|
||||
"sim-n-core.h:%d: write-%d %s:0x%08lx <- 0x%08lx%08lx\n",
|
||||
__LINE__,
|
||||
sizeof (unsigned_N),
|
||||
sim_core_map_to_str (map),
|
||||
(unsigned long) addr,
|
||||
(unsigned long) (((unsigned64)(val)) >> 32),
|
||||
(unsigned long) val);
|
||||
else
|
||||
trace_printf (CPU_STATE (cpu), cpu,
|
||||
"sim-n-core.h:%d: write-%d %s:0x%08lx <- 0x%0*lx\n",
|
||||
__LINE__,
|
||||
sizeof (unsigned_N),
|
||||
sim_core_map_to_str (map),
|
||||
(unsigned long) addr,
|
||||
sizeof (unsigned_N) * 2,
|
||||
(unsigned long) val);
|
||||
sim_core_trace_N (cpu, __LINE__, "write", map, addr, val);
|
||||
}
|
||||
|
||||
/* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
|
||||
/* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
|
||||
/* TAGS: sim_core_write_unaligned_word */
|
||||
/* TAGS: sim_core_write_unaligned_16 sim_core_write_unaligned_word */
|
||||
|
||||
INLINE_SIM_CORE(void)
|
||||
sim_core_write_unaligned_N(sim_cpu *cpu,
|
||||
|
|
@ -277,3 +289,4 @@ sim_core_write_unaligned_N(sim_cpu *cpu,
|
|||
#undef sim_core_write_aligned_N
|
||||
#undef sim_core_read_unaligned_N
|
||||
#undef sim_core_write_unaligned_N
|
||||
#undef sim_core_trace_N
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
/* This file is part of psim (model of the PowerPC(tm) architecture)
|
||||
|
||||
Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
|
||||
Copyright (C) 1997, Free Software Foundation, Inc.
|
||||
Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Library General Public License
|
||||
|
|
@ -63,12 +62,14 @@ typedef unsigned char unsigned8;
|
|||
typedef unsigned short unsigned16;
|
||||
typedef unsigned long unsigned32;
|
||||
|
||||
#if defined __GNUC__ || defined _WIN32
|
||||
#if defined __GNUC__ || defined _MSC_VER
|
||||
#ifdef __GNUC__
|
||||
|
||||
typedef long long natural64;
|
||||
typedef signed long long signed64;
|
||||
typedef unsigned long long unsigned64;
|
||||
typedef struct { unsigned64 a[2]; } unsigned128;
|
||||
typedef struct { signed64 a[2]; } signed128;
|
||||
|
||||
#define UNSIGNED64(X) (X##ULL)
|
||||
#define SIGNED64(X) (X##LL)
|
||||
|
|
@ -76,20 +77,22 @@ typedef unsigned long long unsigned64;
|
|||
#define UNSIGNED32(X) (X##UL)
|
||||
#define SIGNED32(X) (X##L)
|
||||
|
||||
#else /* _WIN32 */
|
||||
#else /* _MSC_VER */
|
||||
|
||||
typedef __int64 natural64;
|
||||
typedef signed __int64 signed64;
|
||||
typedef unsigned __int64 unsigned64;
|
||||
typeded struct { unsigned64 hi; unsigned64 lo; } unsigned128;
|
||||
typeded struct { signed64 hi; signed64 lo; } signed128;
|
||||
|
||||
#define UNSIGNED64(X) (X##ui64)
|
||||
#define SIGNED64(X) (X##i64)
|
||||
|
||||
#define SIGNED32(X) (X)
|
||||
#define UNSIGNED32(X) (X)
|
||||
#define SIGNED32(X) (X##ui32)
|
||||
#define UNSIGNED32(X) (X##i32)
|
||||
|
||||
#endif /* _WIN32 */
|
||||
#else /* Not GNUC or WIN32 */
|
||||
#endif /* _MSC_VER */
|
||||
#else /* Not GNUC or _MSC_VER */
|
||||
/* Not supported */
|
||||
#endif
|
||||
|
||||
|
|
@ -98,16 +101,19 @@ typedef natural8 natural_1;
|
|||
typedef natural16 natural_2;
|
||||
typedef natural32 natural_4;
|
||||
typedef natural64 natural_8;
|
||||
/* typedef natural64 natural_8; */
|
||||
|
||||
typedef signed8 signed_1;
|
||||
typedef signed16 signed_2;
|
||||
typedef signed32 signed_4;
|
||||
typedef signed64 signed_8;
|
||||
typedef signed128 signed_16;
|
||||
|
||||
typedef unsigned8 unsigned_1;
|
||||
typedef unsigned16 unsigned_2;
|
||||
typedef unsigned32 unsigned_4;
|
||||
typedef unsigned64 unsigned_8;
|
||||
typedef unsigned128 unsigned_16;
|
||||
|
||||
|
||||
/* for general work, the following are defined */
|
||||
|
|
@ -121,7 +127,8 @@ typedef unsigned64 unsigned_8;
|
|||
typedef natural64 natural_word;
|
||||
typedef unsigned64 unsigned_word;
|
||||
typedef signed64 signed_word;
|
||||
#else
|
||||
#endif
|
||||
#if (WITH_TARGET_WORD_BITSIZE == 32)
|
||||
typedef natural32 natural_word;
|
||||
typedef unsigned32 unsigned_word;
|
||||
typedef signed32 signed_word;
|
||||
|
|
|
|||
Loading…
Reference in New Issue