Fri Dec 18 17:09:34 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/ldres.cgs: New testcase. * sim/fr30/stres.cgs: New testcase. * sim/fr30/copop.cgs: New testcase. * sim/fr30/copld.cgs: New testcase. * sim/fr30/copst.cgs: New testcase. * sim/fr30/copsv.cgs: New testcase. * sim/fr30/nop.cgs: New testcase. * sim/fr30/andccr.cgs: New testcase. * sim/fr30/orccr.cgs: New testcase. * sim/fr30/addsp.cgs: New testcase. * sim/fr30/stilm.cgs: New testcase. * sim/fr30/extsb.cgs: New testcase. * sim/fr30/extub.cgs: New testcase. * sim/fr30/extsh.cgs: New testcase. * sim/fr30/extuh.cgs: New testcase. * sim/fr30/enter.cgs: New testcase. * sim/fr30/leave.cgs: New testcase. * sim/fr30/xchb.cgs: New testcase. * sim/fr30/dmovb.cgs: New testcase. * sim/fr30/dmov.cgs: New testcase. * sim/fr30/dmovh.cgs: New testcase.
This commit is contained in:
Dave Brolley
parent
a0542b2798
commit
f45ee50714
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@ -0,0 +1,31 @@
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# fr30 testcase for addsp $s10
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global addsp
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addsp:
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; Test addsp $s10
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mvr_h_gr sp,r7 ; save stack pointer permanently
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mvr_h_gr sp,r8 ; Shadow updated sp
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set_cc 0x0f ; Condition codes are irrelevent
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addsp 508
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test_cc 1 1 1 1
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inci_h_gr 508,r8
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testr_h_gr r8,sp
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set_cc 0x0e ; Condition codes are irrelevent
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addsp 0
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test_cc 1 1 1 0
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testr_h_gr r8,sp
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set_cc 0x0d ; Condition codes are irrelevent
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addsp -512
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test_cc 1 1 0 1
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inci_h_gr -512,r8
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testr_h_gr r8,sp
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pass
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@ -0,0 +1,51 @@
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# fr30 testcase for andccr $u8
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global andccr
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andccr:
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set_cc 0x00
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set_i 0
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set_s_system
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andccr 0xff
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test_cc 0 0 0 0
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test_i 0
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test_s_system
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set_cc 0x0f
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set_i 1
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set_s_user
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andccr 0xff
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test_cc 1 1 1 1
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test_i 1
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test_s_user
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set_cc 0x0f
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set_i 1
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set_s_user
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andccr 0xaa
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test_cc 1 0 1 0
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test_i 0
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test_s_user
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set_cc 0x0f
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set_i 1
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set_s_user
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andccr 0xc0
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test_cc 0 0 0 0
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test_i 0
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test_s_system
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set_cc 0x0f
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set_i 1
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set_s_user
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andccr 0x3f ; no effect
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test_cc 1 1 1 1
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test_i 1
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test_s_user
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pass
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@ -0,0 +1,21 @@
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# fr30 testcase for copld $u4,$cc,$Rj,CRi
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global copld
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copld:
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; Test copld copld $u4,$cc,$Rj,CRi
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; The current implementation is a noop
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set_cc 0x0f ; Condition codes are irrelevent
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copld 0,0,r0,cr15
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test_cc 1 1 1 1
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set_cc 0x0e ; Condition codes are irrelevent
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copld 15,255,r15,cr0
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test_cc 1 1 1 0
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pass
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@ -0,0 +1,21 @@
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# fr30 testcase for copop $u4,$cc,$CRj,CRi
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global copop
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copop:
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; Test copop copop $u4,$cc,$CRj,CRi
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; The current implementation is a noop
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set_cc 0x0f ; Condition codes are irrelevent
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copop 0,0,cr0,cr15
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test_cc 1 1 1 1
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set_cc 0x0e ; Condition codes are irrelevent
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copop 15,255,cr0,cr15
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test_cc 1 1 1 0
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pass
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@ -0,0 +1,21 @@
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# fr30 testcase for copst $u4,$cc,$CRj,Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global copst
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copst:
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; Test copst copst $u4,$cc,$CRj,Ri
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; The current implementation is a noop
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set_cc 0x0f ; Condition codes are irrelevent
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copst 0,0,cr0,r15
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test_cc 1 1 1 1
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set_cc 0x0e ; Condition codes are irrelevent
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copst 15,255,cr15,r0
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test_cc 1 1 1 0
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pass
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@ -0,0 +1,21 @@
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# fr30 testcase for copsv $u4,$cc,$CRj,Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global copsv
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copsv:
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; Test copsv copsv $u4,$cc,$CRj,Ri
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; The current implementation is a noop
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set_cc 0x0f ; Condition codes are irrelevent
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copsv 0,0,cr0,r15
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test_cc 1 1 1 1
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set_cc 0x0e ; Condition codes are irrelevent
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copsv 15,255,cr15,r0
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test_cc 1 1 1 0
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pass
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@ -0,0 +1,73 @@
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# fr30 testcase for dmov
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global dmov
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dmov:
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; Test dmov @$dir10,$R13
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mvi_h_gr 0xdeadbeef,r1
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mvi_h_gr 0x200,r2
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mvr_h_mem r1,r2
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set_cc 0x0f ; Condition codes shouldn't change
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dmov @0x200,r13
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test_cc 1 1 1 1
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test_h_gr 0xdeadbeef,r13
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; Test dmov $R13,@$dir10
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mvi_h_gr 0xbeefdead,r13
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set_cc 0x0e ; Condition codes shouldn't change
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dmov r13,@0x200
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test_cc 1 1 1 0
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test_h_mem 0xbeefdead,r2
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; Test dmov @$dir10,@R13+
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mvi_h_gr 0x1fc,r13
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set_cc 0x0d ; Condition codes shouldn't change
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dmov @0x200,@r13+
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test_cc 1 1 0 1
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mvi_h_gr 0x1fc,r2
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test_h_mem 0xbeefdead,r2
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inci_h_gr 4,r2
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test_h_mem 0xbeefdead,r2
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test_h_gr 0x200,r13
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; Test dmov @$R13+,@$dir10
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mvi_h_gr 0x1fc,r13
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mvi_h_mem 0xdeadbeef,r13
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set_cc 0x0c ; Condition codes shouldn't change
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dmov @r13+,@0x200
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test_cc 1 1 0 0
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mvi_h_gr 0x1fc,r2
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test_h_mem 0xdeadbeef,r2
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inci_h_gr 4,r2
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test_h_mem 0xdeadbeef,r2
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test_h_gr 0x200,r13
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; Test dmov @$dir10,@-R15
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mvi_h_gr 0x200,r15
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mvi_h_mem 0xdeadbeef,r15
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set_cc 0x0b ; Condition codes shouldn't change
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dmov @0x200,@-r15
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test_cc 1 0 1 1
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mvi_h_gr 0x1fc,r2
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test_h_mem 0xdeadbeef,r2
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inci_h_gr 4,r2
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test_h_mem 0xdeadbeef,r2
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test_h_gr 0x1fc,r15
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; Test dmov @$R15+,@$dir10
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mvi_h_gr 0x1fc,r15
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mvi_h_mem 0xbeefdead,r15
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set_cc 0x0a ; Condition codes shouldn't change
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dmov @r15+,@0x200
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test_cc 1 0 1 0
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mvi_h_gr 0x1fc,r2
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test_h_mem 0xbeefdead,r2
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inci_h_gr 4,r2
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test_h_mem 0xbeefdead,r2
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test_h_gr 0x200,r15
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pass
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# fr30 testcase for dmovb
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global dmovb
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dmovb:
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; Test dmovb @$dir8,$R13
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mvi_h_gr 0xdeadbeef,r1
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mvi_h_gr 0x80,r2
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mvr_h_mem r1,r2
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set_cc 0x0f ; Condition codes shouldn't change
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dmovb @0x80,r13
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test_cc 1 1 1 1
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test_h_gr 0xffffffde,r13
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; Test dmovb $R13,@$dir8
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mvi_h_gr 0xbeefdead,r13
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set_cc 0x0e ; Condition codes shouldn't change
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dmovb r13,@0x80
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test_cc 1 1 1 0
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test_h_mem 0xadadbeef,r2
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; Test dmovb @$dir8,@R13+
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mvi_h_gr 0x7c,r13
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mvi_h_mem 0xdeadbeef,r13
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set_cc 0x0d ; Condition codes shouldn't change
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dmovb @0x7f,@r13+
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test_cc 1 1 0 1
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mvi_h_gr 0x7c,r2
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test_h_mem 0xefadbeef,r2
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test_h_gr 0x7d,r13
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; Test dmovb @$R13+,@$dir8
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mvi_h_gr 0x7c,r13
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mvi_h_mem 0xbeefdead,r13
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set_cc 0x0c ; Condition codes shouldn't change
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dmovb @r13+,@0x7f
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test_cc 1 1 0 0
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mvi_h_gr 0x7c,r2
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test_h_mem 0xbeefdebe,r2
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test_h_gr 0x7d,r13
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pass
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# fr30 testcase for dmovh
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global dmovh
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dmovh:
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; Test dmovh @$dir9,$R13
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mvi_h_gr 0xdeadbeef,r1
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mvi_h_gr 0x100,r2
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mvr_h_mem r1,r2
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set_cc 0x0f ; Condition codes shouldn't change
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dmovh @0x100,r13
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test_cc 1 1 1 1
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test_h_gr 0xffffdead,r13
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; Test dmovh $R13,@$dir9
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mvi_h_gr 0xdeadbeef,r13
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set_cc 0x0e ; Condition codes shouldn't change
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dmovh r13,@0x100
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test_cc 1 1 1 0
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test_h_mem 0xbeefbeef,r2
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; Test dmovh @$dir9,@R13+
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mvi_h_gr 0x1fc,r13
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mvi_h_mem 0xdeadbeef,r13
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set_cc 0x0d ; Condition codes shouldn't change
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dmovh @0x1fe,@r13+
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test_cc 1 1 0 1
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mvi_h_gr 0x1fc,r2
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test_h_mem 0xbeefbeef,r2
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test_h_gr 0x1fe,r13
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; Test dmovh @$R13+,@$dir9
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mvi_h_gr 0x1fc,r13
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mvi_h_mem 0xbeefdead,r13
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set_cc 0x0c ; Condition codes shouldn't change
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dmovh @r13+,@0x1fe
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test_cc 1 1 0 0
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mvi_h_gr 0x1fc,r2
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test_h_mem 0xbeefbeef,r2
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test_h_gr 0x1fe,r13
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pass
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@ -0,0 +1,36 @@
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# fr30 testcase for extsb $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global extsb
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extsb:
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; Test extsb $Ri
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mvi_h_gr 0,r7
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set_cc 0x0f ; Condition codes are irrelevent
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extsb r7
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test_cc 1 1 1 1
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test_h_gr 0,r7
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mvi_h_gr 0x7f,r7
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set_cc 0x0e ; Condition codes are irrelevent
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extsb r7
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test_cc 1 1 1 0
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test_h_gr 0x7f,r7
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mvi_h_gr 0x80,r7
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set_cc 0x0d ; Condition codes are irrelevent
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extsb r7
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test_cc 1 1 0 1
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test_h_gr 0xffffff80,r7
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mvi_h_gr 0xffffff7f,r7
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set_cc 0x0c ; Condition codes are irrelevent
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extsb r7
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test_cc 1 1 0 0
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test_h_gr 0x7f,r7
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pass
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# fr30 testcase for extsh $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global extsh
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extsh:
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; Test extsh $Ri
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mvi_h_gr 0,r7
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set_cc 0x0f ; Condition codes are irrelevent
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extsh r7
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test_cc 1 1 1 1
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test_h_gr 0,r7
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mvi_h_gr 0x7f,r7
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set_cc 0x0e ; Condition codes are irrelevent
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extsh r7
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test_cc 1 1 1 0
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test_h_gr 0x7f,r7
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mvi_h_gr 0x80,r7
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set_cc 0x0d ; Condition codes are irrelevent
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extsh r7
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test_cc 1 1 0 1
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test_h_gr 0x80,r7
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mvi_h_gr 0x7fff,r7
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set_cc 0x0c ; Condition codes are irrelevent
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extsh r7
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test_cc 1 1 0 0
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test_h_gr 0x7fff,r7
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mvi_h_gr 0x8000,r7
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set_cc 0x0b ; Condition codes are irrelevent
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extsh r7
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test_cc 1 0 1 1
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test_h_gr 0xffff8000,r7
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mvi_h_gr 0xffff7fff,r7
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set_cc 0x0a ; Condition codes are irrelevent
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extsh r7
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test_cc 1 0 1 0
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test_h_gr 0x7fff,r7
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pass
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# fr30 testcase for extub $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global extub
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extub:
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; Test extub $Ri
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mvi_h_gr 0,r7
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set_cc 0x0f ; Condition codes are irrelevent
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extub r7
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test_cc 1 1 1 1
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test_h_gr 0,r7
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mvi_h_gr 0x7f,r7
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set_cc 0x0e ; Condition codes are irrelevent
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extub r7
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test_cc 1 1 1 0
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test_h_gr 0x7f,r7
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mvi_h_gr 0x80,r7
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set_cc 0x0d ; Condition codes are irrelevent
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extub r7
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test_cc 1 1 0 1
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test_h_gr 0x80,r7
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mvi_h_gr 0xffffff7f,r7
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set_cc 0x0c ; Condition codes are irrelevent
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extub r7
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test_cc 1 1 0 0
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test_h_gr 0x7f,r7
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mvi_h_gr 0xffffff80,r7
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set_cc 0x0b ; Condition codes are irrelevent
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extub r7
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test_cc 1 0 1 1
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test_h_gr 0x80,r7
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pass
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@ -0,0 +1,54 @@
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# fr30 testcase for extuh $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global extuh
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extuh:
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; Test extuh $Ri
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mvi_h_gr 0,r7
|
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set_cc 0x0f ; Condition codes are irrelevent
|
||||
extuh r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
mvi_h_gr 0x7f,r7
|
||||
set_cc 0x0e ; Condition codes are irrelevent
|
||||
extuh r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0x7f,r7
|
||||
|
||||
mvi_h_gr 0x80,r7
|
||||
set_cc 0x0d ; Condition codes are irrelevent
|
||||
extuh r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x80,r7
|
||||
|
||||
mvi_h_gr 0x7fff,r7
|
||||
set_cc 0x0e ; Condition codes are irrelevent
|
||||
extuh r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0x7fff,r7
|
||||
|
||||
mvi_h_gr 0x8000,r7
|
||||
set_cc 0x0d ; Condition codes are irrelevent
|
||||
extuh r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x8000,r7
|
||||
|
||||
mvi_h_gr 0xffff7fff,r7
|
||||
set_cc 0x0c ; Condition codes are irrelevent
|
||||
extuh r7
|
||||
test_cc 1 1 0 0
|
||||
test_h_gr 0x7fff,r7
|
||||
|
||||
mvi_h_gr 0xffff8000,r7
|
||||
set_cc 0x0b ; Condition codes are irrelevent
|
||||
extuh r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x8000,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
# fr30 testcase for ldres $@Ri+,$u4
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global ldres
|
||||
ldres:
|
||||
; Test ldres $@Ri+,$u4
|
||||
; The current implementation simply increments Ri
|
||||
mvi_h_gr 0x1000,r7
|
||||
set_cc 0x0f ; Condition codes are irrelevent
|
||||
ldres @r7+,0
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0x1004,r7
|
||||
|
||||
mvi_h_gr 0x1000,r7
|
||||
set_cc 0x0f ; Condition codes are irrelevent
|
||||
ldres @r7+,0xf
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0x1004,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
# fr30 testcase for leave
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global leave
|
||||
leave:
|
||||
; Test leave $u10
|
||||
mvr_h_gr sp,r7 ; save Stack pointer
|
||||
mvr_h_gr sp,r14
|
||||
inci_h_gr -4,r14
|
||||
mvi_h_mem 0xdeadbeef,r14
|
||||
mvi_h_gr 0xbeefdead,r15
|
||||
set_cc 0x0f ; Condition codes are irrelevent
|
||||
leave
|
||||
test_cc 1 1 1 1
|
||||
testr_h_gr sp,r7
|
||||
test_h_gr 0xdeadbeef,r14
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
# fr30 testcase for nop
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global nop
|
||||
nop:
|
||||
; Test nop
|
||||
set_cc 0x0f ; Condition codes are irrelevent
|
||||
nop
|
||||
test_cc 1 1 1 1
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
# fr30 testcase for orccr $u8
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global orccr
|
||||
orccr:
|
||||
orccr 0xff
|
||||
test_cc 1 1 1 1
|
||||
test_i 1
|
||||
test_s_user
|
||||
|
||||
set_cc 0x0f
|
||||
orccr 0x00
|
||||
test_cc 1 1 1 1
|
||||
test_i 1
|
||||
test_s_user
|
||||
|
||||
set_cc 0x00
|
||||
set_i 0
|
||||
set_s_system
|
||||
orccr 0xaa
|
||||
test_cc 1 0 1 0
|
||||
test_i 0
|
||||
test_s_user
|
||||
|
||||
set_cc 0x00
|
||||
set_i 0
|
||||
set_s_system
|
||||
orccr 0xc0
|
||||
test_cc 0 0 0 0
|
||||
test_i 0
|
||||
test_s_system
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
# fr30 testcase for stilm $i8
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global stilm
|
||||
stilm:
|
||||
stilm 0
|
||||
test_ilm 0
|
||||
|
||||
stilm 0xe0
|
||||
test_ilm 0
|
||||
|
||||
stilm 1
|
||||
test_ilm 1
|
||||
|
||||
stilm 15
|
||||
test_ilm 15
|
||||
|
||||
stilm 16
|
||||
test_ilm 16
|
||||
|
||||
stilm 0
|
||||
test_ilm 16
|
||||
|
||||
stilm 1
|
||||
test_ilm 17
|
||||
|
||||
stilm 18
|
||||
test_ilm 18
|
||||
|
||||
stilm 31
|
||||
test_ilm 31
|
||||
|
||||
stilm 0xff
|
||||
test_ilm 31
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
# fr30 testcase for stres $@Ri+,$u4
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global stres
|
||||
stres:
|
||||
; Test stres $@Ri+,$u4
|
||||
; The current implementation simply increments Ri
|
||||
mvi_h_gr 0x1000,r7
|
||||
set_cc 0x0f ; Condition codes are irrelevent
|
||||
stres 0,@r7+
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0x1004,r7
|
||||
|
||||
mvi_h_gr 0x1000,r7
|
||||
set_cc 0x0f ; Condition codes are irrelevent
|
||||
stres 0xf,@r7+
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0x1004,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# fr30 testcase for xchb @$Rj,Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global xchb
|
||||
xchb:
|
||||
; Test xchb @$Rj,Ri
|
||||
mvi_h_mem 0xdeadbeef,sp
|
||||
mvi_h_gr 0xbeefdead,r0
|
||||
set_cc 0x0f ; Condition codes are irrelevent
|
||||
xchb @sp,r0
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0xde,r0
|
||||
test_h_mem 0xadadbeef,sp
|
||||
|
||||
pass
|
||||
Loading…
Reference in New Issue