[AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD and FCMLA extensions. include/ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro. (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM. opcodes/ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... (aarch64_feature_compnum): ...this. (SIMD_V8_3): Replace with... (COMPNUM): ...this. (CNUM_INSN): New macro. (aarch64_opcode_table): Use it for the complex number instructions. gas/ * doc/c-aarch64.texi: Add a "compnum" entry. * config/tc-aarch64.c (aarch64_features): Likewise, * testsuite/gas/aarch64/advsimd-compnum.s: New test. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
This commit is contained in:
Richard Sandiford
parent
6b4bf3bc35
commit
f482d30447
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@ -1,3 +1,10 @@
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Add a "compnum" entry.
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* config/tc-aarch64.c (aarch64_features): Likewise,
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* testsuite/gas/aarch64/advsimd-compnum.s: New test.
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* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
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2017-02-24 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/opcode.s: Add alternative TEST forms.
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@ -8438,6 +8438,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_FP
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| AARCH64_FEATURE_SIMD, 0)},
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{"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_F16
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| AARCH64_FEATURE_SIMD, 0)},
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{"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
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AARCH64_ARCH_NONE},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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@ -131,6 +131,9 @@ automatically cause those extensions to be disabled.
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@multitable @columnfractions .12 .17 .17 .54
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@headitem Extension @tab Minimum Architecture @tab Enabled by default
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@tab Description
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@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
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@tab Enable the complex number SIMD extensions. This implies
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@code{fp16} and @code{simd}.
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@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable CRC instructions.
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@item @code{crypto} @tab ARMv8-A @tab No
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@ -0,0 +1,40 @@
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#as: -march=armv8.2-a+compnum -I$srcdir/$subdir
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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[^:]+: 6ec3c441 fcmla v1\.2d, v2\.2d, v3\.2d, #0
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[^:]+: 6ec3cc41 fcmla v1\.2d, v2\.2d, v3\.2d, #90
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[^:]+: 6ec3d441 fcmla v1\.2d, v2\.2d, v3\.2d, #180
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[^:]+: 6ec3dc41 fcmla v1\.2d, v2\.2d, v3\.2d, #270
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[^:]+: 2e83cc41 fcmla v1\.2s, v2\.2s, v3\.2s, #90
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[^:]+: 6e83cc41 fcmla v1\.4s, v2\.4s, v3\.4s, #90
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[^:]+: 2e43cc41 fcmla v1\.4h, v2\.4h, v3\.4h, #90
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[^:]+: 6e43cc41 fcmla v1\.8h, v2\.8h, v3\.8h, #90
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[^:]+: 6f831041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #0
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[^:]+: 6f833041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #90
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[^:]+: 6f835041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #180
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[^:]+: 6f837041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #270
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[^:]+: 6f833841 fcmla v1\.4s, v2\.4s, v3\.s\[1\], #90
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[^:]+: 2f433041 fcmla v1\.4h, v2\.4h, v3\.h\[0\], #90
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[^:]+: 2f633041 fcmla v1\.4h, v2\.4h, v3\.h\[1\], #90
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[^:]+: 6f433041 fcmla v1\.8h, v2\.8h, v3\.h\[0\], #90
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[^:]+: 6f633041 fcmla v1\.8h, v2\.8h, v3\.h\[1\], #90
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[^:]+: 6f433841 fcmla v1\.8h, v2\.8h, v3\.h\[2\], #90
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[^:]+: 6f633841 fcmla v1\.8h, v2\.8h, v3\.h\[3\], #90
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[^:]+: 6ec3e441 fcadd v1\.2d, v2\.2d, v3\.2d, #90
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[^:]+: 6ec3f441 fcadd v1\.2d, v2\.2d, v3\.2d, #270
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[^:]+: 2e83e441 fcadd v1\.2s, v2\.2s, v3\.2s, #90
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[^:]+: 6e83e441 fcadd v1\.4s, v2\.4s, v3\.4s, #90
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[^:]+: 2e43e441 fcadd v1\.4h, v2\.4h, v3\.4h, #90
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[^:]+: 6e43e441 fcadd v1\.8h, v2\.8h, v3\.8h, #90
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[^:]+: 4e63d441 fadd v1\.2d, v2\.2d, v3\.2d
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[^:]+: 0e23d441 fadd v1\.2s, v2\.2s, v3\.2s
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[^:]+: 4e23d441 fadd v1\.4s, v2\.4s, v3\.4s
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[^:]+: 0e401400 fadd v0\.4h, v0\.4h, v0\.4h
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[^:]+: 0e431441 fadd v1\.4h, v2\.4h, v3\.4h
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[^:]+: 4e401400 fadd v0\.8h, v0\.8h, v0\.8h
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[^:]+: 4e431441 fadd v1\.8h, v2\.8h, v3\.8h
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@ -0,0 +1,9 @@
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.include "advsimd-armv8_3.s"
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fadd v1.2d, v2.2d, v3.2d
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fadd v1.2s, v2.2s, v3.2s
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fadd v1.4s, v2.4s, v3.4s
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fadd v0.4h, v0.4h, v0.4h
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fadd v1.4h, v2.4h, v3.4h
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fadd v0.8h, v0.8h, v0.8h
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fadd v1.8h, v2.8h, v3.8h
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@ -1,3 +1,8 @@
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
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(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
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2017-02-22 Andrew Waterman <andrew@sifive.com>
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* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
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@ -54,6 +54,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
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#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
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#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
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#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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@ -72,7 +73,8 @@ typedef uint32_t aarch64_insn;
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| AARCH64_FEATURE_RAS)
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#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
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AARCH64_FEATURE_V8_3 \
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| AARCH64_FEATURE_RCPC)
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| AARCH64_FEATURE_RCPC \
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| AARCH64_FEATURE_COMPNUM)
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#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
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#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
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@ -1,3 +1,12 @@
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
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(aarch64_feature_compnum): ...this.
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(SIMD_V8_3): Replace with...
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(COMPNUM): ...this.
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(CNUM_INSN): New macro.
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(aarch64_opcode_table): Use it for the complex number instructions.
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2017-02-24 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
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@ -1938,8 +1938,8 @@ static const aarch64_feature_set aarch64_feature_v8_3 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0);
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static const aarch64_feature_set aarch64_feature_fp_v8_3 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0);
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static const aarch64_feature_set aarch64_feature_simd_v8_3 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_SIMD, 0);
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static const aarch64_feature_set aarch64_feature_compnum =
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AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0);
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static const aarch64_feature_set aarch64_feature_rcpc =
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AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0);
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@ -1959,7 +1959,7 @@ static const aarch64_feature_set aarch64_feature_rcpc =
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#define SVE &aarch64_feature_sve
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#define ARMV8_3 &aarch64_feature_v8_3
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#define FP_V8_3 &aarch64_feature_fp_v8_3
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#define SIMD_V8_3 &aarch64_feature_simd_v8_3
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#define COMPNUM &aarch64_feature_compnum
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#define RCPC &aarch64_feature_rcpc
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#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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@ -1989,6 +1989,8 @@ static const aarch64_feature_set aarch64_feature_rcpc =
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FLAGS | F_STRICT, TIED, NULL }
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#define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL }
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#define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, NULL }
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#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL }
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@ -2130,7 +2132,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
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SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
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RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
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RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
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{"fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, SIMD_V8_3, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ, 0, NULL},
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CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ),
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/* AdvSIMD EXT. */
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SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ),
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/* AdvSIMD modified immediate. */
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@ -2374,8 +2376,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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/* AdvSIMD three same extension. */
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RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
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RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
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{"fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL},
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{"fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL},
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CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ),
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CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ),
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/* AdvSIMD shift by immediate. */
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SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
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SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
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