[PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise.
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Andre Vieira
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56858bea62
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f49bb598d9
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@ -1,3 +1,13 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (thumb32_opcodes): Add new instructions.
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(enum mve_instructions): Likewise.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_size): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -245,6 +245,14 @@ enum mve_instructions
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MVE_VMINV,
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MVE_VMINAV,
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MVE_VMLA,
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MVE_VMUL_FP_T1,
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MVE_VMUL_FP_T2,
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MVE_VMUL_VEC_T1,
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MVE_VMUL_VEC_T2,
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MVE_VMULH,
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MVE_VRMULH,
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MVE_VNEG_FP,
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MVE_VNEG_VEC,
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MVE_NONE
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};
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@ -2795,6 +2803,42 @@ static const struct mopcode32 mve_opcodes[] =
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0xfeb00a40, 0xffbf0fd0,
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"vmovx.f16\t%22,12-15F, %5,0-3F"},
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/* Vector VMUL floating-point T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMUL_FP_T1,
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0xff000d50, 0xffa11f51,
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"vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VMUL floating-point T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMUL_FP_T2,
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0xee310e60, 0xefb11f70,
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"vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VMUL T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMUL_VEC_T1,
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0xef000950, 0xff811f51,
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"vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VMUL T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMUL_VEC_T2,
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0xee011e60, 0xff811f70,
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"vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VMULH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMULH,
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0xee010e01, 0xef811f51,
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"vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VRMULH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRMULH,
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0xee011e01, 0xef811f51,
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"vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VMULL integer. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMULL_INT,
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@ -2819,6 +2863,18 @@ static const struct mopcode32 mve_opcodes[] =
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0xffb005c0, 0xffbf1fd1,
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"vmvn%v\t%13-15,22Q, %1-3,5Q"},
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/* Vector VNEG floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VNEG_FP,
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0xffb107c0, 0xffb31fd1,
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"vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VNEG. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VNEG_VEC,
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0xffb103c0, 0xffb31fd1,
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"vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VORN, vector bitwise or not. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VORN,
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@ -5183,6 +5239,9 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VMUL_VEC_T2:
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case MVE_VMULH:
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case MVE_VRMULH:
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case MVE_VMLA:
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case MVE_VMAX:
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case MVE_VMIN:
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@ -5480,6 +5539,7 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VMUL_VEC_T1:
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case MVE_VABD_VEC:
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case MVE_VADD_VEC_T1:
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case MVE_VSUB_VEC_T1:
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@ -5658,6 +5718,7 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VNEG_FP:
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case MVE_VABS_FP:
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case MVE_VCVT_BETWEEN_FP_INT:
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case MVE_VCVT_FROM_FP_TO_INT:
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@ -5820,6 +5881,7 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VNEG_VEC:
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case MVE_VCLS:
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case MVE_VCLZ:
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if (arm_decode_field (given, 18, 19) == 3)
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@ -5889,6 +5951,8 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VMUL_FP_T2:
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case MVE_VMUL_VEC_T2:
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case MVE_VMLA:
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case MVE_VBRSR:
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case MVE_VADD_FP_T2:
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@ -7017,6 +7081,13 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VMINAV:
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case MVE_VMLA:
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case MVE_VMLAS:
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case MVE_VMUL_VEC_T1:
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case MVE_VMUL_VEC_T2:
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case MVE_VMULH:
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case MVE_VRMULH:
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case MVE_VMULL_INT:
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case MVE_VNEG_FP:
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case MVE_VNEG_VEC:
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case MVE_VPT_VEC_T1:
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case MVE_VPT_VEC_T2:
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case MVE_VPT_VEC_T3:
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@ -7080,6 +7151,8 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VMINNMA_FP:
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case MVE_VMINNMV_FP:
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case MVE_VMINNMAV_FP:
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case MVE_VMUL_FP_T1:
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case MVE_VMUL_FP_T2:
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case MVE_VPT_FP_T1:
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case MVE_VPT_FP_T2:
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if (size == 0)
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