gas: blackfin: reject invalid 16bit acc add insns
The 16bit acc add insn cannot assign the two results to the same dreg, so make sure gas rejects attempts to use this insn variant. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -1,3 +1,8 @@
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2011-03-28 Mike Frysinger <vapier@gentoo.org>
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* config/bfin-parse.y (16bit acc add): Return yyerror when dest
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reg $1 is the same as dest reg $7.
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2011-03-28 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (handle_quad): New.
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@ -886,6 +886,9 @@ asm_1:
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| REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
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REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
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{
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if (REG_SAME ($1, $7))
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return yyerror ("Illegal dest register combination");
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if (IS_DREG ($1) && IS_DREG ($7))
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{
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notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
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@ -1,3 +1,10 @@
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2011-03-28 Mike Frysinger <vapier@gentoo.org>
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* gas/bfin/expected_errors.s: Add invalid 16bit acc add insn tests.
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* gas/bfin/expected_errors.l: Add new error messages.
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* testsuite/gas/bfin/video2.s: Drop invalid 16bit acc add insn.
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* testsuite/gas/bfin/video2.d: Updated disassembly output.
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2011-03-28 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/ilp32/inval.s: Remove .quad.
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@ -100,3 +100,4 @@
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.*:126: Error: Resource conflict in dest reg.
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.*:127: Error: Differing source registers.
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.*:129: Error: Register mismatch.
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.*:131: Error: Illegal dest register combination. Input text was A0.H.
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@ -127,3 +127,5 @@
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R7 = R3 +|- R4, R1 = R1 -|+ R2;
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R0 = R3 + R4, R1 = R5 - R6;
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R7 = A1.L + A1.H, R7 = A0.L + A0.H;
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@ -50,7 +50,6 @@ Disassembly of section .text:
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[ 0-9a-f]+: 37 c4 10 0a R5 = BYTEOP3P \(R3:2, R1:0\) \(HI\);
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[ 0-9a-f]+: 17 c4 10 2c R6 = BYTEOP3P \(R3:2, R1:0\) \(LO, R\);
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[ 0-9a-f]+: 37 c4 10 2e R7 = BYTEOP3P \(R3:2, R1:0\) \(HI, R\);
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[ 0-9a-f]+: 0c c4 00 40 R0 = A1.L \+ A1.H, R0 = A0.L \+ A0.H;
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[ 0-9a-f]+: 0c c4 00 42 R0 = A1.L \+ A1.H, R1 = A0.L \+ A0.H;
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[ 0-9a-f]+: 0c c4 80 46 R2 = A1.L \+ A1.H, R3 = A0.L \+ A0.H;
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[ 0-9a-f]+: 0c c4 00 4b R4 = A1.L \+ A1.H, R5 = A0.L \+ A0.H;
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@ -68,7 +68,6 @@ r7 = byteop3p (r3:2, r1:0) (hi, r) ;
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//Dreg = A1.L + A1.H, Dreg = A0.L + A0.H ; /* (b) */
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R0 = A1.L + A1.H, R0= A0.L + A0.H ;
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R0 = A1.L + A1.H, R1= A0.L + A0.H ;
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R2 = A1.L + A1.H, R3= A0.L + A0.H ;
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R4 = A1.L + A1.H, R5= A0.L + A0.H ;
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