2002-06-02 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com> * mips.igen (mdmx): New (pseudo-)model. * mdmx.c, mdmx.igen: New files. * Makefile.in (SIM_OBJS): Add mdmx.o. * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): New typedefs. (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) (qh_fmtsel): New macros. (_sim_cpu): New member "acc". (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
This commit is contained in:
Chris Demetriou
parent
4a67a09883
commit
f4f1b9f102
@ -1,3 +1,29 @@
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2002-06-02 Chris Demetriou <cgd@broadcom.com>
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Ed Satterthwaite <ehs@broadcom.com>
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* mips.igen (mdmx): New (pseudo-)model.
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* mdmx.c, mdmx.igen: New files.
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* Makefile.in (SIM_OBJS): Add mdmx.o.
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* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
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New typedefs.
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(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
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(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
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(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
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(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
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(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
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(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
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(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
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(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
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(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
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(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
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(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
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(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
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(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
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(qh_fmtsel): New macros.
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(_sim_cpu): New member "acc".
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(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
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(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
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2002-05-01 Chris Demetriou <cgd@broadcom.com>
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* interp.c: Use 'deprecated' rather than 'depreciated.'
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@ -43,6 +43,7 @@ SIM_OBJS = \
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$(MIPS_EXTRA_OBJS) \
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cp1.o \
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interp.o \
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mdmx.o \
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sim-main.o \
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sim-hload.o \
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sim-engine.o \
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@ -71,6 +72,7 @@ SIM_RUN_OBJS = nrun.o
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interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
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cp1.o: $(srcdir)/cp1.c config.h sim-main.h
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mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
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../igen/igen:
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cd ../igen && $(MAKE)
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1449
sim/mips/mdmx.c
Normal file
1449
sim/mips/mdmx.c
Normal file
File diff suppressed because it is too large
Load Diff
550
sim/mips/mdmx.igen
Normal file
550
sim/mips/mdmx.igen
Normal file
@ -0,0 +1,550 @@
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// -*- C -*-
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// Simulator definition for the MIPS MDMX ASE.
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// Copyright (C) 2002 Free Software Foundation, Inc.
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// Contributed by Broadcom Corporation (SiByte).
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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// Reference: MIPS64 Architecture Volume IV-b:
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// The MDMX Application-Specific Extension
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// Notes on "format selectors" (FMTSEL):
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//
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// A selector with final bit 0 indicates OB format.
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// A selector with final bits 01 indicates QH format.
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// A selector with final bits 11 has UNPREDICTABLE result per the spec.
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//
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// Similarly, for the single-bit fields which differentiate between
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// formats (FMTOP), 0 is OB format and 1 is QH format.
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// Helper:
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//
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// Check whether MDMX is usable, and if not signal an appropriate exception.
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//
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:function:::void:check_mdmx:instruction_word insn
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*mdmx:
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{
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if (! COP_Usable (1))
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SignalExceptionCoProcessorUnusable (1);
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if ((SR & (status_MX|status_FR)) != (status_MX|status_FR))
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SignalExceptionMDMX ();
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check_u64 (SD_, insn);
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}
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// Helper:
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//
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// Check whether a given MDMX format selector indicates a valid and usable
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// format, and if not signal an appropriate exception.
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//
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:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
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*mdmx:
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{
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switch (fmtsel & 0x03)
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{
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case 0x00: /* ob */
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case 0x02:
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case 0x01: /* qh */
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return 1;
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case 0x03: /* UNPREDICTABLE */
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SignalException (ReservedInstruction, insn);
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return 0;
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}
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return 0;
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}
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// Helper:
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//
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// Check whether a given MDMX format bit indicates a valid and usable
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// format, and if not signal an appropriate exception.
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//
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:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
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*mdmx:
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{
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switch (fmtop & 0x01)
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{
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case 0x00: /* ob */
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case 0x01: /* qh */
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return 1;
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}
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return 0;
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}
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:%s::::FMTSEL:int fmtsel
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*mdmx:
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{
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if ((fmtsel & 0x1) == 0)
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return "ob";
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else if ((fmtsel & 0x3) == 1)
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return "qh";
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else
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return "?";
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}
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:%s::::FMTOP:int fmtop
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*mdmx:
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{
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switch (fmtop)
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{
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case 0: return "ob";
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case 1: return "qh";
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default: return "?";
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}
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}
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:%s::::SHOP:int shop
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*mdmx:
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{
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if ((shop & 0x11) == 0x00)
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switch ((shop >> 1) & 0x07)
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{
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case 3: return "upsl.ob";
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case 4: return "pach.ob";
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case 6: return "mixh.ob";
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case 7: return "mixl.ob";
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default: return "?";
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}
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else if ((shop & 0x03) == 0x01)
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switch ((shop >> 2) & 0x07)
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{
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case 0: return "mixh.qh";
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case 1: return "mixl.qh";
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case 2: return "pach.qh";
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case 4: return "bfla.qh";
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case 6: return "repa.qh";
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case 7: return "repb.qh";
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default: return "?";
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}
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else
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return "?";
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001011:MDMX:64::ADD.fmt
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"add.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Add(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110111:MDMX:64::ADDA.fmt
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"adda.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_AddA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,1,0000,110111:MDMX:64::ADDL.fmt
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"addl.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_AddL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,00,3.IMM,5.VT,5.VS,5.VD,0110,1.FMTOP,0:MDMX:64::ALNI.fmt
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"alni.%s<FMTOP> v<VD>, v<VS>, v<VT>, <IMM>"
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*mdmx:
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{
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unsigned64 result;
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int s;
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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s = (IMM << 3);
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result = ValueFPR(VS,fmt_mdmx) << s;
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if (s != 0) // x86 gcc treats >> 64 as >> 0
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result |= ValueFPR(VT,fmt_mdmx) >> (64 - s);
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StoreFPR(VD,fmt_mdmx,result);
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}
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011110,5.RS,5.VT,5.VS,5.VD,0110,1.FMTOP,1:MDMX:64::ALNV.fmt
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"alnv.%s<FMTOP> v<VD>, v<VS>, v<VT>, r<RS>"
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*mdmx:
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{
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unsigned64 result;
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int s;
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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s = ((GPR[RS] & 0x7) << 3);
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result = ValueFPR(VS,fmt_mdmx) << s;
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if (s != 0) // x86 gcc treats >> 64 as >> 0
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result |= ValueFPR(VT,fmt_mdmx) >> (64 - s);
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StoreFPR(VD,fmt_mdmx,result);
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001100:MDMX:64::AND.fmt
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"and.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_And(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,00000,000001:MDMX:64::C.EQ.fmt
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"c.eq.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_EQ,VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,00000,000101:MDMX:64::C.LE.fmt
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"c.le.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT|MX_C_EQ,VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,00000,000100:MDMX:64::C.LT.fmt
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"c.lt.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT,VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000111:MDMX:64::MAX.fmt
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"max.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Max(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000110:MDMX:64::MIN.fmt
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"min.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Min(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,3.SEL,01,5.VT,5.VS,5.VD,000000:MDMX:64::MSGN.QH
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"msgn.qh v<VD>, v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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StoreFPR(VD,fmt_mdmx,MX_Msgn(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL)));
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,110000:MDMX:64::MUL.fmt
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"mul.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Mul(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110011:MDMX:64::MULA.fmt
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"mula.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_MulA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,1,0000,110011:MDMX:64::MULL.fmt
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"mull.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_MulL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
|
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|
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110010:MDMX:64::MULS.fmt
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"muls.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_MulS(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
|
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|
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011110,5.FMTSEL,5.VT,5.VS,1,0000,110010:MDMX:64::MULSL.fmt
|
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"mulsl.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
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MX_MulSL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
|
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}
|
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|
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|
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001111:MDMX:64::NOR.fmt
|
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"nor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
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*mdmx:
|
||||
{
|
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check_mdmx (SD_, instruction_0);
|
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_Nor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001110:MDMX:64::OR.fmt
|
||||
"or.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_Or(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,000010:MDMX:64::PICKF.fmt
|
||||
"pickf.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_Pick(0,ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,000011:MDMX:64::PICKT.fmt
|
||||
"pickt.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_Pick(1,ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,1000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.fmt
|
||||
"rach.%s<FMTOP> v<VD>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_H,FMTOP));
|
||||
}
|
||||
|
||||
|
||||
011110,0000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.fmt
|
||||
"racl.%s<FMTOP> v<VD>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_L,FMTOP));
|
||||
}
|
||||
|
||||
|
||||
011110,0100,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.fmt
|
||||
"racm.%s<FMTOP> v<VD>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_M,FMTOP));
|
||||
}
|
||||
|
||||
|
||||
011110,3.SEL,01,5.VT,00000,5.VD,100101:MDMX:64::RNAS.QH
|
||||
"rnas.qh v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
StoreFPR(VD,fmt_mdmx,MX_RNAS(VT,qh_fmtsel(SEL)));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,00000,5.VD,100001:MDMX:64::RNAU.fmt
|
||||
"rnau.%s<FMTSEL> v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_RNAU(VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,3.SEL,01,5.VT,00000,5.VD,100110:MDMX:64::RNES.QH
|
||||
"rnes.qh v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
StoreFPR(VD,fmt_mdmx,MX_RNES(VT,qh_fmtsel(SEL)));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,00000,5.VD,100010:MDMX:64::RNEU.fmt
|
||||
"rneu.%s<FMTSEL> v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_RNEU(VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,3.SEL,01,5.VT,00000,5.VD,100100:MDMX:64::RZS.QH
|
||||
"rzs.qh v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
StoreFPR(VD,fmt_mdmx,MX_RZS(VT,qh_fmtsel(SEL)));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,00000,5.VD,100000:MDMX:64::RZU.fmt
|
||||
"rzu.%s<FMTSEL> v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_RZU(VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,5.SHOP,5.VT,5.VS,5.VD,011111:MDMX:64::SHFL.op.fmt
|
||||
"shfl.%s<SHOP> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, SHOP))
|
||||
StoreFPR(VD,fmt_mdmx,MX_SHFL(SHOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx)));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,010000:MDMX:64::SLL.fmt
|
||||
"sll.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_ShiftLeftLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,3.SEL,01,5.VT,5.VS,5.VD,010011:MDMX:64::SRA.QH
|
||||
"sra.qh v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
StoreFPR(VD,fmt_mdmx,MX_ShiftRightArith(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL)));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,010010:MDMX:64::SRL.fmt
|
||||
"srl.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_ShiftRightLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001010:MDMX:64::SUB.fmt
|
||||
"sub.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_Sub(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,0,0000,110110:MDMX:64::SUBA.fmt
|
||||
"suba.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
MX_SubA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,1,0000,110110:MDMX:64::SUBL.fmt
|
||||
"subl.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
MX_SubL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
|
||||
}
|
||||
|
||||
|
||||
011110,1000,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.fmt
|
||||
"wach.%s<FMTOP> v<VS>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
MX_WACH(FMTOP,ValueFPR(VS,fmt_mdmx));
|
||||
}
|
||||
|
||||
|
||||
011110,0000,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.fmt
|
||||
"wacl.%s<FMTOP> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
MX_WACL(FMTOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx));
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001101:MDMX:64::XOR.fmt
|
||||
"xor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
StoreFPR(VD,fmt_mdmx,MX_Xor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
@ -61,7 +61,9 @@
|
||||
// MIPS Application Specific Extensions (ASEs)
|
||||
//
|
||||
// Instructions for the ASEs are in separate .igen files.
|
||||
// ASEs add instructions on to a base ISA.
|
||||
:model:::mips16:mips16: // m16.igen (and m16.dc)
|
||||
:model:::mdmx:mdmx: // mdmx.igen
|
||||
|
||||
|
||||
// Pseudo instructions known by IGEN
|
||||
@ -5054,6 +5056,7 @@
|
||||
|
||||
|
||||
:include:::m16.igen
|
||||
:include:::mdmx.igen
|
||||
:include:::tx.igen
|
||||
:include:::vr.igen
|
||||
|
||||
|
||||
@ -296,6 +296,24 @@ enum float_operation
|
||||
};
|
||||
|
||||
|
||||
/* The internal representation of an MDMX accumulator.
|
||||
Note that 24 and 48 bit accumulator elements are represented in
|
||||
32 or 64 bits. Since the accumulators are 2's complement with
|
||||
overflow suppressed, high-order bits can be ignored in most contexts. */
|
||||
|
||||
typedef signed32 signed24;
|
||||
typedef signed64 signed48;
|
||||
|
||||
typedef union {
|
||||
signed24 ob[8];
|
||||
signed48 qh[4];
|
||||
} MDMX_accumulator;
|
||||
|
||||
|
||||
/* Conventional system arguments. */
|
||||
#define SIM_STATE sim_cpu *cpu, address_word cia
|
||||
#define SIM_ARGS CPU, cia
|
||||
|
||||
struct _sim_cpu {
|
||||
|
||||
|
||||
@ -439,6 +457,10 @@ struct _sim_cpu {
|
||||
|
||||
pending_write_queue pending;
|
||||
|
||||
/* The MDMX accumulator (used only for MDMX ASE). */
|
||||
MDMX_accumulator acc;
|
||||
#define ACC ((CPU)->acc)
|
||||
|
||||
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
|
||||
read-write instructions. It is set when a linked load occurs. It
|
||||
is tested and cleared by the conditional store. It is cleared
|
||||
@ -707,6 +729,107 @@ decode_coproc (SD, CPU, cia, (instruction))
|
||||
int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
|
||||
|
||||
|
||||
/* MDMX access. */
|
||||
|
||||
typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
|
||||
#define ob_fmtsel(sel) (((sel)<<1)|0x0)
|
||||
#define qh_fmtsel(sel) (((sel)<<2)|0x1)
|
||||
|
||||
#define fmt_mdmx fmt_uninterpreted
|
||||
|
||||
#define MX_VECT_AND (0)
|
||||
#define MX_VECT_NOR (1)
|
||||
#define MX_VECT_OR (2)
|
||||
#define MX_VECT_XOR (3)
|
||||
#define MX_VECT_SLL (4)
|
||||
#define MX_VECT_SRL (5)
|
||||
|
||||
#define MX_VECT_ADD (6)
|
||||
#define MX_VECT_SUB (7)
|
||||
#define MX_VECT_MIN (8)
|
||||
#define MX_VECT_MAX (9)
|
||||
#define MX_VECT_MUL (10)
|
||||
#define MX_VECT_MSGN (11)
|
||||
#define MX_VECT_SRA (12)
|
||||
|
||||
unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
|
||||
#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
|
||||
#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
|
||||
#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
|
||||
#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
|
||||
#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
|
||||
#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
|
||||
#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
|
||||
#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
|
||||
#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
|
||||
#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
|
||||
#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
|
||||
#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
|
||||
#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
|
||||
|
||||
#define MX_C_EQ 0x1
|
||||
#define MX_C_LT 0x4
|
||||
|
||||
void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
|
||||
#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
|
||||
|
||||
unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
|
||||
#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
|
||||
|
||||
#define MX_VECT_ADDA (0)
|
||||
#define MX_VECT_ADDL (1)
|
||||
#define MX_VECT_MULA (2)
|
||||
#define MX_VECT_MULL (3)
|
||||
#define MX_VECT_MULS (4)
|
||||
#define MX_VECT_MULSL (5)
|
||||
#define MX_VECT_SUBA (6)
|
||||
#define MX_VECT_SUBL (7)
|
||||
|
||||
void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
|
||||
#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
|
||||
#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
|
||||
#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
|
||||
#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
|
||||
#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
|
||||
#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
|
||||
#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
|
||||
#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
|
||||
|
||||
#define MX_FMT_OB (0)
|
||||
#define MX_FMT_QH (1)
|
||||
|
||||
/* The following codes chosen to indicate the units of shift. */
|
||||
#define MX_RAC_L (0)
|
||||
#define MX_RAC_M (1)
|
||||
#define MX_RAC_H (2)
|
||||
|
||||
unsigned64 mdmx_rac_op (SIM_STATE, int, int);
|
||||
#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
|
||||
|
||||
void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
|
||||
#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
|
||||
void mdmx_wach (SIM_STATE, int, unsigned64);
|
||||
#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
|
||||
|
||||
#define MX_RND_AS (0)
|
||||
#define MX_RND_AU (1)
|
||||
#define MX_RND_ES (2)
|
||||
#define MX_RND_EU (3)
|
||||
#define MX_RND_ZS (4)
|
||||
#define MX_RND_ZU (5)
|
||||
|
||||
unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
|
||||
#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
|
||||
#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
|
||||
#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
|
||||
#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
|
||||
#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
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#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
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unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
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#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
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/* Memory accesses */
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@ -774,6 +897,7 @@ prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
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void unpredictable_action (sim_cpu *cpu, address_word cia);
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#define NotWordValue(val) not_word_value (SD_, (val))
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#define Unpredictable() unpredictable (SD_)
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#define UnpredictableResult() /* For now, do nothing. */
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INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
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||||
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user