* config/tc-i386.c (md_apply_fix3): Change handling of PCREL reloc
for BFD_ASSEMBLER to only change value when COFF if TE_PE.
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Tue Oct 20 10:49:42 1998 Ian Lance Taylor <ian@cygnus.com>
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* config/tc-i386.c (md_apply_fix3): Change handling of PCREL reloc
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for BFD_ASSEMBLER to only change value when COFF if TE_PE.
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Mon Oct 19 20:20:42 1998 Catherine Moore <clm@cygnus.com>
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* config/tc-sh.h (obj_fix_adjustable): Define.
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@ -1511,6 +1511,28 @@ md_assemble (line)
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}
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}
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if (i.tm.base_opcode == AMD_3DNOW_OPCODE)
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{
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/* These AMD specific instructions have an opcode suffix which
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is coded in the same place as an 8-bit immediate field
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would be. Here we fake an 8-bit immediate operand from the
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opcode suffix stored in tm.extension_opcode.
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Note: this "opcode suffix" has nothing to do with what gas
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calls opcode suffixes. gas opcode suffixes should really
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be called instruction mnemonic suffixes. FIXME maybe. */
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expressionS *exp;
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assert(i.imm_operands == 0 && i.operands <= 2);
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exp = &im_expressions[i.imm_operands++];
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i.imms[i.operands] = exp;
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i.types[i.operands++] = Imm8;
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exp->X_op = O_constant;
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exp->X_add_number = i.tm.extension_opcode;
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i.tm.extension_opcode = None;
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}
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/* For insns with operands there are more diddles to do to the opcode. */
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if (i.operands)
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{
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@ -2283,7 +2305,7 @@ i386_operand (operand_string)
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op_string = end_op;
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if (is_space_char (*op_string))
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++op_string;
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if (*op_string)
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if (*op_string == ':')
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{
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if (r->reg_type & (SReg2 | SReg3))
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{
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@ -3090,7 +3112,10 @@ md_apply_fix3 (fixP, valp, seg)
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{
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#ifndef OBJ_AOUT
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if (OUTPUT_FLAVOR == bfd_target_elf_flavour
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|| OUTPUT_FLAVOR == bfd_target_coff_flavour)
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#ifdef TE_PE
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|| OUTPUT_FLAVOR == bfd_target_coff_flavour
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#endif
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)
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value += fixP->fx_where + fixP->fx_frag->fr_address;
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#endif
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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