MIPS: Add microMIPS R5 support

Add base microMIPS Release 5 ISA support and the ERETNC instruction in
particular, as per the architecture specifications[1][2].

Most of this change by Andrew Bennett.

References:

[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
    Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
    Instructions", pp. 266-267

[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
    Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
    Instructions", pp. 326-327

	binutils/
	* NEWS: Mention microMIPS Release 5 ISA support.

	opcodes/
	* micromips-opc.c (I36): New macro.
	(micromips_opcodes): Add "eretnc".

	gas/
	* testsuite/gas/mips/micromips@r5.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.
This commit is contained in:
Maciej W. Rozycki 2017-06-30 07:21:56 +01:00
parent 9785fc2a4d
commit f5b2fd523f
7 changed files with 31 additions and 1 deletions

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@ -1,3 +1,7 @@
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
* NEWS: Mention microMIPS Release 5 ISA support.
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.

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@ -1,5 +1,8 @@
-*- text -*-
* The MIPS port now supports the microMIPS Release 5 ISA for assembly and
disassembly.
* The MIPS port now supports the Imagination interAptiv MR2 processor,
which implements the MIPS32r3 ISA, the MIPS16e2 ASE as well as a couple
of implementation-specific regular MIPS and MIPS16e2 ASE instructions.

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@ -1,3 +1,9 @@
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>

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@ -0,0 +1,9 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#source: r5.s
#name: Test MIPS32r5 instructions
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0001f37c eretnc
\.\.\.

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@ -1565,7 +1565,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "xpa-err" [mips_arch_list_matching mips32r2 !micromips]
run_dump_test_arches "xpa-virt-err" \
[mips_arch_list_matching mips32r2 !micromips]
run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5 !micromips]
run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5]
run_dump_test "pcrel-1"
run_dump_test "pcrel-2"

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@ -1,3 +1,9 @@
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
Maciej W. Rozycki <macro@imgtec.com>
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>

View File

@ -253,6 +253,7 @@ decode_micromips_operand (const char *p)
are accepted as 64-bit microMIPS ISA. */
#define I1 INSN_ISA1
#define I3 INSN_ISA3
#define I36 INSN_ISA32R5
/* MIPS DSP ASE support. */
#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
@ -687,6 +688,7 @@ const struct mips_opcode micromips_opcodes[] =
{"ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 },
{"ei", "s", 0x0000577c, 0xffe0ffff, WR_1|WR_C0, 0, I1, 0, 0 },
{"eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1, 0, 0 },
{"eretnc", "", 0x0001f37c, 0xffffffff, NODS, 0, I36, 0, 0 },
{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 },
{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },