* simops.c: Implement remaining 2 byte instructions. Call
abort for instructions we're not implementing now.
This commit is contained in:
Jeff Law
parent
350d33b87f
commit
f5f13c1d73
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@ -1,3 +1,8 @@
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Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Implement remaining 2 byte instructions. Call
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abort for instructions we're not implementing now.
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Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Implement lots of random instructions.
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@ -173,9 +173,12 @@ void OP_FCB40000 ()
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{
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}
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/* mov */
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/* mov (di,am), dn */
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void OP_F300 ()
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{
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
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}
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/* mov (abs16), dn */
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@ -228,9 +231,12 @@ void OP_FCB00000 ()
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{
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}
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/* mov */
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/* mov (di,am), an*/
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void OP_F380 ()
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{
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State.regs[REG_A0 + ((insn & 0x30) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
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}
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/* mov */
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@ -287,9 +293,12 @@ void OP_FC910000 ()
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{
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}
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/* mov */
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/* mov dm, (di,an) */
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void OP_F340 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
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}
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/* mov dm, (abs16) */
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@ -342,9 +351,12 @@ void OP_FC900000 ()
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{
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}
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/* mov */
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/* mov am, (di,an) */
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void OP_F3C0 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
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State.regs[REG_A0 + ((insn & 0x30) >> 8)]);
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}
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/* mov */
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@ -431,9 +443,12 @@ void OP_FCB80000 ()
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{
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}
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/* movbu */
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/* movbu (di,am), dn */
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void OP_F400 ()
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{
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
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}
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/* movbu (abs16), dn */
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@ -484,9 +499,12 @@ void OP_FC920000 ()
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{
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}
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/* movbu */
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/* movbu dm, (di,an) */
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void OP_F440 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
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}
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/* movbu dm, (abs16) */
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@ -537,9 +555,12 @@ void OP_FCBC0000 ()
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{
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}
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/* movhu */
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/* movhu (di,am), dn */
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void OP_F480 ()
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{
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
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}
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/* movhu (abs16), dn */
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@ -590,9 +611,12 @@ void OP_FC930000 ()
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{
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}
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/* movhu */
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/* movhu dm, (di,an) */
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void OP_F4C0 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
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}
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/* movhu dm, (abs16) */
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@ -1802,7 +1826,7 @@ void OP_F280 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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}
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/* beq */
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/* beq label:8 */
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void OP_C800 ()
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{
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/* The dispatching code will add 2 after we return, so
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@ -1811,7 +1835,7 @@ void OP_C800 ()
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bne */
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/* bne label:8 */
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void OP_C900 ()
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{
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/* The dispatching code will add 2 after we return, so
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@ -1820,129 +1844,194 @@ void OP_C900 ()
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bgt */
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/* bgt label:8 */
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void OP_C100 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!((PSW & PSW_Z)
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|| (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bge */
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/* bge label:8 */
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void OP_C200 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* ble */
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/* ble label:8 */
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void OP_C300 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if ((PSW & PSW_Z)
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|| (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* blt */
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/* blt label:8 */
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void OP_C000 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bhi */
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/* bhi label:8 */
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void OP_C500 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bcc */
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/* bcc label:8 */
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void OP_C600 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!(PSW & PSW_C))
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bls */
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/* bls label:8 */
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void OP_C700 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bcs */
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/* bcs label:8 */
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void OP_C400 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (PSW & PSW_C)
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* bvc */
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/* bvc label:8 */
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void OP_F8E800 ()
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{
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (!(PSW & PSW_V))
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State.pc += SEXT8 (insn & 0xff) - 3;
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}
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/* bvs */
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/* bvs label:8 */
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void OP_F8E900 ()
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{
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (PSW & PSW_V)
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State.pc += SEXT8 (insn & 0xff) - 3;
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}
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/* bnc */
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/* bnc label:8 */
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void OP_F8EA00 ()
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{
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (!(PSW & PSW_N))
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State.pc += SEXT8 (insn & 0xff) - 3;
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}
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/* bns */
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/* bns label:8 */
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void OP_F8EB00 ()
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{
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (PSW & PSW_N)
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State.pc += SEXT8 (insn & 0xff) - 3;
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}
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/* bra */
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/* bra label:8 */
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void OP_CA00 ()
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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State.pc += SEXT8 (insn & 0xff) - 2;
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}
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/* leq */
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void OP_D8 ()
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{
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abort ();
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}
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/* lne */
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void OP_D9 ()
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{
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abort ();
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}
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/* lgt */
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void OP_D1 ()
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{
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abort ();
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}
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/* lge */
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void OP_D2 ()
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{
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abort ();
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}
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/* lle */
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void OP_D3 ()
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{
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abort ();
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}
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/* llt */
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void OP_D0 ()
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{
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abort ();
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}
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/* lhi */
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void OP_D5 ()
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{
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abort ();
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}
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/* lcc */
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void OP_D6 ()
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{
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abort ();
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}
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/* lls */
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void OP_D7 ()
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{
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abort ();
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}
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/* lcs */
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void OP_D4 ()
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{
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abort ();
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}
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/* lra */
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void OP_DA ()
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{
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abort ();
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}
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/* setlb */
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void OP_DB ()
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{
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abort ();
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}
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/* jmp (an) */
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@ -2267,16 +2356,19 @@ void OP_F0FC ()
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/* rti */
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void OP_F0FD ()
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{
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abort ();
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}
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/* trap */
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void OP_F0FE ()
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{
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abort ();
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}
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/* rtm */
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void OP_F0FF ()
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{
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abort ();
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}
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/* nop */
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