sim: mcore: convert to common memory/verbose functions
Re-use the existing memory core that handles reads/writes. The verbose command is converted to the common --verbose flag since only a few call sites use it now.
This commit is contained in:
Mike Frysinger
parent
e53e5aab53
commit
f63036b811
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@ -1,3 +1,28 @@
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2015-04-21 Mike Frysinger <vapier@gentoo.org>
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* interp.c (mcore_regset): Delete msize & memory.
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(issue_messages, mem, wbat, what, wlat, rbat, what, wlat,
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sim_memory_size, MEM_SIZE_FLOOR, sim_size, init_pointers): Delete.
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(DEFAULT_MEMORY_SIZE): Define.
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(set_initial_gprs): Delete memsize handling and call to init_pointers.
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Change cpu.asregs.msize to DEFAULT_MEMORY_SIZE.
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(syscall_read_mem): Change memcpy to sim_core_read_buffer.
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(syscall_write_mem): Change memcpy to sim_core_write_buffer.
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(process_stub): Change issue_messages to STATE_VERBOSE_P.
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(util): Turn printf into a stub. Change issue_messages to
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STATE_VERBOSE_P.
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(rbat, rhat, rlat, wbat, what, wlat): Define to sim core funcs.
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(sim_resume): Change issue_messages to STATE_VERBOSE_P.
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Delete cpu.asregs.msize range checks.
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(sim_write, sim_read): Delete.
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(sim_store_register, sim_fetch_register): Delete call to
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init_pointers.
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(sim_open): Delete osize, call to sim_size, and issue_messages. Call
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sim_do_commandf to setup memory.
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(sim_create_inferior): Delete issue_messages handling. Change
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cpu.asregs.msize to DEFAULT_MEMORY_SIZE. Change strcpy to
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sim_core_write_buffer.
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2015-04-21 Mike Frysinger <vapier@gentoo.org>
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* interp.c (WATCHFUNCTIONS): Undef it.
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@ -113,8 +113,6 @@ struct mcore_regset
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int cycles;
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int insts;
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int exception;
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unsigned long msize;
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unsigned char * memory;
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word * active_gregs;
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};
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@ -129,8 +127,6 @@ union
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static int memcycles = 1;
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static int issue_messages = 0;
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#define gr asregs.active_gregs
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#define cr asregs.cregs
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#define sr asregs.cregs[0]
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@ -146,7 +142,6 @@ static int issue_messages = 0;
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#define ss4 asregs.cregs[10]
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#define gcr asregs.cregs[11]
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#define gsr asregs.cregs[12]
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#define mem asregs.memory
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/* maniuplate the carry bit */
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#define C_ON() (cpu.sr & 1)
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@ -165,243 +160,19 @@ static int issue_messages = 0;
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#define PARM4 5
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#define RET1 2 /* register for return values. */
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static void
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wbat (word x, word v)
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{
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if (((uword)x) >= cpu.asregs.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte write to 0x%x outside memory range\n", x);
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cpu.asregs.exception = SIGSEGV;
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}
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else
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{
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unsigned char *p = cpu.mem + x;
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p[0] = v;
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}
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}
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static void
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wlat (word x, word v)
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{
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if (((uword)x) >= cpu.asregs.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word write to 0x%x outside memory range\n", x);
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cpu.asregs.exception = SIGSEGV;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word write to unaligned memory address: 0x%x\n", x);
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cpu.asregs.exception = SIGBUS;
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}
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else if (! target_big_endian)
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{
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unsigned char * p = cpu.mem + x;
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p[3] = v >> 24;
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p[2] = v >> 16;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char * p = cpu.mem + x;
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p[0] = v >> 24;
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p[1] = v >> 16;
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p[2] = v >> 8;
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p[3] = v;
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}
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}
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}
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static void
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what (word x, word v)
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{
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if (((uword)x) >= cpu.asregs.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short write to 0x%x outside memory range\n", x);
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cpu.asregs.exception = SIGSEGV;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short write to unaligned memory address: 0x%x\n",
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x);
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cpu.asregs.exception = SIGBUS;
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}
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else if (! target_big_endian)
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{
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unsigned char * p = cpu.mem + x;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char * p = cpu.mem + x;
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p[0] = v >> 8;
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p[1] = v;
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}
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}
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}
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/* Read functions. */
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static int
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rbat (word x)
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{
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if (((uword)x) >= cpu.asregs.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte read from 0x%x outside memory range\n", x);
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cpu.asregs.exception = SIGSEGV;
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return 0;
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}
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else
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{
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unsigned char * p = cpu.mem + x;
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return p[0];
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}
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}
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static int
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rlat (word x)
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{
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if (((uword) x) >= cpu.asregs.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word read from 0x%x outside memory range\n", x);
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cpu.asregs.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word read from unaligned address: 0x%x\n", x);
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cpu.asregs.exception = SIGBUS;
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return 0;
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}
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else if (! target_big_endian)
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{
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unsigned char * p = cpu.mem + x;
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return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char * p = cpu.mem + x;
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return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
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}
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}
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}
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static int
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rhat (word x)
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{
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if (((uword)x) >= cpu.asregs.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short read from 0x%x outside memory range\n", x);
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cpu.asregs.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short read from unaligned address: 0x%x\n", x);
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cpu.asregs.exception = SIGBUS;
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return 0;
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}
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else if (! target_big_endian)
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{
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unsigned char * p = cpu.mem + x;
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return (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char * p = cpu.mem + x;
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return (p[0] << 8) | p[1];
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}
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}
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}
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/* Default to a 8 Mbyte (== 2^23) memory space. */
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/* TODO: Delete all this custom memory logic and move to common sim helpers. */
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static int sim_memory_size = 23;
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#define MEM_SIZE_FLOOR 64
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static void
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sim_size (int power)
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{
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sim_memory_size = power;
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cpu.asregs.msize = 1 << sim_memory_size;
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if (cpu.mem)
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free (cpu.mem);
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/* Watch out for the '0 count' problem. There's probably a better
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way.. e.g., why do we use 64 here? */
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if (cpu.asregs.msize < 64) /* Ensure a boundary. */
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cpu.mem = (unsigned char *) calloc (64, (64 + cpu.asregs.msize) / 64);
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else
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cpu.mem = (unsigned char *) calloc (64, cpu.asregs.msize / 64);
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if (!cpu.mem)
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{
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if (issue_messages)
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fprintf (stderr,
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"Not enough VM for simulation of %lu bytes of RAM\n",
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cpu.asregs.msize);
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cpu.asregs.msize = 1;
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cpu.mem = (unsigned char *) calloc (1, 1);
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}
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}
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static void
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init_pointers (void)
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{
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if (cpu.asregs.msize != (1 << sim_memory_size))
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sim_size (sim_memory_size);
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}
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#define DEFAULT_MEMORY_SIZE 0x800000
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static void
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set_initial_gprs (SIM_CPU *scpu)
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{
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int i;
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long space;
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unsigned long memsize;
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init_pointers ();
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/* Set up machine just out of reset. */
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CPU_PC_SET (scpu, 0);
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cpu.sr = 0;
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memsize = cpu.asregs.msize / (1024 * 1024);
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if (issue_messages > 1)
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fprintf (stderr, "Simulated memory of %lu Mbytes (0x0 .. 0x%08lx)\n",
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memsize, cpu.asregs.msize - 1);
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/* Clean out the GPRs and alternate GPRs. */
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for (i = 0; i < 16; i++)
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{
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@ -416,7 +187,7 @@ set_initial_gprs (SIM_CPU *scpu)
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cpu.asregs.active_gregs = &cpu.asregs.gregs[0];
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/* ABI specifies initial values for these registers. */
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cpu.gr[0] = cpu.asregs.msize - 4;
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cpu.gr[0] = DEFAULT_MEMORY_SIZE - 4;
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/* dac fix, the stack address must be 8-byte aligned! */
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cpu.gr[0] = cpu.gr[0] - cpu.gr[0] % 8;
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@ -432,16 +203,20 @@ static int
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syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
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unsigned long taddr, char *buf, int bytes)
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{
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memcpy (buf, cpu.mem + taddr, bytes);
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return bytes;
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SIM_DESC sd = (SIM_DESC) sc->p1;
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SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
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}
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static int
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syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
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unsigned long taddr, const char *buf, int bytes)
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{
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memcpy (cpu.mem + taddr, buf, bytes);
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return bytes;
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SIM_DESC sd = (SIM_DESC) sc->p1;
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SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
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}
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/* Simulate a monitor trap. */
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@ -489,7 +264,7 @@ process_stub (SIM_DESC sd, int what)
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break;
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default:
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "Unhandled stub opcode: %d\n", what);
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break;
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}
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@ -505,31 +280,12 @@ util (SIM_DESC sd, unsigned what)
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break;
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case 1: /* printf */
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{
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unsigned long a[6];
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unsigned char *s;
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int i;
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a[0] = (unsigned long)(cpu.mem + cpu.gr[PARM1]);
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for (s = (unsigned char *)a[0], i = 1 ; *s && i < 6 ; s++)
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{
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if (*s == '%')
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{
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if (*++s == 's')
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a[i] = (unsigned long)(cpu.mem + cpu.gr[PARM1+i]);
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else
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a[i] = cpu.gr[i+PARM1];
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i++;
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}
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}
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cpu.gr[RET1] = printf ((char *)a[0], a[1], a[2], a[3], a[4], a[5]);
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}
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "WARNING: printf unimplemented\n");
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break;
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case 2: /* scanf */
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "WARNING: scanf unimplemented\n");
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break;
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@ -542,7 +298,7 @@ util (SIM_DESC sd, unsigned what)
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break;
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default:
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "Unhandled util code: %x\n", what);
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break;
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}
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@ -586,6 +342,13 @@ int WLW;
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#define IMM5 ((inst >> 4) & 0x1F)
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#define IMM4 ((inst) & 0xF)
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#define rbat(X) sim_core_read_1 (scpu, 0, read_map, X)
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#define rhat(X) sim_core_read_2 (scpu, 0, read_map, X)
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#define rlat(X) sim_core_read_4 (scpu, 0, read_map, X)
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#define wbat(X, D) sim_core_write_1 (scpu, 0, write_map, X, D)
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#define what(X, D) sim_core_write_2 (scpu, 0, write_map, X, D)
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#define wlat(X, D) sim_core_write_4 (scpu, 0, write_map, X, D)
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static int tracing = 0;
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void
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@ -751,17 +514,17 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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break;
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case 0x4: /* stop */
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "WARNING: stop unimplemented\n");
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break;
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case 0x5: /* wait */
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "WARNING: wait unimplemented\n");
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break;
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case 0x6: /* doze */
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "WARNING: doze unimplemented\n");
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break;
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@ -1522,19 +1285,8 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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if (needfetch)
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{
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/* Do not let him fetch from a bad address! */
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if (((uword)pc) >= cpu.asregs.msize)
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{
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if (issue_messages)
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fprintf (stderr, "PC loaded at 0x%x is outside of available memory! (0x%x)\n", oldpc, pc);
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cpu.asregs.exception = SIGSEGV;
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}
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else
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{
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ibuf = rlat (pc & 0xFFFFFFFC);
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needfetch = 0;
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}
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ibuf = rlat (pc & 0xFFFFFFFC);
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needfetch = 0;
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}
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}
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while (!cpu.asregs.exception);
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@ -1547,35 +1299,9 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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cpu.asregs.cycles += memops * memcycles; /* and memop cycle delays */
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}
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int
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sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
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{
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int i;
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init_pointers ();
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memcpy (& cpu.mem[addr], buffer, size);
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return size;
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}
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int
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sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
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{
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int i;
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init_pointers ();
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memcpy (buffer, & cpu.mem[addr], size);
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return size;
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}
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int
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sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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{
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init_pointers ();
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if (rn < NUM_MCORE_REGS && rn >= 0)
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{
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if (length == 4)
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@ -1596,8 +1322,6 @@ sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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int
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sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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{
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init_pointers ();
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if (rn < NUM_MCORE_REGS && rn >= 0)
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{
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if (length == 4)
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@ -1695,8 +1419,8 @@ free_state (SIM_DESC sd)
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SIM_DESC
|
||||
sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
|
||||
{
|
||||
int i;
|
||||
SIM_DESC sd = sim_state_alloc (kind, cb);
|
||||
int i, osize;
|
||||
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
|
||||
|
||||
/* The cpu data is kept in a separately allocated chunk of memory. */
|
||||
|
|
@ -1747,15 +1471,6 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
|
|||
return 0;
|
||||
}
|
||||
|
||||
osize = sim_memory_size;
|
||||
|
||||
if (kind == SIM_OPEN_STANDALONE)
|
||||
issue_messages = 1;
|
||||
|
||||
/* Discard and reacquire memory -- start with a clean slate. */
|
||||
sim_size (1); /* small */
|
||||
sim_size (osize); /* and back again */
|
||||
|
||||
/* CPU specific initialization. */
|
||||
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
|
||||
{
|
||||
|
|
@ -1767,6 +1482,9 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
|
|||
set_initial_gprs (cpu); /* Reset the GPR registers. */
|
||||
}
|
||||
|
||||
/* Default to a 8 Mbyte (== 2^23) memory space. */
|
||||
sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE);
|
||||
|
||||
return sd;
|
||||
}
|
||||
|
||||
|
|
@ -1791,12 +1509,9 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
|
|||
|
||||
|
||||
/* Set the initial register set. */
|
||||
l = issue_messages;
|
||||
issue_messages = 0;
|
||||
set_initial_gprs (scpu);
|
||||
issue_messages = l;
|
||||
|
||||
hi_stack = cpu.asregs.msize - 4;
|
||||
hi_stack = DEFAULT_MEMORY_SIZE - 4;
|
||||
CPU_PC_SET (scpu, bfd_get_start_address (prog_bfd));
|
||||
|
||||
/* Calculate the argument and environment strings. */
|
||||
|
|
@ -1848,7 +1563,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
|
|||
|
||||
/* Copy the string. */
|
||||
l = strlen (* avp) + 1;
|
||||
strcpy ((char *)(cpu.mem + strings), *avp);
|
||||
sim_core_write_buffer (sd, scpu, write_map, *avp, strings, l);
|
||||
|
||||
/* Bump the pointers. */
|
||||
avp++;
|
||||
|
|
@ -1879,7 +1594,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
|
|||
|
||||
/* Copy the string. */
|
||||
l = strlen (* avp) + 1;
|
||||
strcpy ((char *)(cpu.mem + strings), *avp);
|
||||
sim_core_write_buffer (sd, scpu, write_map, *avp, strings, l);
|
||||
|
||||
/* Bump the pointers. */
|
||||
avp++;
|
||||
|
|
|
|||
Loading…
Reference in New Issue