* gas/mips/mips4.s: Split out fp instruction from here ...
* gas/mips/mips4-fp.s: ... to here. * gas/mips/mips4.d: Update. * gas/mips/mips4-fp.l: New file. Check error messages with -msoft-float. * gas/mips/mips4-fp.d: New file. Check disassembly with hard-float. * gas/mips/mips32r2.s: Split out fp instructions from here ... * gas/mips/mips32r2-fp32.s: ... to here. * gas/mips/mips32r2.d: Update. * gas/mips/mips32r2-fp32.l: New file. Check error messages with -msoft-float. * gas/mips/mips32r2-fp32.d: New file. Check disassembly with hard-float. * gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New test derived from mips32r2-ill. * gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check error messages for soft-float targets. * gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l: New test for -msingle-float. * gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l: New test for -msoft-float. * gas/mips/mips-hard-float-flag.s, gas/mips/mips-hard-float-flag.l: New test for -mhard-float. * gas/mips/mips-double-float-flag.s, gas/mips/mips-double-float-flag.l: New test for -mdouble-float. * gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests. Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list test with -msoft-float. Run new mips-macro-ill-sfp test with -msingle-float. Run new mips-macro-ill-nofp test with -msoft-float. Run new mips-hard-float-flag and mips-double-float-flag tests.
This commit is contained in:
Adam Nemet
parent
037b32b9ff
commit
f6829a452a
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@ -1,3 +1,44 @@
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2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
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* gas/mips/mips4.s: Split out fp instruction from here ...
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* gas/mips/mips4-fp.s: ... to here.
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* gas/mips/mips4.d: Update.
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* gas/mips/mips4-fp.l: New file. Check error messages with
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-msoft-float.
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* gas/mips/mips4-fp.d: New file. Check disassembly with
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hard-float.
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* gas/mips/mips32r2.s: Split out fp instructions from here ...
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* gas/mips/mips32r2-fp32.s: ... to here.
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* gas/mips/mips32r2.d: Update.
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* gas/mips/mips32r2-fp32.l: New file. Check error messages with
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-msoft-float.
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* gas/mips/mips32r2-fp32.d: New file. Check disassembly with
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hard-float.
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* gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New
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test derived from mips32r2-ill.
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* gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check
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error messages for soft-float targets.
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* gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l:
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New test for -msingle-float.
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* gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l:
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New test for -msoft-float.
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* gas/mips/mips-hard-float-flag.s,
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gas/mips/mips-hard-float-flag.l: New test for -mhard-float.
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* gas/mips/mips-double-float-flag.s,
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gas/mips/mips-double-float-flag.l: New test for -mdouble-float.
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* gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests.
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Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run
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new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list
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test with -msoft-float. Run new mips-macro-ill-sfp test with
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-msingle-float. Run new mips-macro-ill-nofp test with
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-msoft-float. Run new mips-hard-float-flag and
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mips-double-float-flag tests.
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2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx.
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@ -0,0 +1,3 @@
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.*: Assembler messages:
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.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
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.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
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@ -0,0 +1,17 @@
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.text
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foo:
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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.set singlefloat
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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.set push
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.set doublefloat
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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.set pop
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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@ -0,0 +1,5 @@
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.*: Assembler messages:
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.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
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.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
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.*:16: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
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.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
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@ -0,0 +1,17 @@
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.text
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foo:
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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.set softfloat
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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.set push
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.set hardfloat
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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.set pop
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add.s $f2,$f2,$f2
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add.d $f2,$f2,$f2
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@ -0,0 +1,19 @@
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.*: Assembler messages:
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.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
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.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
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.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
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.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
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.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
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.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
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.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
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.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
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.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
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.*:18: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$f2,d'
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.*:19: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$22,d'
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.*:20: Error: opcode not supported on this processor: .* \(.*\) `l.s \$f2,d'
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.*:21: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f2,1.2'
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.*:22: Error: opcode not supported on this processor: .* \(.*\) `li.s \$22,1.2'
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.*:24: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
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.*:25: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
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.*:26: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
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.*:28: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.s \$f4,\$f6,\$4'
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@ -0,0 +1,32 @@
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# Macros that are disabled without floating point.
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.text
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double_float:
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ldc1 $f2, d
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ldc1 $22, d
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l.d $f2, d
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li.d $f2, 1.2
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li.d $22, 1.2
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sdc1 $f2, d
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sdc1 $22, d
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s.d $f2, d
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trunc.w.d $f4,$f6,$4
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single_float:
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lwc1 $f2, d
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lwc1 $22, d
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l.s $f2, d
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li.s $f2, 1.2
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li.s $22, 1.2
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sdc1 $f2, d
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sdc1 $22, d
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s.d $f2, d
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trunc.w.s $f4,$f6,$4
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d:
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.word 0
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.word 0
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@ -0,0 +1,10 @@
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.*: Assembler messages:
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.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
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.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
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.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
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.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
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.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
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.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
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.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
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.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
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.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
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@ -0,0 +1,19 @@
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# Macros that are disabled without double-precision fp insns.
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.text
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double_float:
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ldc1 $f2, d
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ldc1 $22, d
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l.d $f2, d
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li.d $f2, 1.2
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li.d $22, 1.2
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sdc1 $f2, d
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sdc1 $22, d
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s.d $f2, d
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trunc.w.d $f4,$f6,$4
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d:
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.word 0
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.word 0
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@ -475,6 +475,9 @@ if { [istarget mips*-*-vxworks*] } {
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if $elf { run_dump_test "lif-svr4pic" }
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if $elf { run_dump_test "lif-xgot" }
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run_dump_test_arches "mips4" [mips_arch_list_matching mips4]
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run_dump_test_arches "mips4-fp" [mips_arch_list_matching mips4]
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run_list_test_arches "mips4-fp" "-32 -msoft-float" \
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[mips_arch_list_matching mips4]
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run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
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if $ilocks {
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run_dump_test "mul-ilocks"
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@ -546,12 +549,20 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test_arches "mips32" [mips_arch_list_matching mips32]
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run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32]
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run_list_test_arches "mips32-sf32" "-32 -msoft-float" \
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[mips_arch_list_matching mips32]
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run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2]
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run_dump_test_arches "mips32r2-fp32" \
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[mips_arch_list_matching mips32r2]
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run_list_test_arches "mips32r2-fp32" "-32 -msoft-float" \
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[mips_arch_list_matching mips32r2]
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run_list_test_arches "mips32r2-ill" "-32" \
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[mips_arch_list_matching mips32r2 gpr32]
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[mips_arch_list_matching mips32r2 gpr32]
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run_list_test_arches "mips32r2-ill-fp64" "-mabi=o64" \
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[mips_arch_list_matching mips32r2 gpr64]
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[mips_arch_list_matching mips32r2 gpr64]
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run_list_test_arches "mips32r2-ill-nofp" "-32 -msoft-float" \
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[mips_arch_list_matching mips32r2]
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run_dump_test_arches "mips64" [mips_arch_list_matching mips64]
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@ -795,4 +806,16 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "align2"
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run_dump_test "align2-el"
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run_dump_test "odd-float"
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run_list_test_arches "mips-macro-ill-sfp" "-32 -msingle-float" \
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[mips_arch_list_matching mips2]
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run_list_test_arches "mips-macro-ill-nofp" "-32 -msoft-float" \
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[mips_arch_list_matching mips2]
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run_list_test_arches "mips-hard-float-flag" \
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"-32 -msoft-float -mhard-float" \
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[mips_arch_list_matching mips1]
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run_list_test_arches "mips-double-float-flag" \
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"-32 -msingle-float -mdouble-float" \
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[mips_arch_list_matching mips1]
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||||
}
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||||
|
|
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|||
|
|
@ -0,0 +1,8 @@
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|||
.*: Assembler messages:
|
||||
.*:5: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f1,1.0'
|
||||
.*:6: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f3,1.9'
|
||||
.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f5,\$f1,\$f3'
|
||||
.*:8: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
|
||||
.*:9: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
|
||||
.*:10: Error: opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
|
||||
.*:11: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
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#name: MIPS MIPS32r2 fp instructions
|
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#as: -32
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||||
|
||||
# Check MIPS32 Release 2 (mips32r2) FP instruction assembly
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 44710000 mfhc1 \$17,\$f0
|
||||
0+0004 <[^>]*> 44f10000 mthc1 \$17,\$f0
|
||||
#pass
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
.*: Assembler messages:
|
||||
.*:12: Error: opcode not supported on this processor: .* \(.*\) `mfhc1 \$17,\$f0'
|
||||
.*:13: Error: opcode not supported on this processor: .* \(.*\) `mthc1 \$17,\$f0'
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
# source file to test assembly of mips32r2 FP instructions
|
||||
|
||||
.text
|
||||
text_label:
|
||||
|
||||
# FPU (cp1) instructions
|
||||
#
|
||||
# Even registers are supported w/ 32-bit FPU, odd
|
||||
# registers supported only for 64-bit FPU.
|
||||
# Only the 32-bit FPU instructions are tested here.
|
||||
|
||||
mfhc1 $17, $f0
|
||||
mthc1 $17, $f0
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
.*: Assembler messages:
|
||||
.*:12: Error: Improper position \([0-9]*\)
|
||||
.*:15: Error: Improper position \(32\)
|
||||
.*:18: Error: Improper extract size \(0, position 0\)
|
||||
.*:21: Error: Improper extract size \(33, position 0\)
|
||||
.*:24: Error: Improper extract size \(0, position 0\)
|
||||
.*:27: Error: Improper extract size \(2, position 31\)
|
||||
.*:30: Error: Improper position \([0-9]*\)
|
||||
.*:33: Error: Improper position \(32\)
|
||||
.*:36: Error: Improper insert size \(0, position 0\)
|
||||
.*:39: Error: Improper insert size \(33, position 0\)
|
||||
.*:42: Error: Improper insert size \(0, position 0\)
|
||||
.*:45: Error: Improper insert size \(2, position 31\)
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
# source file to test illegal mips32r2 instructions
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.text
|
||||
text_label:
|
||||
|
||||
# insert and extract position/size checks:
|
||||
|
||||
# ext constraint: 0 <= pos < 32
|
||||
ext $4, $5, -1, 1 # error
|
||||
ext $4, $5, 0, 1
|
||||
ext $4, $5, 31, 1
|
||||
ext $4, $5, 32, 1 # error
|
||||
|
||||
# ext constraint: 0 < size <= 32
|
||||
ext $4, $5, 0, 0 # error
|
||||
ext $4, $5, 0, 1
|
||||
ext $4, $5, 0, 32
|
||||
ext $4, $5, 0, 33 # error
|
||||
|
||||
# ext constraint: 0 < (pos+size) <= 32
|
||||
ext $4, $5, 0, 0 # error
|
||||
ext $4, $5, 0, 1
|
||||
ext $4, $5, 31, 1
|
||||
ext $4, $5, 31, 2 # error
|
||||
|
||||
# ins constraint: 0 <= pos < 32
|
||||
ins $4, $5, -1, 1 # error
|
||||
ins $4, $5, 0, 1
|
||||
ins $4, $5, 31, 1
|
||||
ins $4, $5, 32, 1 # error
|
||||
|
||||
# ins constraint: 0 < size <= 32
|
||||
ins $4, $5, 0, 0 # error
|
||||
ins $4, $5, 0, 1
|
||||
ins $4, $5, 0, 32
|
||||
ins $4, $5, 0, 33 # error
|
||||
|
||||
# ins constraint: 0 < (pos+size) <= 32
|
||||
ins $4, $5, 0, 0 # error
|
||||
ins $4, $5, 0, 1
|
||||
ins $4, $5, 31, 1
|
||||
ins $4, $5, 31, 2 # error
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
||||
#name: MIPS MIPS32r2 instructions
|
||||
#name: MIPS MIPS32r2 non-fp instructions
|
||||
#as: -32
|
||||
|
||||
# Check MIPS32 Release 2 (mips32r2) instruction assembly
|
||||
# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
|
|
@ -40,8 +40,6 @@ Disassembly of section .text:
|
|||
0+0078 <[^>]*> 416a6020 ei \$10
|
||||
0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
|
||||
0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
|
||||
0+0084 <[^>]*> 44710000 mfhc1 \$17,\$f0
|
||||
0+0088 <[^>]*> 44f10000 mthc1 \$17,\$f0
|
||||
0+008c <[^>]*> 48715555 mfhc2 \$17,0x5555
|
||||
0+0090 <[^>]*> 48f15555 mthc2 \$17,0x5555
|
||||
0+0084 <[^>]*> 48715555 mfhc2 \$17,0x5555
|
||||
0+0088 <[^>]*> 48f15555 mthc2 \$17,0x5555
|
||||
...
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# source file to test assembly of mips32r2 instructions
|
||||
# source file to test assembly of mips32r2 *non-fp* instructions
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
|
@ -63,15 +63,6 @@ text_label:
|
|||
|
||||
wrpgpr $10, $25
|
||||
|
||||
# FPU (cp1) instructions
|
||||
#
|
||||
# Even registers are supported w/ 32-bit FPU, odd
|
||||
# registers supported only for 64-bit FPU.
|
||||
# Only the 32-bit FPU instructions are tested here.
|
||||
|
||||
mfhc1 $17, $f0
|
||||
mthc1 $17, $f0
|
||||
|
||||
# cp2 instructions
|
||||
|
||||
mfhc2 $17, 0x5555
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
#objdump: -dr --prefix-addresses
|
||||
#name: MIPS mips4 fp
|
||||
|
||||
# Test mips4 fp instructions.
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> bc1f 00000000+ <text_label>
|
||||
0+0004 <[^>]*> nop
|
||||
0+0008 <[^>]*> bc1f \$fcc1,00000000+ <text_label>
|
||||
0+000c <[^>]*> nop
|
||||
0+0010 <[^>]*> bc1fl \$fcc1,00000000+ <text_label>
|
||||
0+0014 <[^>]*> nop
|
||||
0+0018 <[^>]*> bc1t \$fcc1,00000000+ <text_label>
|
||||
0+001c <[^>]*> nop
|
||||
0+0020 <[^>]*> bc1tl \$fcc2,00000000+ <text_label>
|
||||
0+0024 <[^>]*> nop
|
||||
0+0028 <[^>]*> c.f.d \$f4,\$f6
|
||||
0+002c <[^>]*> c.f.d \$fcc1,\$f4,\$f6
|
||||
0+0030 <[^>]*> ldxc1 \$f2,a0\(a1\)
|
||||
0+0034 <[^>]*> lwxc1 \$f2,a0\(a1\)
|
||||
0+0038 <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6
|
||||
0+003c <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0
|
||||
0+0040 <[^>]*> movf a0,a1,\$fcc4
|
||||
0+0044 <[^>]*> movf.d \$f4,\$f6,\$fcc0
|
||||
0+0048 <[^>]*> movf.s \$f4,\$f6,\$fcc0
|
||||
0+004c <[^>]*> movn.d \$f4,\$f6,a2
|
||||
0+0050 <[^>]*> movn.s \$f4,\$f6,a2
|
||||
0+0054 <[^>]*> movt a0,a1,\$fcc4
|
||||
0+0058 <[^>]*> movt.d \$f4,\$f6,\$fcc0
|
||||
0+005c <[^>]*> movt.s \$f4,\$f6,\$fcc0
|
||||
0+0060 <[^>]*> movz.d \$f4,\$f6,a2
|
||||
0+0064 <[^>]*> movz.s \$f4,\$f6,a2
|
||||
0+0068 <[^>]*> msub.d \$f0,\$f2,\$f4,\$f6
|
||||
0+006c <[^>]*> msub.s \$f0,\$f2,\$f4,\$f6
|
||||
0+0070 <[^>]*> nmadd.d \$f0,\$f2,\$f4,\$f6
|
||||
0+0074 <[^>]*> nmadd.s \$f0,\$f2,\$f4,\$f6
|
||||
0+0078 <[^>]*> nmsub.d \$f0,\$f2,\$f4,\$f6
|
||||
0+007c <[^>]*> nmsub.s \$f0,\$f2,\$f4,\$f6
|
||||
0+0080 <[^>]*> prefx 0x4,a0\(a1\)
|
||||
0+0084 <[^>]*> recip.d \$f4,\$f6
|
||||
0+0088 <[^>]*> recip.s \$f4,\$f6
|
||||
0+008c <[^>]*> rsqrt.d \$f4,\$f6
|
||||
0+0090 <[^>]*> rsqrt.s \$f4,\$f6
|
||||
0+0094 <[^>]*> sdxc1 \$f4,a0\(a1\)
|
||||
0+0098 <[^>]*> swxc1 \$f4,a0\(a1\)
|
||||
...
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
|
||||
.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
|
||||
.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
|
||||
.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
|
||||
.*:8: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
|
||||
.*:9: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
|
||||
.*:10: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
|
||||
.*:11: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
|
||||
.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
|
||||
.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
|
||||
.*:15: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
|
||||
.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
|
||||
.*:17: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
|
||||
.*:18: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
|
||||
.*:19: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
|
||||
.*:20: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
|
||||
.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
|
||||
.*:22: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
|
||||
.*:23: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
|
||||
.*:24: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
|
||||
.*:25: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
|
||||
.*:26: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
|
||||
.*:27: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
|
||||
.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
|
||||
.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
|
||||
.*:30: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
|
||||
.*:31: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
|
||||
.*:33: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
|
||||
.*:34: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
|
||||
.*:35: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
|
||||
.*:36: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
|
||||
.*:37: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
|
||||
.*:38: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
|
||||
.*:39: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
# Source file used to test -mips4 fp instructions.
|
||||
|
||||
text_label:
|
||||
bc1f text_label
|
||||
bc1f $fcc1,text_label
|
||||
bc1fl $fcc1,text_label
|
||||
bc1t $fcc1,text_label
|
||||
bc1tl $fcc2,text_label
|
||||
c.f.d $f4,$f6
|
||||
c.f.d $fcc1,$f4,$f6
|
||||
ldxc1 $f2,$4($5)
|
||||
lwxc1 $f2,$4($5)
|
||||
madd.d $f0,$f2,$f4,$f6
|
||||
# This choice of arguments is so that it matches bc3f on pre-mips4.
|
||||
madd.s $f10,$f8,$f2,$f0
|
||||
movf $4,$5,$fcc4
|
||||
movf.d $f4,$f6,$fcc0
|
||||
movf.s $f4,$f6,$fcc0
|
||||
movn.d $f4,$f6,$6
|
||||
movn.s $f4,$f6,$6
|
||||
movt $4,$5,$fcc4
|
||||
movt.d $f4,$f6,$fcc0
|
||||
movt.s $f4,$f6,$fcc0
|
||||
movz.d $f4,$f6,$6
|
||||
movz.s $f4,$f6,$6
|
||||
msub.d $f0,$f2,$f4,$f6
|
||||
msub.s $f0,$f2,$f4,$f6
|
||||
nmadd.d $f0,$f2,$f4,$f6
|
||||
nmadd.s $f0,$f2,$f4,$f6
|
||||
nmsub.d $f0,$f2,$f4,$f6
|
||||
nmsub.s $f0,$f2,$f4,$f6
|
||||
# It used to be disabled due to a clash with lwc3.
|
||||
prefx 4,$4($5)
|
||||
recip.d $f4,$f6
|
||||
recip.s $f4,$f6
|
||||
rsqrt.d $f4,$f6
|
||||
rsqrt.s $f4,$f6
|
||||
sdxc1 $f4,$4($5)
|
||||
swxc1 $f4,$4($5)
|
||||
|
||||
# Round to a 16 byte boundary, for ease in testing multiple targets.
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
|
@ -1,51 +1,12 @@
|
|||
#objdump: -dr --prefix-addresses
|
||||
#name: MIPS mips4
|
||||
#name: MIPS mips4 non-fp
|
||||
|
||||
# Test the mips4 macros.
|
||||
# Test mips4 *non-fp* insturctions.
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> bc1f 00000000+ <text_label>
|
||||
0+0004 <[^>]*> nop
|
||||
0+0008 <[^>]*> bc1f \$fcc1,00000000+ <text_label>
|
||||
0+000c <[^>]*> nop
|
||||
0+0010 <[^>]*> bc1fl \$fcc1,00000000+ <text_label>
|
||||
0+0014 <[^>]*> nop
|
||||
0+0018 <[^>]*> bc1t \$fcc1,00000000+ <text_label>
|
||||
0+001c <[^>]*> nop
|
||||
0+0020 <[^>]*> bc1tl \$fcc2,00000000+ <text_label>
|
||||
0+0024 <[^>]*> nop
|
||||
0+0028 <[^>]*> c.f.d \$f4,\$f6
|
||||
0+002c <[^>]*> c.f.d \$fcc1,\$f4,\$f6
|
||||
0+0030 <[^>]*> ldxc1 \$f2,a0\(a1\)
|
||||
0+0034 <[^>]*> lwxc1 \$f2,a0\(a1\)
|
||||
0+0038 <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6
|
||||
0+003c <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0
|
||||
0+0040 <[^>]*> movf a0,a1,\$fcc4
|
||||
0+0044 <[^>]*> movf.d \$f4,\$f6,\$fcc0
|
||||
0+0048 <[^>]*> movf.s \$f4,\$f6,\$fcc0
|
||||
0+004c <[^>]*> movn a0,a2,a2
|
||||
0+0050 <[^>]*> movn.d \$f4,\$f6,a2
|
||||
0+0054 <[^>]*> movn.s \$f4,\$f6,a2
|
||||
0+0058 <[^>]*> movt a0,a1,\$fcc4
|
||||
0+005c <[^>]*> movt.d \$f4,\$f6,\$fcc0
|
||||
0+0060 <[^>]*> movt.s \$f4,\$f6,\$fcc0
|
||||
0+0064 <[^>]*> movz a0,a2,a2
|
||||
0+0068 <[^>]*> movz.d \$f4,\$f6,a2
|
||||
0+006c <[^>]*> movz.s \$f4,\$f6,a2
|
||||
0+0070 <[^>]*> msub.d \$f0,\$f2,\$f4,\$f6
|
||||
0+0074 <[^>]*> msub.s \$f0,\$f2,\$f4,\$f6
|
||||
0+0078 <[^>]*> nmadd.d \$f0,\$f2,\$f4,\$f6
|
||||
0+007c <[^>]*> nmadd.s \$f0,\$f2,\$f4,\$f6
|
||||
0+0080 <[^>]*> nmsub.d \$f0,\$f2,\$f4,\$f6
|
||||
0+0084 <[^>]*> nmsub.s \$f0,\$f2,\$f4,\$f6
|
||||
0+0088 <[^>]*> pref 0x4,0\(a0\)
|
||||
0+008c <[^>]*> prefx 0x4,a0\(a1\)
|
||||
0+0090 <[^>]*> recip.d \$f4,\$f6
|
||||
0+0094 <[^>]*> recip.s \$f4,\$f6
|
||||
0+0098 <[^>]*> rsqrt.d \$f4,\$f6
|
||||
0+009c <[^>]*> rsqrt.s \$f4,\$f6
|
||||
0+00a0 <[^>]*> sdxc1 \$f4,a0\(a1\)
|
||||
0+00a4 <[^>]*> swxc1 \$f4,a0\(a1\)
|
||||
0+0000 <[^>]*> movn a0,a2,a2
|
||||
0+0004 <[^>]*> movz a0,a2,a2
|
||||
0+0008 <[^>]*> pref 0x4,0\(a0\)
|
||||
...
|
||||
|
|
|
|||
|
|
@ -1,45 +1,10 @@
|
|||
# Source file used to test -mips4 instructions.
|
||||
# Source file used to test -mips4 *non-fp* instructions.
|
||||
|
||||
text_label:
|
||||
bc1f text_label
|
||||
bc1f $fcc1,text_label
|
||||
bc1fl $fcc1,text_label
|
||||
bc1t $fcc1,text_label
|
||||
bc1tl $fcc2,text_label
|
||||
c.f.d $f4,$f6
|
||||
c.f.d $fcc1,$f4,$f6
|
||||
ldxc1 $f2,$4($5)
|
||||
lwxc1 $f2,$4($5)
|
||||
madd.d $f0,$f2,$f4,$f6
|
||||
# This choice of arguments is so that it matches bc3f on pre-mips4.
|
||||
madd.s $f10,$f8,$f2,$f0
|
||||
movf $4,$5,$fcc4
|
||||
movf.d $f4,$f6,$fcc0
|
||||
movf.s $f4,$f6,$fcc0
|
||||
movn $4,$6,$6
|
||||
movn.d $f4,$f6,$6
|
||||
movn.s $f4,$f6,$6
|
||||
movt $4,$5,$fcc4
|
||||
movt.d $f4,$f6,$fcc0
|
||||
movt.s $f4,$f6,$fcc0
|
||||
movz $4,$6,$6
|
||||
movz.d $f4,$f6,$6
|
||||
movz.s $f4,$f6,$6
|
||||
msub.d $f0,$f2,$f4,$f6
|
||||
msub.s $f0,$f2,$f4,$f6
|
||||
nmadd.d $f0,$f2,$f4,$f6
|
||||
nmadd.s $f0,$f2,$f4,$f6
|
||||
nmsub.d $f0,$f2,$f4,$f6
|
||||
nmsub.s $f0,$f2,$f4,$f6
|
||||
# It used to be disabled due to a clash with lwc3.
|
||||
pref 4,0($4)
|
||||
prefx 4,$4($5)
|
||||
recip.d $f4,$f6
|
||||
recip.s $f4,$f6
|
||||
rsqrt.d $f4,$f6
|
||||
rsqrt.s $f4,$f6
|
||||
sdxc1 $f4,$4($5)
|
||||
swxc1 $f4,$4($5)
|
||||
|
||||
# Round to a 16 byte boundary, for ease in testing multiple targets.
|
||||
nop
|
||||
|
|
|
|||
Loading…
Reference in New Issue