* cris: New directory, simulator for Axis Communications CRIS
including CRIS v32, CGEN-based. * configure.ac: Add corresponding configury. * configure: Regenerate.
This commit is contained in:
Hans-Peter Nilsson
parent
97f669eda9
commit
f6bcefefe8
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@ -1,3 +1,10 @@
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2005-01-28 Hans-Peter Nilsson <hp@axis.com>
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* cris: New directory, simulator for Axis Communications CRIS
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including CRIS v32, CGEN-based.
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* configure.ac: Add corresponding configury.
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* configure: Regenerate.
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2005-01-17 Andrew Cagney <cagney@gnu.org>
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* configure.ac: For mips*-*-* and mn10300*-*-* configure the
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@ -273,6 +273,7 @@ PACKAGE_BUGREPORT=
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ac_unique_file="Makefile.in"
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ac_subdirs_all="$ac_subdirs_all arm"
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ac_subdirs_all="$ac_subdirs_all cris"
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ac_subdirs_all="$ac_subdirs_all d10v"
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ac_subdirs_all="$ac_subdirs_all frv"
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ac_subdirs_all="$ac_subdirs_all h8300"
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@ -3414,6 +3415,14 @@ if test "${enable_sim}" != no; then
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subdirs="$subdirs arm"
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testsuite=yes
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common=yes
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;;
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cris-*-* | crisv32-*-*)
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subdirs="$subdirs cris"
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testsuite=yes
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common=yes
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;;
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@ -50,6 +50,11 @@ if test "${enable_sim}" != no; then
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testsuite=yes
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common=yes
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;;
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cris-*-* | crisv32-*-*)
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AC_CONFIG_SUBDIRS(cris)
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testsuite=yes
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common=yes
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;;
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d10v-*-*)
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AC_CONFIG_SUBDIRS(d10v)
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;;
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@ -0,0 +1,164 @@
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# Makefile template for Configure for the CRIS simulator, based on a mix
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# of the ones for m32r and i960.
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#
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# Copyright (C) 2004, 2005 Free Software Foundation, Inc.
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# Contributed by Axis Communications.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License along
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# with this program; if not, write to the Free Software Foundation, Inc.,
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# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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## COMMON_PRE_CONFIG_FRAG
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CRISV10F_OBJS = crisv10f.o cpuv10.o decodev10.o semcrisv10f-switch.o modelv10.o mloopv10f.o
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CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o semcrisv32f-switch.o modelv32.o mloopv32f.o
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CONFIG_DEVICES = dv-sockser.o
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CONFIG_DEVICES =
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SIM_OBJS = \
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$(SIM_NEW_COMMON_OBJS) \
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sim-cpu.o \
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sim-hload.o \
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sim-hrw.o \
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sim-model.o \
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sim-reg.o \
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cgen-utils.o cgen-trace.o cgen-scache.o \
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cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
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sim-if.o arch.o \
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$(CRISV10F_OBJS) \
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$(CRISV32F_OBJS) \
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traps.o devices.o \
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$(CONFIG_DEVICES) \
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cris-desc.o
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# Extra headers included by sim-main.h.
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# FIXME: $(srccom)/cgen-ops.h should be in CGEN_INCLUDE_DEPS.
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SIM_EXTRA_DEPS = \
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$(CGEN_INCLUDE_DEPS) $(srccom)/cgen-ops.h \
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arch.h cpuall.h cris-sim.h cris-desc.h
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SIM_RUN_OBJS = nrun.o
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SIM_EXTRA_CLEAN = cris-clean
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# This selects the cris newlib/libgloss syscall definitions.
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NL_TARGET = -DNL_TARGET_cris
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## COMMON_POST_CONFIG_FRAG
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CGEN_CPU_DIR = $(CGENDIR)/../cpu
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arch = cris
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sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(sim-core_h) $(sim-options_h)
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arch.o: arch.c $(SIM_MAIN_DEPS)
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traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS) $(sim-options_h)
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devices.o: devices.c $(SIM_MAIN_DEPS)
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# CRISV10 objs
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CRISV10F_INCLUDE_DEPS = \
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$(CGEN_MAIN_CPU_DEPS) \
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cpuv10.h decodev10.h engv10.h
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crisv10f.o: crisv10f.c cris-tmpl.c $(CRISV10F_INCLUDE_DEPS)
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# FIXME: What is mono and what does "Use of `mono' is wip" mean (other
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# than the apparent; some "mono" feature is work in progress)?
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mloopv10f.c engv10.h: stamp-v10fmloop
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stamp-v10fmloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
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$(SHELL) $(srccom)/genmloop.sh \
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-mono -no-fast -pbb -switch semcrisv10f-switch.c \
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-cpu crisv10f -infile $(srcdir)/mloop.in
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$(SHELL) $(srcroot)/move-if-change eng.hin engv10.h
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$(SHELL) $(srcroot)/move-if-change mloop.cin mloopv10f.c
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touch stamp-v10fmloop
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mloopv10f.o: mloopv10f.c semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
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cpuv10.o: cpuv10.c $(CRISV10F_INCLUDE_DEPS)
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decodev10.o: decodev10.c $(CRISV10F_INCLUDE_DEPS)
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semcrisv10f-switch.o: semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
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modelv10.o: modelv10.c $(CRISV10F_INCLUDE_DEPS)
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# CRISV32 objs
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CRISV32F_INCLUDE_DEPS = \
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$(CGEN_MAIN_CPU_DEPS) \
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cpuv32.h decodev32.h engv32.h
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crisv32f.o: crisv32f.c cris-tmpl.c $(CRISV32F_INCLUDE_DEPS)
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# FIXME: What is mono and what does "Use of `mono' is wip" mean (other
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# than the apparent; some "mono" feature is work in progress)?
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mloopv32f.c engv32.h: stamp-v32fmloop
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stamp-v32fmloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
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$(SHELL) $(srccom)/genmloop.sh \
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-mono -no-fast -pbb -switch semcrisv32f-switch.c \
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-cpu crisv32f -infile $(srcdir)/mloop.in
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$(SHELL) $(srcroot)/move-if-change eng.hin engv32.h
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$(SHELL) $(srcroot)/move-if-change mloop.cin mloopv32f.c
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touch stamp-v32fmloop
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mloopv32f.o: mloopv32f.c semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
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cpuv32.o: cpuv32.c $(CRISV32F_INCLUDE_DEPS)
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decodev32.o: decodev32.c $(CRISV32F_INCLUDE_DEPS)
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semcrisv32f-switch.o: semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
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modelv32.o: modelv32.c $(CRISV32F_INCLUDE_DEPS)
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cris-clean:
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for v in 10 32; do \
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rm -f mloopv$${v}f.c engv$${v}.h stamp-v$${v}fmloop; \
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rm -f stamp-v$${v}fcpu; \
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done
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-rm -f stamp-arch stamp-desc
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-rm -f tmp-*
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# cgen support, enable with --enable-cgen-maint
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CGEN_MAINT = ; @true
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# The following line is commented in or out depending upon --enable-cgen-maint.
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@CGEN_MAINT@CGEN_MAINT =
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# Useful when making CGEN-generated files manually, without --enable-cgen-maint.
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stamps: stamp-v10fmloop stamp-v32fmloop stamp-arch stamp-v10fcpu stamp-v32fcpu stamp-desc
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stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
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$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=crisv10,crisv32 \
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archfile=$(CGEN_CPU_DIR)/cris.cpu \
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FLAGS="with-scache with-profile=fn"
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touch stamp-arch
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arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
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stamp-v10fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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archfile=$(CGEN_CPU_DIR)/cris.cpu \
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cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
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$(SHELL) $(srcroot)/move-if-change $(srcdir)/semv10-switch.c $(srcdir)/semcrisv10f-switch.c
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touch stamp-v10fcpu
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cpuv10.h cpuv10.c semcrisv10f-switch.c modelv10.c decodev10.c decodev10.h: $(CGEN_MAINT) stamp-v10fcpu
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stamp-v32fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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archfile=$(CGEN_CPU_DIR)/cris.cpu \
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cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
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$(SHELL) $(srcroot)/move-if-change $(srcdir)/semv32-switch.c $(srcdir)/semcrisv32f-switch.c
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touch stamp-v32fcpu
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cpuv32.h cpuv32.c semcrisv32f-switch.c modelv32.c decodev32.c decodev32.h: $(CGEN_MAINT) stamp-v32fcpu
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stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
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$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
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archfile=$(CGEN_CPU_DIR)/cris.cpu \
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cpu=cris mach=all
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touch stamp-desc
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cris-desc.c cris-desc.h cris-opc.h: $(CGEN_MAINT) stamp-desc
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@ -0,0 +1,38 @@
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/* Simulator support for cris.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2004 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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|
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "sim-main.h"
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#include "bfd.h"
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const MACH *sim_machs[] =
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{
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#ifdef HAVE_CPU_CRISV10F
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& crisv10_mach,
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#endif
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#ifdef HAVE_CPU_CRISV32F
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& crisv32_mach,
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#endif
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0
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};
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@ -0,0 +1,50 @@
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/* Simulator header for cris.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2004 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
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the Free Software Foundation; either version 2, or (at your option)
|
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any later version.
|
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|
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef CRIS_ARCH_H
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#define CRIS_ARCH_H
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#define TARGET_BIG_ENDIAN 1
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/* Enum declaration for model types. */
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typedef enum model_type {
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MODEL_CRISV10, MODEL_CRISV32, MODEL_MAX
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} MODEL_TYPE;
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#define MAX_MODELS ((int) MODEL_MAX)
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/* Enum declaration for unit types. */
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typedef enum unit_type {
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UNIT_NONE, UNIT_CRISV10_U_MOVEM, UNIT_CRISV10_U_MULTIPLY, UNIT_CRISV10_U_SKIP4
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, UNIT_CRISV10_U_STALL, UNIT_CRISV10_U_CONST32, UNIT_CRISV10_U_CONST16, UNIT_CRISV10_U_MEM
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, UNIT_CRISV10_U_EXEC, UNIT_CRISV32_U_EXEC_TO_SR, UNIT_CRISV32_U_EXEC_MOVEM, UNIT_CRISV32_U_EXEC
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, UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16, UNIT_CRISV32_U_JUMP
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, UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH, UNIT_CRISV32_U_MULTIPLY
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, UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W, UNIT_CRISV32_U_MEM_R
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, UNIT_CRISV32_U_MEM, UNIT_MAX
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} UNIT_TYPE;
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#define MAX_UNITS (4)
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#endif /* CRIS_ARCH_H */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,22 @@
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dnl Process this file with autoconf to produce a configure script.
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AC_PREREQ(2.59)dnl
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AC_INIT(Makefile.in)
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AC_CONFIG_HEADER(config.h:config.in)
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|
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sinclude(../common/aclocal.m4)
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||||
|
||||
# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
|
||||
# it by inlining the macro's contents.
|
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sinclude(../common/common.m4)
|
||||
|
||||
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
|
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SIM_AC_OPTION_HOSTENDIAN
|
||||
SIM_AC_OPTION_SCACHE(16384)
|
||||
|
||||
# The default model shouldn't matter as long as there's a BFD.
|
||||
SIM_AC_OPTION_DEFAULT_MODEL(crisv32)
|
||||
SIM_AC_OPTION_ENVIRONMENT
|
||||
SIM_AC_OPTION_INLINE()
|
||||
SIM_AC_OPTION_CGEN_MAINT
|
||||
|
||||
SIM_AC_OUTPUT
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/* Simulator CPU header for cris.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CRIS_CPUALL_H
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#define CRIS_CPUALL_H
|
||||
|
||||
/* Include files for each cpu family. */
|
||||
|
||||
#ifdef WANT_CPU_CRISV0F
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#include "engv0.h"
|
||||
#include "cgen-engine.h"
|
||||
#include "cpuv0.h"
|
||||
#include "decodev0.h"
|
||||
#endif
|
||||
|
||||
#ifdef WANT_CPU_CRISV3F
|
||||
#include "engv3.h"
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||||
#include "cgen-engine.h"
|
||||
#include "cpuv3.h"
|
||||
#include "decodev3.h"
|
||||
#endif
|
||||
|
||||
#ifdef WANT_CPU_CRISV8F
|
||||
#include "engv8.h"
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||||
#include "cgen-engine.h"
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||||
#include "cpuv8.h"
|
||||
#include "decodev8.h"
|
||||
#endif
|
||||
|
||||
#ifdef WANT_CPU_CRISV10F
|
||||
#include "engv10.h"
|
||||
#include "cgen-engine.h"
|
||||
#include "cpuv10.h"
|
||||
#include "decodev10.h"
|
||||
#endif
|
||||
|
||||
#ifdef WANT_CPU_CRISV32F
|
||||
#include "engv32.h"
|
||||
#include "cgen-engine.h"
|
||||
#include "cpuv32.h"
|
||||
#include "decodev32.h"
|
||||
#endif
|
||||
|
||||
extern const MACH crisv10_mach;
|
||||
extern const MACH crisv32_mach;
|
||||
|
||||
#ifndef WANT_CPU
|
||||
/* The ARGBUF struct. */
|
||||
struct argbuf {
|
||||
/* These are the baseclass definitions. */
|
||||
IADDR addr;
|
||||
const IDESC *idesc;
|
||||
char trace_p;
|
||||
char profile_p;
|
||||
/* ??? Temporary hack for skip insns. */
|
||||
char skip_count;
|
||||
char unused;
|
||||
/* cpu specific data follows */
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifndef WANT_CPU
|
||||
/* A cached insn.
|
||||
|
||||
??? SCACHE used to contain more than just argbuf. We could delete the
|
||||
type entirely and always just use ARGBUF, but for future concerns and as
|
||||
a level of abstraction it is left in. */
|
||||
|
||||
struct scache {
|
||||
struct argbuf argbuf;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* CRIS_CPUALL_H */
|
||||
|
|
@ -0,0 +1,501 @@
|
|||
/* Misc. support for CPU family crisv10f.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#define WANT_CPU crisv10f
|
||||
#define WANT_CPU_CRISV10F
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "cgen-ops.h"
|
||||
|
||||
/* Get the value of h-v32-non-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_v32_non_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_V32_NON_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-v32-non-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_v32_non_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_V32_NON_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-pc. */
|
||||
|
||||
USI
|
||||
crisv10f_h_pc_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_pc);
|
||||
}
|
||||
|
||||
/* Set a value for h-pc. */
|
||||
|
||||
void
|
||||
crisv10f_h_pc_set (SIM_CPU *current_cpu, USI newval)
|
||||
{
|
||||
SET_H_PC (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-gr. */
|
||||
|
||||
SI
|
||||
crisv10f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_GR (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-gr. */
|
||||
|
||||
void
|
||||
crisv10f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_GR (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-gr-pc. */
|
||||
|
||||
SI
|
||||
crisv10f_h_gr_pc_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_GR_PC (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-gr-pc. */
|
||||
|
||||
void
|
||||
crisv10f_h_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_GR_PC (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-gr-real-pc. */
|
||||
|
||||
SI
|
||||
crisv10f_h_gr_real_pc_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return CPU (h_gr_real_pc[regno]);
|
||||
}
|
||||
|
||||
/* Set a value for h-gr-real-pc. */
|
||||
|
||||
void
|
||||
crisv10f_h_gr_real_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
CPU (h_gr_real_pc[regno]) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-raw-gr-pc. */
|
||||
|
||||
SI
|
||||
crisv10f_h_raw_gr_pc_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_RAW_GR_PC (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-raw-gr-pc. */
|
||||
|
||||
void
|
||||
crisv10f_h_raw_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_RAW_GR_PC (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-sr. */
|
||||
|
||||
SI
|
||||
crisv10f_h_sr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_SR (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-sr. */
|
||||
|
||||
void
|
||||
crisv10f_h_sr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_SR (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-sr-v10. */
|
||||
|
||||
SI
|
||||
crisv10f_h_sr_v10_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_SR_V10 (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-sr-v10. */
|
||||
|
||||
void
|
||||
crisv10f_h_sr_v10_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_SR_V10 (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-cbit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_cbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_cbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-cbit. */
|
||||
|
||||
void
|
||||
crisv10f_h_cbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_cbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-cbit-move. */
|
||||
|
||||
BI
|
||||
crisv10f_h_cbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_CBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-cbit-move. */
|
||||
|
||||
void
|
||||
crisv10f_h_cbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_CBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-cbit-move-pre-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_CBIT_MOVE_PRE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-cbit-move-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_CBIT_MOVE_PRE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-vbit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_vbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_vbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-vbit. */
|
||||
|
||||
void
|
||||
crisv10f_h_vbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_vbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-vbit-move. */
|
||||
|
||||
BI
|
||||
crisv10f_h_vbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_VBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-vbit-move. */
|
||||
|
||||
void
|
||||
crisv10f_h_vbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_VBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-vbit-move-pre-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_VBIT_MOVE_PRE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-vbit-move-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_VBIT_MOVE_PRE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-zbit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_zbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_zbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-zbit. */
|
||||
|
||||
void
|
||||
crisv10f_h_zbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_zbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-zbit-move. */
|
||||
|
||||
BI
|
||||
crisv10f_h_zbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_ZBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-zbit-move. */
|
||||
|
||||
void
|
||||
crisv10f_h_zbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_ZBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-zbit-move-pre-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_ZBIT_MOVE_PRE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-zbit-move-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_ZBIT_MOVE_PRE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-nbit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_nbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_nbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-nbit. */
|
||||
|
||||
void
|
||||
crisv10f_h_nbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_nbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-nbit-move. */
|
||||
|
||||
BI
|
||||
crisv10f_h_nbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_NBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-nbit-move. */
|
||||
|
||||
void
|
||||
crisv10f_h_nbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_NBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-nbit-move-pre-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_NBIT_MOVE_PRE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-nbit-move-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_NBIT_MOVE_PRE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-xbit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_xbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_xbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-xbit. */
|
||||
|
||||
void
|
||||
crisv10f_h_xbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_xbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-ibit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_ibit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_IBIT ();
|
||||
}
|
||||
|
||||
/* Set a value for h-ibit. */
|
||||
|
||||
void
|
||||
crisv10f_h_ibit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_IBIT (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-ibit-pre-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_ibit_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_ibit_pre_v32);
|
||||
}
|
||||
|
||||
/* Set a value for h-ibit-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_ibit_pre_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_ibit_pre_v32) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-pbit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_pbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_pbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-pbit. */
|
||||
|
||||
void
|
||||
crisv10f_h_pbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_pbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-ubit. */
|
||||
|
||||
BI
|
||||
crisv10f_h_ubit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_UBIT ();
|
||||
}
|
||||
|
||||
/* Set a value for h-ubit. */
|
||||
|
||||
void
|
||||
crisv10f_h_ubit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_UBIT (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-ubit-pre-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_ubit_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_ubit_pre_v32);
|
||||
}
|
||||
|
||||
/* Set a value for h-ubit-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_ubit_pre_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_ubit_pre_v32) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-insn-prefixed-p. */
|
||||
|
||||
BI
|
||||
crisv10f_h_insn_prefixed_p_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_INSN_PREFIXED_P ();
|
||||
}
|
||||
|
||||
/* Set a value for h-insn-prefixed-p. */
|
||||
|
||||
void
|
||||
crisv10f_h_insn_prefixed_p_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_INSN_PREFIXED_P (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-insn-prefixed-p-pre-v32. */
|
||||
|
||||
BI
|
||||
crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_insn_prefixed_p_pre_v32);
|
||||
}
|
||||
|
||||
/* Set a value for h-insn-prefixed-p-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_insn_prefixed_p_pre_v32) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-prefixreg-pre-v32. */
|
||||
|
||||
SI
|
||||
crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_prefixreg_pre_v32);
|
||||
}
|
||||
|
||||
/* Set a value for h-prefixreg-pre-v32. */
|
||||
|
||||
void
|
||||
crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *current_cpu, SI newval)
|
||||
{
|
||||
CPU (h_prefixreg_pre_v32) = newval;
|
||||
}
|
||||
|
||||
/* Record trace results for INSN. */
|
||||
|
||||
void
|
||||
crisv10f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
|
||||
int *indices, TRACE_RECORD *tr)
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,597 @@
|
|||
/* Misc. support for CPU family crisv32f.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#define WANT_CPU crisv32f
|
||||
#define WANT_CPU_CRISV32F
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "cgen-ops.h"
|
||||
|
||||
/* Get the value of h-v32-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_v32_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_V32_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-v32-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_v32_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_V32_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-pc. */
|
||||
|
||||
USI
|
||||
crisv32f_h_pc_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_pc);
|
||||
}
|
||||
|
||||
/* Set a value for h-pc. */
|
||||
|
||||
void
|
||||
crisv32f_h_pc_set (SIM_CPU *current_cpu, USI newval)
|
||||
{
|
||||
SET_H_PC (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-gr. */
|
||||
|
||||
SI
|
||||
crisv32f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_GR (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-gr. */
|
||||
|
||||
void
|
||||
crisv32f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_GR (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-gr-acr. */
|
||||
|
||||
SI
|
||||
crisv32f_h_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return CPU (h_gr_acr[regno]);
|
||||
}
|
||||
|
||||
/* Set a value for h-gr-acr. */
|
||||
|
||||
void
|
||||
crisv32f_h_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
CPU (h_gr_acr[regno]) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-raw-gr-acr. */
|
||||
|
||||
SI
|
||||
crisv32f_h_raw_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_RAW_GR_ACR (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-raw-gr-acr. */
|
||||
|
||||
void
|
||||
crisv32f_h_raw_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_RAW_GR_ACR (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-sr. */
|
||||
|
||||
SI
|
||||
crisv32f_h_sr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_SR (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-sr. */
|
||||
|
||||
void
|
||||
crisv32f_h_sr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_SR (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-sr-v32. */
|
||||
|
||||
SI
|
||||
crisv32f_h_sr_v32_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_SR_V32 (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-sr-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_sr_v32_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_SR_V32 (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-supr. */
|
||||
|
||||
SI
|
||||
crisv32f_h_supr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return GET_H_SUPR (regno);
|
||||
}
|
||||
|
||||
/* Set a value for h-supr. */
|
||||
|
||||
void
|
||||
crisv32f_h_supr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
|
||||
{
|
||||
SET_H_SUPR (regno, newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-cbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_cbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_cbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-cbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_cbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_cbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-cbit-move. */
|
||||
|
||||
BI
|
||||
crisv32f_h_cbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_CBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-cbit-move. */
|
||||
|
||||
void
|
||||
crisv32f_h_cbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_CBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-cbit-move-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_cbit_move_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_CBIT_MOVE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-cbit-move-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_cbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_CBIT_MOVE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-vbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_vbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_vbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-vbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_vbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_vbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-vbit-move. */
|
||||
|
||||
BI
|
||||
crisv32f_h_vbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_VBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-vbit-move. */
|
||||
|
||||
void
|
||||
crisv32f_h_vbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_VBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-vbit-move-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_vbit_move_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_VBIT_MOVE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-vbit-move-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_vbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_VBIT_MOVE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-zbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_zbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_zbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-zbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_zbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_zbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-zbit-move. */
|
||||
|
||||
BI
|
||||
crisv32f_h_zbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_ZBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-zbit-move. */
|
||||
|
||||
void
|
||||
crisv32f_h_zbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_ZBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-zbit-move-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_zbit_move_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_ZBIT_MOVE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-zbit-move-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_zbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_ZBIT_MOVE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-nbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_nbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_nbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-nbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_nbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_nbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-nbit-move. */
|
||||
|
||||
BI
|
||||
crisv32f_h_nbit_move_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_NBIT_MOVE ();
|
||||
}
|
||||
|
||||
/* Set a value for h-nbit-move. */
|
||||
|
||||
void
|
||||
crisv32f_h_nbit_move_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_NBIT_MOVE (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-nbit-move-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_nbit_move_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_NBIT_MOVE_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-nbit-move-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_nbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_NBIT_MOVE_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-xbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_xbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_xbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-xbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_xbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_xbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-ibit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_ibit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_IBIT ();
|
||||
}
|
||||
|
||||
/* Set a value for h-ibit. */
|
||||
|
||||
void
|
||||
crisv32f_h_ibit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_IBIT (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-pbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_pbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_pbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-pbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_pbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_pbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-rbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_rbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_rbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-rbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_rbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_rbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-ubit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_ubit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_UBIT ();
|
||||
}
|
||||
|
||||
/* Set a value for h-ubit. */
|
||||
|
||||
void
|
||||
crisv32f_h_ubit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_UBIT (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-gbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_gbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_gbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-gbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_gbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
CPU (h_gbit) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-kernel-sp. */
|
||||
|
||||
SI
|
||||
crisv32f_h_kernel_sp_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_kernel_sp);
|
||||
}
|
||||
|
||||
/* Set a value for h-kernel-sp. */
|
||||
|
||||
void
|
||||
crisv32f_h_kernel_sp_set (SIM_CPU *current_cpu, SI newval)
|
||||
{
|
||||
CPU (h_kernel_sp) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-ubit-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_ubit_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_ubit_v32);
|
||||
}
|
||||
|
||||
/* Set a value for h-ubit-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_ubit_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_UBIT_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-ibit-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_ibit_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_ibit_v32);
|
||||
}
|
||||
|
||||
/* Set a value for h-ibit-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_ibit_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_IBIT_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-mbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_mbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_mbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-mbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_mbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_MBIT (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-qbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_qbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_qbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-qbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_qbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_QBIT (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-sbit. */
|
||||
|
||||
BI
|
||||
crisv32f_h_sbit_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return CPU (h_sbit);
|
||||
}
|
||||
|
||||
/* Set a value for h-sbit. */
|
||||
|
||||
void
|
||||
crisv32f_h_sbit_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_SBIT (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-insn-prefixed-p. */
|
||||
|
||||
BI
|
||||
crisv32f_h_insn_prefixed_p_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_INSN_PREFIXED_P ();
|
||||
}
|
||||
|
||||
/* Set a value for h-insn-prefixed-p. */
|
||||
|
||||
void
|
||||
crisv32f_h_insn_prefixed_p_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_INSN_PREFIXED_P (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-insn-prefixed-p-v32. */
|
||||
|
||||
BI
|
||||
crisv32f_h_insn_prefixed_p_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_INSN_PREFIXED_P_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-insn-prefixed-p-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_insn_prefixed_p_v32_set (SIM_CPU *current_cpu, BI newval)
|
||||
{
|
||||
SET_H_INSN_PREFIXED_P_V32 (newval);
|
||||
}
|
||||
|
||||
/* Get the value of h-prefixreg-v32. */
|
||||
|
||||
SI
|
||||
crisv32f_h_prefixreg_v32_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_PREFIXREG_V32 ();
|
||||
}
|
||||
|
||||
/* Set a value for h-prefixreg-v32. */
|
||||
|
||||
void
|
||||
crisv32f_h_prefixreg_v32_set (SIM_CPU *current_cpu, SI newval)
|
||||
{
|
||||
SET_H_PREFIXREG_V32 (newval);
|
||||
}
|
||||
|
||||
/* Record trace results for INSN. */
|
||||
|
||||
void
|
||||
crisv32f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
|
||||
int *indices, TRACE_RECORD *tr)
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,355 @@
|
|||
/* CPU data header for cris.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CRIS_CPU_H
|
||||
#define CRIS_CPU_H
|
||||
|
||||
#define CGEN_ARCH cris
|
||||
|
||||
/* Given symbol S, return cris_cgen_<S>. */
|
||||
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
|
||||
#define CGEN_SYM(s) cris##_cgen_##s
|
||||
#else
|
||||
#define CGEN_SYM(s) cris/**/_cgen_/**/s
|
||||
#endif
|
||||
|
||||
|
||||
/* Selected cpu families. */
|
||||
#define HAVE_CPU_CRISV0F
|
||||
#define HAVE_CPU_CRISV3F
|
||||
#define HAVE_CPU_CRISV8F
|
||||
#define HAVE_CPU_CRISV10F
|
||||
#define HAVE_CPU_CRISV32F
|
||||
|
||||
#define CGEN_INSN_LSB0_P 1
|
||||
|
||||
/* Minimum size of any insn (in bytes). */
|
||||
#define CGEN_MIN_INSN_SIZE 2
|
||||
|
||||
/* Maximum size of any insn (in bytes). */
|
||||
#define CGEN_MAX_INSN_SIZE 6
|
||||
|
||||
#define CGEN_INT_INSN_P 0
|
||||
|
||||
/* Maximum number of syntax elements in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
|
||||
|
||||
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
|
||||
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
|
||||
we can't hash on everything up to the space. */
|
||||
#define CGEN_MNEMONIC_OPERANDS
|
||||
|
||||
/* Maximum number of fields in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6
|
||||
|
||||
/* Enums. */
|
||||
|
||||
/* Enum declaration for . */
|
||||
typedef enum gr_names_pcreg {
|
||||
H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1
|
||||
, H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5
|
||||
, H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9
|
||||
, H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13
|
||||
, H_GR_REAL_PC_R14 = 14
|
||||
} GR_NAMES_PCREG;
|
||||
|
||||
/* Enum declaration for . */
|
||||
typedef enum gr_names_acr {
|
||||
H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1
|
||||
, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
|
||||
, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
|
||||
, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
|
||||
, H_GR_R14 = 14
|
||||
} GR_NAMES_ACR;
|
||||
|
||||
/* Enum declaration for . */
|
||||
typedef enum gr_names_v32 {
|
||||
H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1
|
||||
, H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5
|
||||
, H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9
|
||||
, H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13
|
||||
, H_GR_V32_R14 = 14
|
||||
} GR_NAMES_V32;
|
||||
|
||||
/* Enum declaration for . */
|
||||
typedef enum p_names_v10 {
|
||||
H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10
|
||||
, H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15
|
||||
, H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1
|
||||
, H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5
|
||||
, H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9
|
||||
, H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13
|
||||
, H_SR_PRE_V32_P14 = 14
|
||||
} P_NAMES_V10;
|
||||
|
||||
/* Enum declaration for . */
|
||||
typedef enum p_names_v32 {
|
||||
H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4
|
||||
, H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8
|
||||
, H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13
|
||||
, H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11
|
||||
, H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3
|
||||
, H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7
|
||||
, H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11
|
||||
, H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14
|
||||
} P_NAMES_V32;
|
||||
|
||||
/* Enum declaration for . */
|
||||
typedef enum p_names_v32_x {
|
||||
H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4
|
||||
, H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8
|
||||
, H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13
|
||||
, H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11
|
||||
, H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3
|
||||
, H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7
|
||||
, H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11
|
||||
, H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14
|
||||
} P_NAMES_V32_X;
|
||||
|
||||
/* Enum declaration for Standard instruction operand size. */
|
||||
typedef enum insn_size {
|
||||
SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED
|
||||
} INSN_SIZE;
|
||||
|
||||
/* Enum declaration for Standard instruction addressing modes. */
|
||||
typedef enum insn_mode {
|
||||
MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT
|
||||
} INSN_MODE;
|
||||
|
||||
/* Enum declaration for Whether the operand is indirect. */
|
||||
typedef enum insn_memoryness_mode {
|
||||
MODEMEMP_NO, MODEMEMP_YES
|
||||
} INSN_MEMORYNESS_MODE;
|
||||
|
||||
/* Enum declaration for Whether the indirect operand is autoincrement. */
|
||||
typedef enum insn_memincness_mode {
|
||||
MODEINCP_NO, MODEINCP_YES
|
||||
} INSN_MEMINCNESS_MODE;
|
||||
|
||||
/* Enum declaration for Signed instruction operand size. */
|
||||
typedef enum insn_signed_size {
|
||||
SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD
|
||||
} INSN_SIGNED_SIZE;
|
||||
|
||||
/* Enum declaration for Unsigned instruction operand size. */
|
||||
typedef enum insn_unsigned_size {
|
||||
UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3
|
||||
} INSN_UNSIGNED_SIZE;
|
||||
|
||||
/* Enum declaration for Insns for MODE_QUICK_IMMEDIATE. */
|
||||
typedef enum insn_qi_opc {
|
||||
Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3
|
||||
, Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3
|
||||
, Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ
|
||||
, Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ
|
||||
} INSN_QI_OPC;
|
||||
|
||||
/* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode. */
|
||||
typedef enum insn_qihi_opc {
|
||||
QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3
|
||||
} INSN_QIHI_OPC;
|
||||
|
||||
/* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */
|
||||
typedef enum insn_r_opc {
|
||||
R_ADDX, R_MOVX, R_SUBX, R_LSL
|
||||
, R_ADDI, R_BIAP, R_NEG, R_BOUND
|
||||
, R_ADD, R_MOVE, R_SUB, R_CMP
|
||||
, R_AND, R_OR, R_ASR, R_LSR
|
||||
} INSN_R_OPC;
|
||||
|
||||
/* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED. */
|
||||
typedef enum insn_rfix_opc {
|
||||
RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST
|
||||
, RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF
|
||||
, RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP
|
||||
, RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP
|
||||
} INSN_RFIX_OPC;
|
||||
|
||||
/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */
|
||||
typedef enum insn_indir_opc {
|
||||
INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX
|
||||
, INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND
|
||||
, INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP
|
||||
, INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M
|
||||
} INSN_INDIR_OPC;
|
||||
|
||||
/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED. */
|
||||
typedef enum insn_infix_opc {
|
||||
INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX
|
||||
, INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M
|
||||
, INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE
|
||||
, INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M
|
||||
} INSN_INFIX_OPC;
|
||||
|
||||
/* Attributes. */
|
||||
|
||||
/* Enum declaration for machine type selection. */
|
||||
typedef enum mach_attr {
|
||||
MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8
|
||||
, MACH_CRISV10, MACH_CRISV32, MACH_MAX
|
||||
} MACH_ATTR;
|
||||
|
||||
/* Enum declaration for instruction set selection. */
|
||||
typedef enum isa_attr {
|
||||
ISA_CRIS, ISA_MAX
|
||||
} ISA_ATTR;
|
||||
|
||||
/* Number of architecture variants. */
|
||||
#define MAX_ISAS 1
|
||||
#define MAX_MACHS ((int) MACH_MAX)
|
||||
|
||||
/* Ifield support. */
|
||||
|
||||
extern const struct cgen_ifld cris_cgen_ifld_table[];
|
||||
|
||||
/* Ifield attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_ifld attrs. */
|
||||
typedef enum cgen_ifld_attr {
|
||||
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
|
||||
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
|
||||
, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
|
||||
} CGEN_IFLD_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_ifld_attr. */
|
||||
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
|
||||
|
||||
/* Enum declaration for cris ifield types. */
|
||||
typedef enum ifield_type {
|
||||
CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE
|
||||
, CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE
|
||||
, CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC
|
||||
, CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4
|
||||
, CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9
|
||||
, CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL
|
||||
, CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX
|
||||
} IFIELD_TYPE;
|
||||
|
||||
#define MAX_IFLD ((int) CRIS_F_MAX)
|
||||
|
||||
/* Hardware attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_hw attrs. */
|
||||
typedef enum cgen_hw_attr {
|
||||
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
|
||||
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
|
||||
} CGEN_HW_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_hw_attr. */
|
||||
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
|
||||
|
||||
/* Enum declaration for cris hardware types. */
|
||||
typedef enum cgen_hw_type {
|
||||
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
|
||||
, HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP
|
||||
, HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR
|
||||
, HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR
|
||||
, HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE
|
||||
, HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X
|
||||
, HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT
|
||||
, HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT
|
||||
, HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT
|
||||
, HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT
|
||||
, HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X
|
||||
, HW_H_PREFIXREG, HW_MAX
|
||||
} CGEN_HW_TYPE;
|
||||
|
||||
#define MAX_HW ((int) HW_MAX)
|
||||
|
||||
/* Operand attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_operand attrs. */
|
||||
typedef enum cgen_operand_attr {
|
||||
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
|
||||
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
|
||||
, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
|
||||
} CGEN_OPERAND_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_operand_attr. */
|
||||
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
|
||||
|
||||
/* Enum declaration for cris operand types. */
|
||||
typedef enum cgen_operand_type {
|
||||
CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT
|
||||
, CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT
|
||||
, CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT
|
||||
, CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT
|
||||
, CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS
|
||||
, CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD
|
||||
, CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO
|
||||
, CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16
|
||||
, CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD
|
||||
, CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC
|
||||
, CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX
|
||||
} CGEN_OPERAND_TYPE;
|
||||
|
||||
/* Number of operands types. */
|
||||
#define MAX_OPERANDS 43
|
||||
|
||||
/* Maximum number of operands referenced by any insn. */
|
||||
#define MAX_OPERAND_INSTANCES 8
|
||||
|
||||
/* Insn attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_insn attrs. */
|
||||
typedef enum cgen_insn_attr {
|
||||
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
|
||||
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
|
||||
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
|
||||
, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
|
||||
} CGEN_INSN_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_insn_attr. */
|
||||
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
|
||||
|
||||
/* cgen.h uses things we just defined. */
|
||||
#include "opcode/cgen.h"
|
||||
|
||||
/* Attributes. */
|
||||
extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[];
|
||||
|
||||
/* Hardware decls. */
|
||||
|
||||
extern CGEN_KEYWORD cris_cgen_opval_h_inc;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_h_ccode;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_h_swap;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_h_flagbits;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_p_names_v32;
|
||||
extern CGEN_KEYWORD cris_cgen_opval_h_supr;
|
||||
|
||||
extern const CGEN_HW_ENTRY cris_cgen_hw_table[];
|
||||
|
||||
|
||||
|
||||
#endif /* CRIS_CPU_H */
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/* Instruction opcode header for cris.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CRIS_OPC_H
|
||||
#define CRIS_OPC_H
|
||||
|
||||
/* Enum declaration for cris instruction types. */
|
||||
typedef enum cgen_insn_type {
|
||||
CRIS_INSN_INVALID, CRIS_INSN_NOP, CRIS_INSN_MOVE_B_R, CRIS_INSN_MOVE_W_R
|
||||
, CRIS_INSN_MOVE_D_R, CRIS_INSN_MOVEPCR, CRIS_INSN_MOVEQ, CRIS_INSN_MOVS_B_R
|
||||
, CRIS_INSN_MOVS_W_R, CRIS_INSN_MOVU_B_R, CRIS_INSN_MOVU_W_R, CRIS_INSN_MOVECBR
|
||||
, CRIS_INSN_MOVECWR, CRIS_INSN_MOVECDR, CRIS_INSN_MOVSCBR, CRIS_INSN_MOVSCWR
|
||||
, CRIS_INSN_MOVUCBR, CRIS_INSN_MOVUCWR, CRIS_INSN_ADDQ, CRIS_INSN_SUBQ
|
||||
, CRIS_INSN_CMP_R_B_R, CRIS_INSN_CMP_R_W_R, CRIS_INSN_CMP_R_D_R, CRIS_INSN_CMP_M_B_M
|
||||
, CRIS_INSN_CMP_M_W_M, CRIS_INSN_CMP_M_D_M, CRIS_INSN_CMPCBR, CRIS_INSN_CMPCWR
|
||||
, CRIS_INSN_CMPCDR, CRIS_INSN_CMPQ, CRIS_INSN_CMPS_M_B_M, CRIS_INSN_CMPS_M_W_M
|
||||
, CRIS_INSN_CMPSCBR, CRIS_INSN_CMPSCWR, CRIS_INSN_CMPU_M_B_M, CRIS_INSN_CMPU_M_W_M
|
||||
, CRIS_INSN_CMPUCBR, CRIS_INSN_CMPUCWR, CRIS_INSN_MOVE_M_B_M, CRIS_INSN_MOVE_M_W_M
|
||||
, CRIS_INSN_MOVE_M_D_M, CRIS_INSN_MOVS_M_B_M, CRIS_INSN_MOVS_M_W_M, CRIS_INSN_MOVU_M_B_M
|
||||
, CRIS_INSN_MOVU_M_W_M, CRIS_INSN_MOVE_R_SPRV0, CRIS_INSN_MOVE_R_SPRV3, CRIS_INSN_MOVE_R_SPRV8
|
||||
, CRIS_INSN_MOVE_R_SPRV10, CRIS_INSN_MOVE_R_SPRV32, CRIS_INSN_MOVE_SPR_RV0, CRIS_INSN_MOVE_SPR_RV3
|
||||
, CRIS_INSN_MOVE_SPR_RV8, CRIS_INSN_MOVE_SPR_RV10, CRIS_INSN_MOVE_SPR_RV32, CRIS_INSN_RET_TYPE
|
||||
, CRIS_INSN_MOVE_M_SPRV0, CRIS_INSN_MOVE_M_SPRV3, CRIS_INSN_MOVE_M_SPRV8, CRIS_INSN_MOVE_M_SPRV10
|
||||
, CRIS_INSN_MOVE_M_SPRV32, CRIS_INSN_MOVE_C_SPRV0_P0, CRIS_INSN_MOVE_C_SPRV0_P1, CRIS_INSN_MOVE_C_SPRV0_P4
|
||||
, CRIS_INSN_MOVE_C_SPRV0_P5, CRIS_INSN_MOVE_C_SPRV0_P8, CRIS_INSN_MOVE_C_SPRV0_P9, CRIS_INSN_MOVE_C_SPRV0_P10
|
||||
, CRIS_INSN_MOVE_C_SPRV0_P11, CRIS_INSN_MOVE_C_SPRV0_P12, CRIS_INSN_MOVE_C_SPRV0_P13, CRIS_INSN_MOVE_C_SPRV0_P6
|
||||
, CRIS_INSN_MOVE_C_SPRV0_P7, CRIS_INSN_MOVE_C_SPRV3_P0, CRIS_INSN_MOVE_C_SPRV3_P1, CRIS_INSN_MOVE_C_SPRV3_P4
|
||||
, CRIS_INSN_MOVE_C_SPRV3_P5, CRIS_INSN_MOVE_C_SPRV3_P8, CRIS_INSN_MOVE_C_SPRV3_P9, CRIS_INSN_MOVE_C_SPRV3_P10
|
||||
, CRIS_INSN_MOVE_C_SPRV3_P11, CRIS_INSN_MOVE_C_SPRV3_P12, CRIS_INSN_MOVE_C_SPRV3_P13, CRIS_INSN_MOVE_C_SPRV3_P6
|
||||
, CRIS_INSN_MOVE_C_SPRV3_P7, CRIS_INSN_MOVE_C_SPRV3_P14, CRIS_INSN_MOVE_C_SPRV8_P0, CRIS_INSN_MOVE_C_SPRV8_P1
|
||||
, CRIS_INSN_MOVE_C_SPRV8_P4, CRIS_INSN_MOVE_C_SPRV8_P5, CRIS_INSN_MOVE_C_SPRV8_P8, CRIS_INSN_MOVE_C_SPRV8_P9
|
||||
, CRIS_INSN_MOVE_C_SPRV8_P10, CRIS_INSN_MOVE_C_SPRV8_P11, CRIS_INSN_MOVE_C_SPRV8_P12, CRIS_INSN_MOVE_C_SPRV8_P13
|
||||
, CRIS_INSN_MOVE_C_SPRV8_P14, CRIS_INSN_MOVE_C_SPRV10_P0, CRIS_INSN_MOVE_C_SPRV10_P1, CRIS_INSN_MOVE_C_SPRV10_P4
|
||||
, CRIS_INSN_MOVE_C_SPRV10_P5, CRIS_INSN_MOVE_C_SPRV10_P8, CRIS_INSN_MOVE_C_SPRV10_P9, CRIS_INSN_MOVE_C_SPRV10_P10
|
||||
, CRIS_INSN_MOVE_C_SPRV10_P11, CRIS_INSN_MOVE_C_SPRV10_P12, CRIS_INSN_MOVE_C_SPRV10_P13, CRIS_INSN_MOVE_C_SPRV10_P7
|
||||
, CRIS_INSN_MOVE_C_SPRV10_P14, CRIS_INSN_MOVE_C_SPRV10_P15, CRIS_INSN_MOVE_C_SPRV32_P0, CRIS_INSN_MOVE_C_SPRV32_P1
|
||||
, CRIS_INSN_MOVE_C_SPRV32_P2, CRIS_INSN_MOVE_C_SPRV32_P3, CRIS_INSN_MOVE_C_SPRV32_P4, CRIS_INSN_MOVE_C_SPRV32_P5
|
||||
, CRIS_INSN_MOVE_C_SPRV32_P6, CRIS_INSN_MOVE_C_SPRV32_P7, CRIS_INSN_MOVE_C_SPRV32_P8, CRIS_INSN_MOVE_C_SPRV32_P9
|
||||
, CRIS_INSN_MOVE_C_SPRV32_P10, CRIS_INSN_MOVE_C_SPRV32_P11, CRIS_INSN_MOVE_C_SPRV32_P12, CRIS_INSN_MOVE_C_SPRV32_P13
|
||||
, CRIS_INSN_MOVE_C_SPRV32_P14, CRIS_INSN_MOVE_C_SPRV32_P15, CRIS_INSN_MOVE_SPR_MV0, CRIS_INSN_MOVE_SPR_MV3
|
||||
, CRIS_INSN_MOVE_SPR_MV8, CRIS_INSN_MOVE_SPR_MV10, CRIS_INSN_MOVE_SPR_MV32, CRIS_INSN_SBFS
|
||||
, CRIS_INSN_MOVE_SS_R, CRIS_INSN_MOVE_R_SS, CRIS_INSN_MOVEM_R_M, CRIS_INSN_MOVEM_R_M_V32
|
||||
, CRIS_INSN_MOVEM_M_R, CRIS_INSN_MOVEM_M_PC, CRIS_INSN_MOVEM_M_R_V32, CRIS_INSN_ADD_B_R
|
||||
, CRIS_INSN_ADD_W_R, CRIS_INSN_ADD_D_R, CRIS_INSN_ADD_M_B_M, CRIS_INSN_ADD_M_W_M
|
||||
, CRIS_INSN_ADD_M_D_M, CRIS_INSN_ADDCBR, CRIS_INSN_ADDCWR, CRIS_INSN_ADDCDR
|
||||
, CRIS_INSN_ADDCPC, CRIS_INSN_ADDS_B_R, CRIS_INSN_ADDS_W_R, CRIS_INSN_ADDS_M_B_M
|
||||
, CRIS_INSN_ADDS_M_W_M, CRIS_INSN_ADDSCBR, CRIS_INSN_ADDSCWR, CRIS_INSN_ADDSPCPC
|
||||
, CRIS_INSN_ADDU_B_R, CRIS_INSN_ADDU_W_R, CRIS_INSN_ADDU_M_B_M, CRIS_INSN_ADDU_M_W_M
|
||||
, CRIS_INSN_ADDUCBR, CRIS_INSN_ADDUCWR, CRIS_INSN_SUB_B_R, CRIS_INSN_SUB_W_R
|
||||
, CRIS_INSN_SUB_D_R, CRIS_INSN_SUB_M_B_M, CRIS_INSN_SUB_M_W_M, CRIS_INSN_SUB_M_D_M
|
||||
, CRIS_INSN_SUBCBR, CRIS_INSN_SUBCWR, CRIS_INSN_SUBCDR, CRIS_INSN_SUBS_B_R
|
||||
, CRIS_INSN_SUBS_W_R, CRIS_INSN_SUBS_M_B_M, CRIS_INSN_SUBS_M_W_M, CRIS_INSN_SUBSCBR
|
||||
, CRIS_INSN_SUBSCWR, CRIS_INSN_SUBU_B_R, CRIS_INSN_SUBU_W_R, CRIS_INSN_SUBU_M_B_M
|
||||
, CRIS_INSN_SUBU_M_W_M, CRIS_INSN_SUBUCBR, CRIS_INSN_SUBUCWR, CRIS_INSN_ADDC_R
|
||||
, CRIS_INSN_ADDC_M, CRIS_INSN_ADDC_C, CRIS_INSN_LAPC_D, CRIS_INSN_LAPCQ
|
||||
, CRIS_INSN_ADDI_B_R, CRIS_INSN_ADDI_W_R, CRIS_INSN_ADDI_D_R, CRIS_INSN_NEG_B_R
|
||||
, CRIS_INSN_NEG_W_R, CRIS_INSN_NEG_D_R, CRIS_INSN_TEST_M_B_M, CRIS_INSN_TEST_M_W_M
|
||||
, CRIS_INSN_TEST_M_D_M, CRIS_INSN_MOVE_R_M_B_M, CRIS_INSN_MOVE_R_M_W_M, CRIS_INSN_MOVE_R_M_D_M
|
||||
, CRIS_INSN_MULS_B, CRIS_INSN_MULS_W, CRIS_INSN_MULS_D, CRIS_INSN_MULU_B
|
||||
, CRIS_INSN_MULU_W, CRIS_INSN_MULU_D, CRIS_INSN_MCP, CRIS_INSN_MSTEP
|
||||
, CRIS_INSN_DSTEP, CRIS_INSN_ABS, CRIS_INSN_AND_B_R, CRIS_INSN_AND_W_R
|
||||
, CRIS_INSN_AND_D_R, CRIS_INSN_AND_M_B_M, CRIS_INSN_AND_M_W_M, CRIS_INSN_AND_M_D_M
|
||||
, CRIS_INSN_ANDCBR, CRIS_INSN_ANDCWR, CRIS_INSN_ANDCDR, CRIS_INSN_ANDQ
|
||||
, CRIS_INSN_ORR_B_R, CRIS_INSN_ORR_W_R, CRIS_INSN_ORR_D_R, CRIS_INSN_OR_M_B_M
|
||||
, CRIS_INSN_OR_M_W_M, CRIS_INSN_OR_M_D_M, CRIS_INSN_ORCBR, CRIS_INSN_ORCWR
|
||||
, CRIS_INSN_ORCDR, CRIS_INSN_ORQ, CRIS_INSN_XOR, CRIS_INSN_NOT
|
||||
, CRIS_INSN_SWAP, CRIS_INSN_ASRR_B_R, CRIS_INSN_ASRR_W_R, CRIS_INSN_ASRR_D_R
|
||||
, CRIS_INSN_ASRQ, CRIS_INSN_LSRR_B_R, CRIS_INSN_LSRR_W_R, CRIS_INSN_LSRR_D_R
|
||||
, CRIS_INSN_LSRQ, CRIS_INSN_LSLR_B_R, CRIS_INSN_LSLR_W_R, CRIS_INSN_LSLR_D_R
|
||||
, CRIS_INSN_LSLQ, CRIS_INSN_BTST, CRIS_INSN_BTSTQ, CRIS_INSN_SETF
|
||||
, CRIS_INSN_CLEARF, CRIS_INSN_RFE, CRIS_INSN_SFE, CRIS_INSN_RFG
|
||||
, CRIS_INSN_RFN, CRIS_INSN_HALT, CRIS_INSN_BCC_B, CRIS_INSN_BA_B
|
||||
, CRIS_INSN_BCC_W, CRIS_INSN_BA_W, CRIS_INSN_JAS_R, CRIS_INSN_JUMP_R
|
||||
, CRIS_INSN_JAS_C, CRIS_INSN_JUMP_M, CRIS_INSN_JUMP_C, CRIS_INSN_JUMP_P
|
||||
, CRIS_INSN_BAS_C, CRIS_INSN_JASC_R, CRIS_INSN_JASC_C, CRIS_INSN_BASC_C
|
||||
, CRIS_INSN_BREAK, CRIS_INSN_BOUND_R_B_R, CRIS_INSN_BOUND_R_W_R, CRIS_INSN_BOUND_R_D_R
|
||||
, CRIS_INSN_BOUND_M_B_M, CRIS_INSN_BOUND_M_W_M, CRIS_INSN_BOUND_M_D_M, CRIS_INSN_BOUND_CB
|
||||
, CRIS_INSN_BOUND_CW, CRIS_INSN_BOUND_CD, CRIS_INSN_SCC, CRIS_INSN_LZ
|
||||
, CRIS_INSN_ADDOQ, CRIS_INSN_BDAPQPC, CRIS_INSN_ADDO_M_B_M, CRIS_INSN_ADDO_M_W_M
|
||||
, CRIS_INSN_ADDO_M_D_M, CRIS_INSN_ADDO_CB, CRIS_INSN_ADDO_CW, CRIS_INSN_ADDO_CD
|
||||
, CRIS_INSN_DIP_M, CRIS_INSN_DIP_C, CRIS_INSN_ADDI_ACR_B_R, CRIS_INSN_ADDI_ACR_W_R
|
||||
, CRIS_INSN_ADDI_ACR_D_R, CRIS_INSN_BIAP_PC_B_R, CRIS_INSN_BIAP_PC_W_R, CRIS_INSN_BIAP_PC_D_R
|
||||
, CRIS_INSN_FIDXI, CRIS_INSN_FTAGI, CRIS_INSN_FIDXD, CRIS_INSN_FTAGD
|
||||
} CGEN_INSN_TYPE;
|
||||
|
||||
/* Index of `invalid' insn place holder. */
|
||||
#define CGEN_INSN_INVALID CRIS_INSN_INVALID
|
||||
|
||||
/* Total number of insns in table. */
|
||||
#define MAX_INSNS ((int) CRIS_INSN_FTAGD + 1)
|
||||
|
||||
/* This struct records data prior to insertion or after extraction. */
|
||||
struct cgen_fields
|
||||
{
|
||||
int length;
|
||||
long f_nil;
|
||||
long f_anyof;
|
||||
long f_operand1;
|
||||
long f_size;
|
||||
long f_opcode;
|
||||
long f_mode;
|
||||
long f_operand2;
|
||||
long f_memmode;
|
||||
long f_membit;
|
||||
long f_b5;
|
||||
long f_opcode_hi;
|
||||
long f_dstsrc;
|
||||
long f_u6;
|
||||
long f_s6;
|
||||
long f_u5;
|
||||
long f_u4;
|
||||
long f_s8;
|
||||
long f_disp9_hi;
|
||||
long f_disp9_lo;
|
||||
long f_disp9;
|
||||
long f_qo;
|
||||
long f_indir_pc__byte;
|
||||
long f_indir_pc__word;
|
||||
long f_indir_pc__word_pcrel;
|
||||
long f_indir_pc__dword;
|
||||
long f_indir_pc__dword_pcrel;
|
||||
};
|
||||
|
||||
#define CGEN_INIT_PARSE(od) \
|
||||
{\
|
||||
}
|
||||
#define CGEN_INIT_INSERT(od) \
|
||||
{\
|
||||
}
|
||||
#define CGEN_INIT_EXTRACT(od) \
|
||||
{\
|
||||
}
|
||||
#define CGEN_INIT_PRINT(od) \
|
||||
{\
|
||||
}
|
||||
|
||||
|
||||
#endif /* CRIS_OPC_H */
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/* Collection of junk for CRIS.
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* For other arch:s, this file is described as a "collection of junk", so
|
||||
let's collect some nice junk of our own. Keep it; it might be useful
|
||||
some day! */
|
||||
|
||||
#ifndef CRIS_SIM_H
|
||||
#define CRIS_SIM_H
|
||||
|
||||
typedef struct {
|
||||
/* Whether the branch for the current insn was taken. Placed first
|
||||
here, in hope it'll get closer to the main simulator data. */
|
||||
USI branch_taken;
|
||||
|
||||
/* PC of the insn of the branch. */
|
||||
USI old_pc;
|
||||
|
||||
/* Static cycle count for all insns executed so far, including
|
||||
non-context-specific stall cycles, for example when adding to PC. */
|
||||
unsigned64 basic_cycle_count;
|
||||
|
||||
/* Stall cycles for unaligned access of memory operands. FIXME:
|
||||
Should or should not include unaligned [PC+] operands? */
|
||||
unsigned64 unaligned_mem_dword_count;
|
||||
|
||||
/* Context-specific stall cycles. */
|
||||
unsigned64 memsrc_stall_count;
|
||||
unsigned64 memraw_stall_count;
|
||||
unsigned64 movemsrc_stall_count;
|
||||
unsigned64 movemaddr_stall_count;
|
||||
unsigned64 movemdst_stall_count;
|
||||
unsigned64 mulsrc_stall_count;
|
||||
unsigned64 jumpsrc_stall_count;
|
||||
unsigned64 branch_stall_count;
|
||||
unsigned64 jumptarget_stall_count;
|
||||
|
||||
/* What kind of target-specific trace to perform. */
|
||||
int flags;
|
||||
|
||||
/* Just the basic cycle count. */
|
||||
#define FLAG_CRIS_MISC_PROFILE_SIMPLE 1
|
||||
|
||||
/* Show unaligned accesses. */
|
||||
#define FLAG_CRIS_MISC_PROFILE_UNALIGNED 2
|
||||
|
||||
/* Show schedulable entities. */
|
||||
#define FLAG_CRIS_MISC_PROFILE_SCHEDULABLE 4
|
||||
|
||||
/* Show everything. */
|
||||
#define FLAG_CRIS_MISC_PROFILE_ALL \
|
||||
(FLAG_CRIS_MISC_PROFILE_SIMPLE \
|
||||
| FLAG_CRIS_MISC_PROFILE_UNALIGNED \
|
||||
| FLAG_CRIS_MISC_PROFILE_SCHEDULABLE)
|
||||
|
||||
/* Emit trace of each insn, xsim style. */
|
||||
#define FLAG_CRIS_MISC_PROFILE_XSIM_TRACE 8
|
||||
|
||||
#define N_CRISV32_BRANCH_PREDICTORS 256
|
||||
unsigned char branch_predictors[N_CRISV32_BRANCH_PREDICTORS];
|
||||
|
||||
} CRIS_MISC_PROFILE;
|
||||
|
||||
/* Handler prototypes for functions called from the CGEN description. */
|
||||
|
||||
extern USI cris_bmod_handler (SIM_CPU *, UINT, USI);
|
||||
extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
|
||||
extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
|
||||
extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
|
||||
extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI,
|
||||
USI, USI);
|
||||
|
||||
/* Using GNU syntax (not C99) so we can compile this on RH 6.2
|
||||
(egcs-1.1.2/gcc-2.91.66). */
|
||||
#define cris_trace_printf(SD, CPU, FMT...) \
|
||||
do \
|
||||
{ \
|
||||
if (TRACE_FILE (STATE_TRACE_DATA (SD)) != NULL) \
|
||||
fprintf (TRACE_FILE (CPU_TRACE_DATA (CPU)), FMT); \
|
||||
else \
|
||||
sim_io_printf (SD, FMT); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
#define crisv32f_branch_taken(cpu, oldpc, newpc, taken) \
|
||||
do \
|
||||
{ \
|
||||
CPU_CRIS_MISC_PROFILE (cpu)->old_pc = oldpc; \
|
||||
CPU_CRIS_MISC_PROFILE (cpu)->branch_taken = taken; \
|
||||
} \
|
||||
while (0)
|
||||
#else
|
||||
#define crisv32f_branch_taken(cpu, oldpc, newpc, taken)
|
||||
#endif
|
||||
|
||||
#define crisv10f_branch_taken(cpu, oldpc, newpc, taken)
|
||||
|
||||
#define crisv32f_read_supr(cpu, index) \
|
||||
(cgen_rtx_error (current_cpu, \
|
||||
"Read of support register is unimplemented"), \
|
||||
0)
|
||||
|
||||
#define crisv32f_write_supr(cpu, index, val) \
|
||||
cgen_rtx_error (current_cpu, \
|
||||
"Write to support register is unimplemented") \
|
||||
|
||||
#define crisv32f_rfg_handler(cpu, pc) \
|
||||
cgen_rtx_error (current_cpu, "RFG isn't implemented")
|
||||
|
||||
#define crisv32f_halt_handler(cpu, pc) \
|
||||
(cgen_rtx_error (current_cpu, "HALT isn't implemented"), 0)
|
||||
|
||||
#define crisv32f_fidxi_handler(cpu, pc, indx) \
|
||||
(cgen_rtx_error (current_cpu, "FIDXI isn't implemented"), 0)
|
||||
|
||||
#define crisv32f_ftagi_handler(cpu, pc, indx) \
|
||||
(cgen_rtx_error (current_cpu, "FTAGI isn't implemented"), 0)
|
||||
|
||||
#define crisv32f_fidxd_handler(cpu, pc, indx) \
|
||||
(cgen_rtx_error (current_cpu, "FIDXD isn't implemented"), 0)
|
||||
|
||||
#define crisv32f_ftagd_handler(cpu, pc, indx) \
|
||||
(cgen_rtx_error (current_cpu, "FTAGD isn't implemented"), 0)
|
||||
|
||||
/* We have nothing special to do when interrupts or NMI are enabled
|
||||
after having been disabled, so empty macros are enough for these
|
||||
hooks. */
|
||||
#define crisv32f_interrupts_enabled(cpu)
|
||||
#define crisv32f_nmi_enabled(cpu)
|
||||
|
||||
/* Better warn for this case here, because everything needed is
|
||||
somewhere within the CPU. Compare to trying to use interrupts and
|
||||
NMI, which would fail earlier, when trying to make nonexistent
|
||||
external components generate those exceptions. */
|
||||
#define crisv32f_single_step_enabled(cpu) \
|
||||
((crisv32f_h_qbit_get (cpu) != 0 \
|
||||
|| (crisv32f_h_sr_get (cpu, H_SR_SPC) & ~1) != 0) \
|
||||
? (cgen_rtx_error (cpu, \
|
||||
"single-stepping isn't implemented"), 0) \
|
||||
: 0)
|
||||
|
||||
/* We don't need to track the value of the PID register here. */
|
||||
#define crisv32f_write_pid_handler(cpu, val)
|
||||
|
||||
/* Neither do we need to know of transitions to user mode. */
|
||||
#define crisv32f_usermode_enabled(cpu)
|
||||
|
||||
/* House-keeping exported from traps.c */
|
||||
extern void cris_set_callbacks (host_callback *);
|
||||
|
||||
/* FIXME: Add more junk. */
|
||||
#endif
|
||||
|
|
@ -0,0 +1,382 @@
|
|||
/* CRIS base simulator support code
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* The infrastructure is based on that of i960.c. */
|
||||
|
||||
#define WANT_CPU
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "cgen-mem.h"
|
||||
#include "cgen-ops.h"
|
||||
|
||||
#define MY(f) XCONCAT3(crisv,BASENUM,f)
|
||||
|
||||
/* Dispatcher for break insn. */
|
||||
|
||||
USI
|
||||
MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc)
|
||||
{
|
||||
SIM_DESC sd = CPU_STATE (cpu);
|
||||
USI ret = pc + 2;
|
||||
|
||||
MY (f_h_pc_set) (cpu, ret);
|
||||
|
||||
/* FIXME: Error out if IBR or ERP set. */
|
||||
switch (breaknum)
|
||||
{
|
||||
case 13:
|
||||
MY (f_h_gr_set (cpu, 10,
|
||||
cris_break_13_handler (cpu,
|
||||
MY (f_h_gr_get (cpu, 9)),
|
||||
MY (f_h_gr_get (cpu, 10)),
|
||||
MY (f_h_gr_get (cpu, 11)),
|
||||
MY (f_h_gr_get (cpu, 12)),
|
||||
MY (f_h_gr_get (cpu, 13)),
|
||||
MY (f_h_sr_get (cpu, 7)),
|
||||
MY (f_h_sr_get (cpu, 11)),
|
||||
pc)));
|
||||
break;
|
||||
|
||||
case 14:
|
||||
sim_io_printf (sd, "%x\n", MY (f_h_gr_get (cpu, 3)));
|
||||
break;
|
||||
|
||||
case 15:
|
||||
/* Re-use the Linux exit call. */
|
||||
cris_break_13_handler (cpu, /* TARGET_SYS_exit */ 1, 0,
|
||||
0, 0, 0, 0, 0, pc);
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
return MY (f_h_pc_get) (cpu);
|
||||
}
|
||||
|
||||
/* Accessor function for simulator internal use.
|
||||
Note the contents of BUF are in target byte order. */
|
||||
|
||||
int
|
||||
MY (f_fetch_register) (SIM_CPU *current_cpu, int rn,
|
||||
unsigned char *buf, int len ATTRIBUTE_UNUSED)
|
||||
{
|
||||
SETTSI (buf, XCONCAT3(crisv,BASENUM,f_h_gr_get) (current_cpu, rn));
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Accessor function for simulator internal use.
|
||||
Note the contents of BUF are in target byte order. */
|
||||
|
||||
int
|
||||
MY (f_store_register) (SIM_CPU *current_cpu, int rn,
|
||||
unsigned char *buf, int len ATTRIBUTE_UNUSED)
|
||||
{
|
||||
XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf));
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
|
||||
/* FIXME: Some of these should be inline or macros. Later. */
|
||||
|
||||
/* Initialize cycle counting for an insn.
|
||||
FIRST_P is non-zero if this is the first insn in a set of parallel
|
||||
insns. */
|
||||
|
||||
void
|
||||
MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* To give the impression that we actually know what PC is, we have to
|
||||
dump register contents *before* the *next* insn, not after the
|
||||
*previous* insn. Uhh... */
|
||||
|
||||
/* FIXME: Move this to separate, overridable function. */
|
||||
if ((CPU_CRIS_MISC_PROFILE (current_cpu)->flags
|
||||
& FLAG_CRIS_MISC_PROFILE_XSIM_TRACE)
|
||||
#ifdef GET_H_INSN_PREFIXED_P
|
||||
/* For versions with prefixed insns, trace the combination as
|
||||
one insn. */
|
||||
&& !GET_H_INSN_PREFIXED_P ()
|
||||
#endif
|
||||
&& 1)
|
||||
{
|
||||
int i;
|
||||
char flags[7];
|
||||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||||
|
||||
cris_trace_printf (sd, current_cpu, "%lx ", (unsigned long) (CPU (h_pc)));
|
||||
|
||||
for (i = 0; i < 15; i++)
|
||||
cris_trace_printf (sd, current_cpu, "%lx ",
|
||||
(unsigned long) (XCONCAT3(crisv,BASENUM,
|
||||
f_h_gr_get) (current_cpu,
|
||||
i)));
|
||||
flags[0] = GET_H_IBIT () != 0 ? 'I' : 'i';
|
||||
flags[1] = GET_H_XBIT () != 0 ? 'X' : 'x';
|
||||
flags[2] = GET_H_NBIT () != 0 ? 'N' : 'n';
|
||||
flags[3] = GET_H_ZBIT () != 0 ? 'Z' : 'z';
|
||||
flags[4] = GET_H_VBIT () != 0 ? 'V' : 'v';
|
||||
flags[5] = GET_H_CBIT () != 0 ? 'C' : 'c';
|
||||
flags[6] = 0;
|
||||
|
||||
/* Emit ACR after flags and cycle count for this insn. */
|
||||
if (BASENUM == 32)
|
||||
cris_trace_printf (sd, current_cpu, "%s %d %lx\n", flags,
|
||||
(int)
|
||||
((CPU_CRIS_MISC_PROFILE (current_cpu)
|
||||
->basic_cycle_count
|
||||
- CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
|
||||
->basic_cycle_count)
|
||||
+ (CPU_CRIS_MISC_PROFILE (current_cpu)
|
||||
->unaligned_mem_dword_count
|
||||
- CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
|
||||
->unaligned_mem_dword_count)),
|
||||
(unsigned long) (XCONCAT3(crisv,BASENUM,
|
||||
f_h_gr_get) (current_cpu,
|
||||
15)));
|
||||
else
|
||||
cris_trace_printf (sd, current_cpu, "%s %d\n", flags,
|
||||
(int)
|
||||
((CPU_CRIS_MISC_PROFILE (current_cpu)
|
||||
->basic_cycle_count
|
||||
- CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
|
||||
->basic_cycle_count)
|
||||
+ (CPU_CRIS_MISC_PROFILE (current_cpu)
|
||||
->unaligned_mem_dword_count
|
||||
- CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
|
||||
->unaligned_mem_dword_count)));
|
||||
|
||||
CPU_CRIS_PREV_MISC_PROFILE (current_cpu)[0]
|
||||
= CPU_CRIS_MISC_PROFILE (current_cpu)[0];
|
||||
}
|
||||
}
|
||||
|
||||
/* Record the cycles computed for an insn.
|
||||
LAST_P is non-zero if this is the last insn in a set of parallel insns,
|
||||
and we update the total cycle count.
|
||||
CYCLES is the cycle count of the insn. */
|
||||
|
||||
void
|
||||
MY (f_model_insn_after) (SIM_CPU *current_cpu, int last_p ATTRIBUTE_UNUSED,
|
||||
int cycles)
|
||||
{
|
||||
PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);
|
||||
|
||||
PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
|
||||
CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count += cycles;
|
||||
PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
|
||||
}
|
||||
|
||||
/* Initialize cycle counting for an insn.
|
||||
FIRST_P is non-zero if this is the first insn in a set of parallel
|
||||
insns. */
|
||||
|
||||
void
|
||||
MY (f_model_init_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
|
||||
int first_p ATTRIBUTE_UNUSED)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Record the cycles computed for an insn.
|
||||
LAST_P is non-zero if this is the last insn in a set of parallel insns,
|
||||
and we update the total cycle count. */
|
||||
|
||||
void
|
||||
MY (f_model_update_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
|
||||
int last_p ATTRIBUTE_UNUSED)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
#if 0
|
||||
void
|
||||
MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
void
|
||||
MY (f_model_mark_get_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
void
|
||||
MY (f_model_mark_set_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Create the context for a thread. */
|
||||
|
||||
void *
|
||||
MY (make_thread_cpu_data) (SIM_CPU *current_cpu, void *context)
|
||||
{
|
||||
void *info = xmalloc (current_cpu->thread_cpu_data_size);
|
||||
|
||||
if (context != NULL)
|
||||
memcpy (info,
|
||||
context,
|
||||
current_cpu->thread_cpu_data_size);
|
||||
else
|
||||
memset (info, 0, current_cpu->thread_cpu_data_size),abort();
|
||||
return info;
|
||||
}
|
||||
|
||||
/* Hook function for per-cpu simulator initialization. */
|
||||
|
||||
void
|
||||
MY (f_specific_init) (SIM_CPU *current_cpu)
|
||||
{
|
||||
current_cpu->make_thread_cpu_data = MY (make_thread_cpu_data);
|
||||
current_cpu->thread_cpu_data_size = sizeof (current_cpu->cpu_data);
|
||||
}
|
||||
|
||||
/* Model function for arbitrary single stall cycles. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_stall)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
|
||||
const IDESC *idesc,
|
||||
int unit_num,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return idesc->timing->units[unit_num].done;
|
||||
}
|
||||
|
||||
#ifndef SPECIFIC_U_SKIP4_FN
|
||||
|
||||
/* Model function for u-skip4 unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_skip4)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc,
|
||||
int unit_num,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
|
||||
CPU (h_pc) += 4;
|
||||
return idesc->timing->units[unit_num].done;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef SPECIFIC_U_EXEC_FN
|
||||
|
||||
/* Model function for u-exec unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_exec)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc,
|
||||
int unit_num, int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
|
||||
CPU (h_pc) += 2;
|
||||
return idesc->timing->units[unit_num].done;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef SPECIFIC_U_MEM_FN
|
||||
|
||||
/* Model function for u-mem unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_mem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
|
||||
const IDESC *idesc,
|
||||
int unit_num,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return idesc->timing->units[unit_num].done;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef SPECIFIC_U_CONST16_FN
|
||||
|
||||
/* Model function for u-const16 unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_const16)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc,
|
||||
int unit_num,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
CPU (h_pc) += 2;
|
||||
return idesc->timing->units[unit_num].done;
|
||||
}
|
||||
#endif /* SPECIFIC_U_CONST16_FN */
|
||||
|
||||
#ifndef SPECIFIC_U_CONST32_FN
|
||||
|
||||
/* This will be incorrect for early models, where a dword always take
|
||||
two cycles. */
|
||||
#define CRIS_MODEL_MASK_PC_STALL 2
|
||||
|
||||
/* Model function for u-const32 unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_const32)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc,
|
||||
int unit_num,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int unaligned_extra
|
||||
= (((CPU (h_pc) + 2) & CRIS_MODEL_MASK_PC_STALL)
|
||||
== CRIS_MODEL_MASK_PC_STALL);
|
||||
|
||||
/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
|
||||
CPU_CRIS_MISC_PROFILE (current_cpu)->unaligned_mem_dword_count
|
||||
+= unaligned_extra;
|
||||
|
||||
CPU (h_pc) += 4;
|
||||
return idesc->timing->units[unit_num].done;
|
||||
}
|
||||
#endif /* SPECIFIC_U_CONST32_FN */
|
||||
|
||||
#ifndef SPECIFIC_U_MOVEM_FN
|
||||
|
||||
/* Model function for u-movem unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_movem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
INT limreg)
|
||||
{
|
||||
/* FIXME: Add cycles for misalignment. */
|
||||
|
||||
if (limreg == -1)
|
||||
abort ();
|
||||
|
||||
/* We don't record movem move cycles in movemsrc_stall_count since
|
||||
those cycles have historically been handled as ordinary cycles. */
|
||||
return limreg + 1;
|
||||
}
|
||||
#endif /* SPECIFIC_U_MOVEM_FN */
|
||||
|
||||
#endif /* WITH_PROFILE_MODEL_P */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* CRIS v10 simulator support code
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* The infrastructure is based on that of i960.c. */
|
||||
|
||||
#define WANT_CPU_CRISV10F
|
||||
|
||||
#define BASENUM 10
|
||||
#include "cris-tmpl.c"
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
|
||||
/* Model function for u-multiply unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_multiply)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* WITH_PROFILE_MODEL_P */
|
||||
|
|
@ -0,0 +1,558 @@
|
|||
/* CRIS v32 simulator support code
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* The infrastructure is based on that of i960.c. */
|
||||
|
||||
#define WANT_CPU_CRISV32F
|
||||
|
||||
#define SPECIFIC_U_EXEC_FN
|
||||
#define SPECIFIC_U_SKIP4_FN
|
||||
#define SPECIFIC_U_CONST16_FN
|
||||
#define SPECIFIC_U_CONST32_FN
|
||||
#define SPECIFIC_U_MEM_FN
|
||||
#define SPECIFIC_U_MOVEM_FN
|
||||
#define BASENUM 32
|
||||
#include "cris-tmpl.c"
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
|
||||
/* Re-use the bit position for the BZ register, since there are no stall
|
||||
cycles for reading or writing it. */
|
||||
#define CRIS_BZ_REGNO 16
|
||||
#define CRIS_MODF_JUMP_MASK (1 << CRIS_BZ_REGNO)
|
||||
/* Likewise for the WZ register, marking memory writes. */
|
||||
#define CRIS_WZ_REGNO 20
|
||||
#define CRIS_MODF_MEM_WRITE_MASK (1 << CRIS_WZ_REGNO)
|
||||
#define CRIS_MOF_REGNO (16 + 7)
|
||||
#define CRIS_ALWAYS_CONDITION 14
|
||||
|
||||
/* This macro must only be used in context where there's only one
|
||||
dynamic cause for a penalty, except in the u-exec unit. */
|
||||
|
||||
#define PENALIZE1(CNT) \
|
||||
do \
|
||||
{ \
|
||||
CPU_CRIS_MISC_PROFILE (current_cpu)->CNT++; \
|
||||
model_data->prev_prev_prev_modf_regs \
|
||||
= model_data->prev_prev_modf_regs; \
|
||||
model_data->prev_prev_modf_regs \
|
||||
= model_data->prev_modf_regs; \
|
||||
model_data->prev_modf_regs = 0; \
|
||||
model_data->prev_prev_prev_movem_dest_regs \
|
||||
= model_data->prev_prev_movem_dest_regs; \
|
||||
model_data->prev_prev_movem_dest_regs \
|
||||
= model_data->prev_movem_dest_regs; \
|
||||
model_data->prev_movem_dest_regs = 0; \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
|
||||
/* Model function for u-skip4 unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_skip4)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
|
||||
CPU (h_pc) += 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-exec unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_exec)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
INT destreg_in,
|
||||
INT srcreg,
|
||||
INT destreg_out)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
UINT modf_regs
|
||||
= ((destreg_out == -1 ? 0 : (1 << destreg_out))
|
||||
| model_data->modf_regs);
|
||||
|
||||
if (srcreg != -1)
|
||||
{
|
||||
if (model_data->prev_movem_dest_regs & (1 << srcreg))
|
||||
{
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
}
|
||||
else if (model_data->prev_prev_movem_dest_regs & (1 << srcreg))
|
||||
{
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
}
|
||||
else if (model_data->prev_prev_prev_movem_dest_regs & (1 << srcreg))
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
}
|
||||
|
||||
if (destreg_in != -1)
|
||||
{
|
||||
if (model_data->prev_movem_dest_regs & (1 << destreg_in))
|
||||
{
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
}
|
||||
else if (model_data->prev_prev_movem_dest_regs & (1 << destreg_in))
|
||||
{
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
}
|
||||
else if (model_data->prev_prev_prev_movem_dest_regs & (1 << destreg_in))
|
||||
PENALIZE1 (movemdst_stall_count);
|
||||
}
|
||||
|
||||
model_data->prev_prev_prev_modf_regs
|
||||
= model_data->prev_prev_modf_regs;
|
||||
model_data->prev_prev_modf_regs = model_data->prev_modf_regs;
|
||||
model_data->prev_modf_regs = modf_regs;
|
||||
model_data->modf_regs = 0;
|
||||
|
||||
model_data->prev_prev_prev_movem_dest_regs
|
||||
= model_data->prev_prev_movem_dest_regs;
|
||||
model_data->prev_prev_movem_dest_regs = model_data->prev_movem_dest_regs;
|
||||
model_data->prev_movem_dest_regs = model_data->movem_dest_regs;
|
||||
model_data->movem_dest_regs = 0;
|
||||
|
||||
/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
|
||||
CPU (h_pc) += 2;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Special case used when the destination is a special register. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_exec_to_sr)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
INT srcreg,
|
||||
INT specreg)
|
||||
{
|
||||
int specdest;
|
||||
|
||||
if (specreg != -1)
|
||||
specdest = specreg + 16;
|
||||
else
|
||||
abort ();
|
||||
|
||||
return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_exec))
|
||||
(current_cpu, NULL, 0, 0, -1, srcreg,
|
||||
/* The positions for constant-zero registers BZ and WZ are recycled
|
||||
for jump and memory-write markers. We must take precautions
|
||||
here not to add false markers for them. It might be that the
|
||||
hardware inserts stall cycles for instructions that actually try
|
||||
and write those registers, but we'll burn that bridge when we
|
||||
get to it; we'd have to find other free bits or make new
|
||||
model_data variables. However, it's doubtful that there will
|
||||
ever be a need to be cycle-correct for useless code, at least in
|
||||
this particular simulator, mainly used for GCC testing. */
|
||||
specdest == CRIS_BZ_REGNO || specdest == CRIS_WZ_REGNO
|
||||
? -1 : specdest);
|
||||
}
|
||||
|
||||
|
||||
/* Special case for movem. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_exec_movem)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
INT srcreg,
|
||||
INT destreg_out)
|
||||
{
|
||||
return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_exec))
|
||||
(current_cpu, NULL, 0, 0, -1, srcreg, destreg_out);
|
||||
}
|
||||
|
||||
/* Model function for u-const16 unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_const16)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
/* If the previous insn was a jump of some sort and this insn
|
||||
straddles a cache-line, there's a one-cycle penalty.
|
||||
FIXME: Test-cases for normal const16 and others, like branch. */
|
||||
if ((model_data->prev_modf_regs & CRIS_MODF_JUMP_MASK)
|
||||
&& (CPU (h_pc) & 0x1e) == 0x1e)
|
||||
PENALIZE1 (jumptarget_stall_count);
|
||||
|
||||
/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
|
||||
CPU (h_pc) += 2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-const32 unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_const32)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
/* If the previous insn was a jump of some sort and this insn
|
||||
straddles a cache-line, there's a one-cycle penalty. */
|
||||
if ((model_data->prev_modf_regs & CRIS_MODF_JUMP_MASK)
|
||||
&& (CPU (h_pc) & 0x1e) == 0x1c)
|
||||
PENALIZE1 (jumptarget_stall_count);
|
||||
|
||||
/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
|
||||
CPU (h_pc) += 4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-mem unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_mem)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
INT srcreg)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
if (srcreg == -1)
|
||||
abort ();
|
||||
|
||||
/* If srcreg references a register modified in the previous cycle
|
||||
through other than autoincrement, then there's a penalty: one
|
||||
cycle. */
|
||||
if (model_data->prev_modf_regs & (1 << srcreg))
|
||||
PENALIZE1 (memsrc_stall_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-mem-r unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_mem_r)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
/* There's a two-cycle penalty for read after a memory write in any of
|
||||
the two previous cycles, known as a cache read-after-write hazard.
|
||||
|
||||
This model function (the model_data member access) depends on being
|
||||
executed before the u-exec unit. */
|
||||
if ((model_data->prev_modf_regs & CRIS_MODF_MEM_WRITE_MASK)
|
||||
|| (model_data->prev_prev_modf_regs & CRIS_MODF_MEM_WRITE_MASK))
|
||||
{
|
||||
PENALIZE1 (memraw_stall_count);
|
||||
PENALIZE1 (memraw_stall_count);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-mem-w unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_mem_w)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
/* Mark that memory has been written. This model function (the
|
||||
model_data member access) depends on being executed after the
|
||||
u-exec unit. */
|
||||
model_data->prev_modf_regs |= CRIS_MODF_MEM_WRITE_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-movem-rtom unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_movem_rtom)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
/* Deliberate order. */
|
||||
INT addrreg, INT limreg)
|
||||
{
|
||||
USI addr;
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
if (limreg == -1 || addrreg == -1)
|
||||
abort ();
|
||||
|
||||
addr = GET_H_GR (addrreg);
|
||||
|
||||
/* The movem-to-memory instruction must not move a register modified
|
||||
in one of the previous two cycles. Enforce by adding penalty
|
||||
cycles. */
|
||||
if (model_data->prev_modf_regs & ((1 << (limreg + 1)) - 1))
|
||||
{
|
||||
PENALIZE1 (movemsrc_stall_count);
|
||||
PENALIZE1 (movemsrc_stall_count);
|
||||
}
|
||||
else if (model_data->prev_prev_modf_regs & ((1 << (limreg + 1)) - 1))
|
||||
PENALIZE1 (movemsrc_stall_count);
|
||||
|
||||
/* One-cycle penalty for each cache-line straddled. Use the
|
||||
documented expressions. Unfortunately no penalty cycles are
|
||||
eliminated by any penalty cycles above. We file these numbers
|
||||
separately, since they aren't schedulable for all cases. */
|
||||
if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5))
|
||||
;
|
||||
else if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5) - 1)
|
||||
PENALIZE1 (movemaddr_stall_count);
|
||||
else if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5) - 2)
|
||||
{
|
||||
PENALIZE1 (movemaddr_stall_count);
|
||||
PENALIZE1 (movemaddr_stall_count);
|
||||
}
|
||||
else
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-movem-mtor unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_movem_mtor)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
/* Deliberate order. */
|
||||
INT addrreg, INT limreg)
|
||||
{
|
||||
USI addr;
|
||||
int nregs = limreg + 1;
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
if (limreg == -1 || addrreg == -1)
|
||||
abort ();
|
||||
|
||||
addr = GET_H_GR (addrreg);
|
||||
|
||||
/* One-cycle penalty for each cache-line straddled. Use the
|
||||
documented expressions. One cycle is the norm; more cycles are
|
||||
counted as penalties. Unfortunately no penalty cycles here
|
||||
eliminate penalty cycles indicated in ->movem_dest_regs. */
|
||||
if ((addr >> 5) == (((addr + 4 * nregs) - 1) >> 5) - 1)
|
||||
PENALIZE1 (movemaddr_stall_count);
|
||||
else if ((addr >> 5) == (((addr + 4 * nregs) - 1) >> 5) - 2)
|
||||
{
|
||||
PENALIZE1 (movemaddr_stall_count);
|
||||
PENALIZE1 (movemaddr_stall_count);
|
||||
}
|
||||
|
||||
model_data->modf_regs |= ((1 << nregs) - 1);
|
||||
model_data->movem_dest_regs |= ((1 << nregs) - 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* Model function for u-branch unit.
|
||||
FIXME: newpc and cc are always wrong. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,_u_branch)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc,
|
||||
int unit_num, int referenced)
|
||||
{
|
||||
CRIS_MISC_PROFILE *profp = CPU_CRIS_MISC_PROFILE (current_cpu);
|
||||
USI pc = profp->old_pc;
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
int taken = profp->branch_taken;
|
||||
int branch_index = (pc & (N_CRISV32_BRANCH_PREDICTORS - 1)) >> 1;
|
||||
int pred_taken = (profp->branch_predictors[branch_index] & 2) != 0;
|
||||
|
||||
if (taken != pred_taken)
|
||||
{
|
||||
PENALIZE1 (branch_stall_count);
|
||||
PENALIZE1 (branch_stall_count);
|
||||
}
|
||||
|
||||
if (taken)
|
||||
{
|
||||
if (profp->branch_predictors[branch_index] < 3)
|
||||
profp->branch_predictors[branch_index]++;
|
||||
|
||||
return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump))
|
||||
(current_cpu, idesc, unit_num, referenced, -1);
|
||||
}
|
||||
|
||||
if (profp->branch_predictors[branch_index] != 0)
|
||||
profp->branch_predictors[branch_index]--;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-jump-r unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_jump_r)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
int regno)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
if (regno == -1)
|
||||
abort ();
|
||||
|
||||
/* For jump-to-register, the register must not have been modified the
|
||||
last two cycles. Penalty: two cycles from the modifying insn. */
|
||||
if ((1 << regno) & model_data->prev_modf_regs)
|
||||
{
|
||||
PENALIZE1 (jumpsrc_stall_count);
|
||||
PENALIZE1 (jumpsrc_stall_count);
|
||||
}
|
||||
else if ((1 << regno) & model_data->prev_prev_modf_regs)
|
||||
PENALIZE1 (jumpsrc_stall_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-jump-sr unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump_sr)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc,
|
||||
int unit_num, int referenced,
|
||||
int sr_regno)
|
||||
{
|
||||
int regno;
|
||||
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
if (sr_regno == -1)
|
||||
abort ();
|
||||
|
||||
regno = sr_regno + 16;
|
||||
|
||||
/* For jump-to-register, the register must not have been modified the
|
||||
last two cycles. Penalty: two cycles from the modifying insn. */
|
||||
if ((1 << regno) & model_data->prev_modf_regs)
|
||||
{
|
||||
PENALIZE1 (jumpsrc_stall_count);
|
||||
PENALIZE1 (jumpsrc_stall_count);
|
||||
}
|
||||
else if ((1 << regno) & model_data->prev_prev_modf_regs)
|
||||
PENALIZE1 (jumpsrc_stall_count);
|
||||
|
||||
return
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump)) (current_cpu, idesc,
|
||||
unit_num, referenced, -1);
|
||||
}
|
||||
|
||||
/* Model function for u-jump unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_jump)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
int out_sr_regno)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
/* Mark that we made a jump. */
|
||||
model_data->modf_regs
|
||||
|= (CRIS_MODF_JUMP_MASK
|
||||
| (out_sr_regno == -1 || out_sr_regno == CRIS_BZ_REGNO
|
||||
? 0 : (1 << (out_sr_regno + 16))));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Model function for u-multiply unit. */
|
||||
|
||||
int
|
||||
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
||||
_u_multiply)) (SIM_CPU *current_cpu,
|
||||
const IDESC *idesc ATTRIBUTE_UNUSED,
|
||||
int unit_num ATTRIBUTE_UNUSED,
|
||||
int referenced ATTRIBUTE_UNUSED,
|
||||
int srcreg, int destreg)
|
||||
{
|
||||
MODEL_CRISV32_DATA *model_data
|
||||
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
||||
|
||||
/* Sanity-check for cases that should never happen. */
|
||||
if (srcreg == -1 || destreg == -1)
|
||||
abort ();
|
||||
|
||||
/* This takes extra cycles when one of the inputs has been modified
|
||||
through other than autoincrement in the previous cycle. Penalty:
|
||||
one cycle. */
|
||||
if (((1 << srcreg) | (1 << destreg)) & model_data->prev_modf_regs)
|
||||
PENALIZE1 (mulsrc_stall_count);
|
||||
|
||||
/* We modified the multiplication destination (marked in u-exec) and
|
||||
the MOF register. */
|
||||
model_data->modf_regs |= (1 << CRIS_MOF_REGNO);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* WITH_PROFILE_MODEL_P */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,141 @@
|
|||
/* Decode header for crisv10f.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CRISV10F_DECODE_H
|
||||
#define CRISV10F_DECODE_H
|
||||
|
||||
extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
|
||||
CGEN_INSN_INT,
|
||||
ARGBUF *);
|
||||
extern void crisv10f_init_idesc_table (SIM_CPU *);
|
||||
extern void crisv10f_sem_init_idesc_table (SIM_CPU *);
|
||||
extern void crisv10f_semf_init_idesc_table (SIM_CPU *);
|
||||
|
||||
/* Enum declaration for instructions in cpu family crisv10f. */
|
||||
typedef enum crisv10f_insn_type {
|
||||
CRISV10F_INSN_X_INVALID, CRISV10F_INSN_X_AFTER, CRISV10F_INSN_X_BEFORE, CRISV10F_INSN_X_CTI_CHAIN
|
||||
, CRISV10F_INSN_X_CHAIN, CRISV10F_INSN_X_BEGIN, CRISV10F_INSN_NOP, CRISV10F_INSN_MOVE_B_R
|
||||
, CRISV10F_INSN_MOVE_W_R, CRISV10F_INSN_MOVE_D_R, CRISV10F_INSN_MOVEPCR, CRISV10F_INSN_MOVEQ
|
||||
, CRISV10F_INSN_MOVS_B_R, CRISV10F_INSN_MOVS_W_R, CRISV10F_INSN_MOVU_B_R, CRISV10F_INSN_MOVU_W_R
|
||||
, CRISV10F_INSN_MOVECBR, CRISV10F_INSN_MOVECWR, CRISV10F_INSN_MOVECDR, CRISV10F_INSN_MOVSCBR
|
||||
, CRISV10F_INSN_MOVSCWR, CRISV10F_INSN_MOVUCBR, CRISV10F_INSN_MOVUCWR, CRISV10F_INSN_ADDQ
|
||||
, CRISV10F_INSN_SUBQ, CRISV10F_INSN_CMP_R_B_R, CRISV10F_INSN_CMP_R_W_R, CRISV10F_INSN_CMP_R_D_R
|
||||
, CRISV10F_INSN_CMP_M_B_M, CRISV10F_INSN_CMP_M_W_M, CRISV10F_INSN_CMP_M_D_M, CRISV10F_INSN_CMPCBR
|
||||
, CRISV10F_INSN_CMPCWR, CRISV10F_INSN_CMPCDR, CRISV10F_INSN_CMPQ, CRISV10F_INSN_CMPS_M_B_M
|
||||
, CRISV10F_INSN_CMPS_M_W_M, CRISV10F_INSN_CMPSCBR, CRISV10F_INSN_CMPSCWR, CRISV10F_INSN_CMPU_M_B_M
|
||||
, CRISV10F_INSN_CMPU_M_W_M, CRISV10F_INSN_CMPUCBR, CRISV10F_INSN_CMPUCWR, CRISV10F_INSN_MOVE_M_B_M
|
||||
, CRISV10F_INSN_MOVE_M_W_M, CRISV10F_INSN_MOVE_M_D_M, CRISV10F_INSN_MOVS_M_B_M, CRISV10F_INSN_MOVS_M_W_M
|
||||
, CRISV10F_INSN_MOVU_M_B_M, CRISV10F_INSN_MOVU_M_W_M, CRISV10F_INSN_MOVE_R_SPRV10, CRISV10F_INSN_MOVE_SPR_RV10
|
||||
, CRISV10F_INSN_RET_TYPE, CRISV10F_INSN_MOVE_M_SPRV10, CRISV10F_INSN_MOVE_C_SPRV10_P0, CRISV10F_INSN_MOVE_C_SPRV10_P1
|
||||
, CRISV10F_INSN_MOVE_C_SPRV10_P4, CRISV10F_INSN_MOVE_C_SPRV10_P5, CRISV10F_INSN_MOVE_C_SPRV10_P8, CRISV10F_INSN_MOVE_C_SPRV10_P9
|
||||
, CRISV10F_INSN_MOVE_C_SPRV10_P10, CRISV10F_INSN_MOVE_C_SPRV10_P11, CRISV10F_INSN_MOVE_C_SPRV10_P12, CRISV10F_INSN_MOVE_C_SPRV10_P13
|
||||
, CRISV10F_INSN_MOVE_C_SPRV10_P7, CRISV10F_INSN_MOVE_C_SPRV10_P14, CRISV10F_INSN_MOVE_C_SPRV10_P15, CRISV10F_INSN_MOVE_SPR_MV10
|
||||
, CRISV10F_INSN_SBFS, CRISV10F_INSN_MOVEM_R_M, CRISV10F_INSN_MOVEM_M_R, CRISV10F_INSN_MOVEM_M_PC
|
||||
, CRISV10F_INSN_ADD_B_R, CRISV10F_INSN_ADD_W_R, CRISV10F_INSN_ADD_D_R, CRISV10F_INSN_ADD_M_B_M
|
||||
, CRISV10F_INSN_ADD_M_W_M, CRISV10F_INSN_ADD_M_D_M, CRISV10F_INSN_ADDCBR, CRISV10F_INSN_ADDCWR
|
||||
, CRISV10F_INSN_ADDCDR, CRISV10F_INSN_ADDCPC, CRISV10F_INSN_ADDS_B_R, CRISV10F_INSN_ADDS_W_R
|
||||
, CRISV10F_INSN_ADDS_M_B_M, CRISV10F_INSN_ADDS_M_W_M, CRISV10F_INSN_ADDSCBR, CRISV10F_INSN_ADDSCWR
|
||||
, CRISV10F_INSN_ADDSPCPC, CRISV10F_INSN_ADDU_B_R, CRISV10F_INSN_ADDU_W_R, CRISV10F_INSN_ADDU_M_B_M
|
||||
, CRISV10F_INSN_ADDU_M_W_M, CRISV10F_INSN_ADDUCBR, CRISV10F_INSN_ADDUCWR, CRISV10F_INSN_SUB_B_R
|
||||
, CRISV10F_INSN_SUB_W_R, CRISV10F_INSN_SUB_D_R, CRISV10F_INSN_SUB_M_B_M, CRISV10F_INSN_SUB_M_W_M
|
||||
, CRISV10F_INSN_SUB_M_D_M, CRISV10F_INSN_SUBCBR, CRISV10F_INSN_SUBCWR, CRISV10F_INSN_SUBCDR
|
||||
, CRISV10F_INSN_SUBS_B_R, CRISV10F_INSN_SUBS_W_R, CRISV10F_INSN_SUBS_M_B_M, CRISV10F_INSN_SUBS_M_W_M
|
||||
, CRISV10F_INSN_SUBSCBR, CRISV10F_INSN_SUBSCWR, CRISV10F_INSN_SUBU_B_R, CRISV10F_INSN_SUBU_W_R
|
||||
, CRISV10F_INSN_SUBU_M_B_M, CRISV10F_INSN_SUBU_M_W_M, CRISV10F_INSN_SUBUCBR, CRISV10F_INSN_SUBUCWR
|
||||
, CRISV10F_INSN_ADDI_B_R, CRISV10F_INSN_ADDI_W_R, CRISV10F_INSN_ADDI_D_R, CRISV10F_INSN_NEG_B_R
|
||||
, CRISV10F_INSN_NEG_W_R, CRISV10F_INSN_NEG_D_R, CRISV10F_INSN_TEST_M_B_M, CRISV10F_INSN_TEST_M_W_M
|
||||
, CRISV10F_INSN_TEST_M_D_M, CRISV10F_INSN_MOVE_R_M_B_M, CRISV10F_INSN_MOVE_R_M_W_M, CRISV10F_INSN_MOVE_R_M_D_M
|
||||
, CRISV10F_INSN_MULS_B, CRISV10F_INSN_MULS_W, CRISV10F_INSN_MULS_D, CRISV10F_INSN_MULU_B
|
||||
, CRISV10F_INSN_MULU_W, CRISV10F_INSN_MULU_D, CRISV10F_INSN_MSTEP, CRISV10F_INSN_DSTEP
|
||||
, CRISV10F_INSN_ABS, CRISV10F_INSN_AND_B_R, CRISV10F_INSN_AND_W_R, CRISV10F_INSN_AND_D_R
|
||||
, CRISV10F_INSN_AND_M_B_M, CRISV10F_INSN_AND_M_W_M, CRISV10F_INSN_AND_M_D_M, CRISV10F_INSN_ANDCBR
|
||||
, CRISV10F_INSN_ANDCWR, CRISV10F_INSN_ANDCDR, CRISV10F_INSN_ANDQ, CRISV10F_INSN_ORR_B_R
|
||||
, CRISV10F_INSN_ORR_W_R, CRISV10F_INSN_ORR_D_R, CRISV10F_INSN_OR_M_B_M, CRISV10F_INSN_OR_M_W_M
|
||||
, CRISV10F_INSN_OR_M_D_M, CRISV10F_INSN_ORCBR, CRISV10F_INSN_ORCWR, CRISV10F_INSN_ORCDR
|
||||
, CRISV10F_INSN_ORQ, CRISV10F_INSN_XOR, CRISV10F_INSN_SWAP, CRISV10F_INSN_ASRR_B_R
|
||||
, CRISV10F_INSN_ASRR_W_R, CRISV10F_INSN_ASRR_D_R, CRISV10F_INSN_ASRQ, CRISV10F_INSN_LSRR_B_R
|
||||
, CRISV10F_INSN_LSRR_W_R, CRISV10F_INSN_LSRR_D_R, CRISV10F_INSN_LSRQ, CRISV10F_INSN_LSLR_B_R
|
||||
, CRISV10F_INSN_LSLR_W_R, CRISV10F_INSN_LSLR_D_R, CRISV10F_INSN_LSLQ, CRISV10F_INSN_BTST
|
||||
, CRISV10F_INSN_BTSTQ, CRISV10F_INSN_SETF, CRISV10F_INSN_CLEARF, CRISV10F_INSN_BCC_B
|
||||
, CRISV10F_INSN_BA_B, CRISV10F_INSN_BCC_W, CRISV10F_INSN_BA_W, CRISV10F_INSN_JUMP_R
|
||||
, CRISV10F_INSN_JUMP_M, CRISV10F_INSN_JUMP_C, CRISV10F_INSN_BREAK, CRISV10F_INSN_BOUND_R_B_R
|
||||
, CRISV10F_INSN_BOUND_R_W_R, CRISV10F_INSN_BOUND_R_D_R, CRISV10F_INSN_BOUND_M_B_M, CRISV10F_INSN_BOUND_M_W_M
|
||||
, CRISV10F_INSN_BOUND_M_D_M, CRISV10F_INSN_BOUND_CB, CRISV10F_INSN_BOUND_CW, CRISV10F_INSN_BOUND_CD
|
||||
, CRISV10F_INSN_SCC, CRISV10F_INSN_LZ, CRISV10F_INSN_ADDOQ, CRISV10F_INSN_BDAPQPC
|
||||
, CRISV10F_INSN_ADDO_M_B_M, CRISV10F_INSN_ADDO_M_W_M, CRISV10F_INSN_ADDO_M_D_M, CRISV10F_INSN_ADDO_CB
|
||||
, CRISV10F_INSN_ADDO_CW, CRISV10F_INSN_ADDO_CD, CRISV10F_INSN_DIP_M, CRISV10F_INSN_DIP_C
|
||||
, CRISV10F_INSN_ADDI_ACR_B_R, CRISV10F_INSN_ADDI_ACR_W_R, CRISV10F_INSN_ADDI_ACR_D_R, CRISV10F_INSN_BIAP_PC_B_R
|
||||
, CRISV10F_INSN_BIAP_PC_W_R, CRISV10F_INSN_BIAP_PC_D_R, CRISV10F_INSN__MAX
|
||||
} CRISV10F_INSN_TYPE;
|
||||
|
||||
/* Enum declaration for semantic formats in cpu family crisv10f. */
|
||||
typedef enum crisv10f_sfmt_type {
|
||||
CRISV10F_SFMT_EMPTY, CRISV10F_SFMT_NOP, CRISV10F_SFMT_MOVE_B_R, CRISV10F_SFMT_MOVE_D_R
|
||||
, CRISV10F_SFMT_MOVEPCR, CRISV10F_SFMT_MOVEQ, CRISV10F_SFMT_MOVS_B_R, CRISV10F_SFMT_MOVECBR
|
||||
, CRISV10F_SFMT_MOVECWR, CRISV10F_SFMT_MOVECDR, CRISV10F_SFMT_MOVSCBR, CRISV10F_SFMT_MOVSCWR
|
||||
, CRISV10F_SFMT_MOVUCBR, CRISV10F_SFMT_MOVUCWR, CRISV10F_SFMT_ADDQ, CRISV10F_SFMT_CMP_R_B_R
|
||||
, CRISV10F_SFMT_CMP_M_B_M, CRISV10F_SFMT_CMP_M_W_M, CRISV10F_SFMT_CMP_M_D_M, CRISV10F_SFMT_CMPCBR
|
||||
, CRISV10F_SFMT_CMPCWR, CRISV10F_SFMT_CMPCDR, CRISV10F_SFMT_CMPQ, CRISV10F_SFMT_CMPUCBR
|
||||
, CRISV10F_SFMT_CMPUCWR, CRISV10F_SFMT_MOVE_M_B_M, CRISV10F_SFMT_MOVE_M_W_M, CRISV10F_SFMT_MOVE_M_D_M
|
||||
, CRISV10F_SFMT_MOVS_M_B_M, CRISV10F_SFMT_MOVS_M_W_M, CRISV10F_SFMT_MOVE_R_SPRV10, CRISV10F_SFMT_MOVE_SPR_RV10
|
||||
, CRISV10F_SFMT_RET_TYPE, CRISV10F_SFMT_MOVE_M_SPRV10, CRISV10F_SFMT_MOVE_C_SPRV10_P0, CRISV10F_SFMT_MOVE_C_SPRV10_P4
|
||||
, CRISV10F_SFMT_MOVE_C_SPRV10_P8, CRISV10F_SFMT_MOVE_SPR_MV10, CRISV10F_SFMT_SBFS, CRISV10F_SFMT_MOVEM_R_M
|
||||
, CRISV10F_SFMT_MOVEM_M_R, CRISV10F_SFMT_MOVEM_M_PC, CRISV10F_SFMT_ADD_B_R, CRISV10F_SFMT_ADD_D_R
|
||||
, CRISV10F_SFMT_ADD_M_B_M, CRISV10F_SFMT_ADD_M_W_M, CRISV10F_SFMT_ADD_M_D_M, CRISV10F_SFMT_ADDCBR
|
||||
, CRISV10F_SFMT_ADDCWR, CRISV10F_SFMT_ADDCDR, CRISV10F_SFMT_ADDCPC, CRISV10F_SFMT_ADDS_M_B_M
|
||||
, CRISV10F_SFMT_ADDS_M_W_M, CRISV10F_SFMT_ADDSCBR, CRISV10F_SFMT_ADDSCWR, CRISV10F_SFMT_ADDSPCPC
|
||||
, CRISV10F_SFMT_ADDI_B_R, CRISV10F_SFMT_NEG_B_R, CRISV10F_SFMT_NEG_D_R, CRISV10F_SFMT_TEST_M_B_M
|
||||
, CRISV10F_SFMT_TEST_M_W_M, CRISV10F_SFMT_TEST_M_D_M, CRISV10F_SFMT_MOVE_R_M_B_M, CRISV10F_SFMT_MOVE_R_M_W_M
|
||||
, CRISV10F_SFMT_MOVE_R_M_D_M, CRISV10F_SFMT_MULS_B, CRISV10F_SFMT_MSTEP, CRISV10F_SFMT_DSTEP
|
||||
, CRISV10F_SFMT_AND_B_R, CRISV10F_SFMT_AND_W_R, CRISV10F_SFMT_AND_D_R, CRISV10F_SFMT_AND_M_B_M
|
||||
, CRISV10F_SFMT_AND_M_W_M, CRISV10F_SFMT_AND_M_D_M, CRISV10F_SFMT_ANDCBR, CRISV10F_SFMT_ANDCWR
|
||||
, CRISV10F_SFMT_ANDCDR, CRISV10F_SFMT_ANDQ, CRISV10F_SFMT_SWAP, CRISV10F_SFMT_ASRR_B_R
|
||||
, CRISV10F_SFMT_ASRQ, CRISV10F_SFMT_LSRR_B_R, CRISV10F_SFMT_LSRR_D_R, CRISV10F_SFMT_BTST
|
||||
, CRISV10F_SFMT_BTSTQ, CRISV10F_SFMT_SETF, CRISV10F_SFMT_BCC_B, CRISV10F_SFMT_BA_B
|
||||
, CRISV10F_SFMT_BCC_W, CRISV10F_SFMT_BA_W, CRISV10F_SFMT_JUMP_R, CRISV10F_SFMT_JUMP_M
|
||||
, CRISV10F_SFMT_JUMP_C, CRISV10F_SFMT_BREAK, CRISV10F_SFMT_BOUND_M_B_M, CRISV10F_SFMT_BOUND_M_W_M
|
||||
, CRISV10F_SFMT_BOUND_M_D_M, CRISV10F_SFMT_BOUND_CB, CRISV10F_SFMT_BOUND_CW, CRISV10F_SFMT_BOUND_CD
|
||||
, CRISV10F_SFMT_SCC, CRISV10F_SFMT_ADDOQ, CRISV10F_SFMT_BDAPQPC, CRISV10F_SFMT_ADDO_M_B_M
|
||||
, CRISV10F_SFMT_ADDO_M_W_M, CRISV10F_SFMT_ADDO_M_D_M, CRISV10F_SFMT_ADDO_CB, CRISV10F_SFMT_ADDO_CW
|
||||
, CRISV10F_SFMT_ADDO_CD, CRISV10F_SFMT_DIP_M, CRISV10F_SFMT_DIP_C, CRISV10F_SFMT_ADDI_ACR_B_R
|
||||
, CRISV10F_SFMT_BIAP_PC_B_R
|
||||
} CRISV10F_SFMT_TYPE;
|
||||
|
||||
/* Function unit handlers (user written). */
|
||||
|
||||
extern int crisv10f_model_crisv10_u_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/);
|
||||
extern int crisv10f_model_crisv10_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv10f_model_crisv10_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv10f_model_crisv10_u_stall (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv10f_model_crisv10_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv10f_model_crisv10_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv10f_model_crisv10_u_mem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv10f_model_crisv10_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
|
||||
/* Profiling before/after handlers (user written) */
|
||||
|
||||
extern void crisv10f_model_insn_before (SIM_CPU *, int /*first_p*/);
|
||||
extern void crisv10f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
|
||||
|
||||
#endif /* CRISV10F_DECODE_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,150 @@
|
|||
/* Decode header for crisv32f.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CRISV32F_DECODE_H
|
||||
#define CRISV32F_DECODE_H
|
||||
|
||||
extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
|
||||
CGEN_INSN_INT,
|
||||
ARGBUF *);
|
||||
extern void crisv32f_init_idesc_table (SIM_CPU *);
|
||||
extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
|
||||
extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
|
||||
|
||||
/* Enum declaration for instructions in cpu family crisv32f. */
|
||||
typedef enum crisv32f_insn_type {
|
||||
CRISV32F_INSN_X_INVALID, CRISV32F_INSN_X_AFTER, CRISV32F_INSN_X_BEFORE, CRISV32F_INSN_X_CTI_CHAIN
|
||||
, CRISV32F_INSN_X_CHAIN, CRISV32F_INSN_X_BEGIN, CRISV32F_INSN_MOVE_B_R, CRISV32F_INSN_MOVE_W_R
|
||||
, CRISV32F_INSN_MOVE_D_R, CRISV32F_INSN_MOVEQ, CRISV32F_INSN_MOVS_B_R, CRISV32F_INSN_MOVS_W_R
|
||||
, CRISV32F_INSN_MOVU_B_R, CRISV32F_INSN_MOVU_W_R, CRISV32F_INSN_MOVECBR, CRISV32F_INSN_MOVECWR
|
||||
, CRISV32F_INSN_MOVECDR, CRISV32F_INSN_MOVSCBR, CRISV32F_INSN_MOVSCWR, CRISV32F_INSN_MOVUCBR
|
||||
, CRISV32F_INSN_MOVUCWR, CRISV32F_INSN_ADDQ, CRISV32F_INSN_SUBQ, CRISV32F_INSN_CMP_R_B_R
|
||||
, CRISV32F_INSN_CMP_R_W_R, CRISV32F_INSN_CMP_R_D_R, CRISV32F_INSN_CMP_M_B_M, CRISV32F_INSN_CMP_M_W_M
|
||||
, CRISV32F_INSN_CMP_M_D_M, CRISV32F_INSN_CMPCBR, CRISV32F_INSN_CMPCWR, CRISV32F_INSN_CMPCDR
|
||||
, CRISV32F_INSN_CMPQ, CRISV32F_INSN_CMPS_M_B_M, CRISV32F_INSN_CMPS_M_W_M, CRISV32F_INSN_CMPSCBR
|
||||
, CRISV32F_INSN_CMPSCWR, CRISV32F_INSN_CMPU_M_B_M, CRISV32F_INSN_CMPU_M_W_M, CRISV32F_INSN_CMPUCBR
|
||||
, CRISV32F_INSN_CMPUCWR, CRISV32F_INSN_MOVE_M_B_M, CRISV32F_INSN_MOVE_M_W_M, CRISV32F_INSN_MOVE_M_D_M
|
||||
, CRISV32F_INSN_MOVS_M_B_M, CRISV32F_INSN_MOVS_M_W_M, CRISV32F_INSN_MOVU_M_B_M, CRISV32F_INSN_MOVU_M_W_M
|
||||
, CRISV32F_INSN_MOVE_R_SPRV32, CRISV32F_INSN_MOVE_SPR_RV32, CRISV32F_INSN_MOVE_M_SPRV32, CRISV32F_INSN_MOVE_C_SPRV32_P0
|
||||
, CRISV32F_INSN_MOVE_C_SPRV32_P1, CRISV32F_INSN_MOVE_C_SPRV32_P2, CRISV32F_INSN_MOVE_C_SPRV32_P3, CRISV32F_INSN_MOVE_C_SPRV32_P4
|
||||
, CRISV32F_INSN_MOVE_C_SPRV32_P5, CRISV32F_INSN_MOVE_C_SPRV32_P6, CRISV32F_INSN_MOVE_C_SPRV32_P7, CRISV32F_INSN_MOVE_C_SPRV32_P8
|
||||
, CRISV32F_INSN_MOVE_C_SPRV32_P9, CRISV32F_INSN_MOVE_C_SPRV32_P10, CRISV32F_INSN_MOVE_C_SPRV32_P11, CRISV32F_INSN_MOVE_C_SPRV32_P12
|
||||
, CRISV32F_INSN_MOVE_C_SPRV32_P13, CRISV32F_INSN_MOVE_C_SPRV32_P14, CRISV32F_INSN_MOVE_C_SPRV32_P15, CRISV32F_INSN_MOVE_SPR_MV32
|
||||
, CRISV32F_INSN_MOVE_SS_R, CRISV32F_INSN_MOVE_R_SS, CRISV32F_INSN_MOVEM_R_M_V32, CRISV32F_INSN_MOVEM_M_R_V32
|
||||
, CRISV32F_INSN_ADD_B_R, CRISV32F_INSN_ADD_W_R, CRISV32F_INSN_ADD_D_R, CRISV32F_INSN_ADD_M_B_M
|
||||
, CRISV32F_INSN_ADD_M_W_M, CRISV32F_INSN_ADD_M_D_M, CRISV32F_INSN_ADDCBR, CRISV32F_INSN_ADDCWR
|
||||
, CRISV32F_INSN_ADDCDR, CRISV32F_INSN_ADDS_B_R, CRISV32F_INSN_ADDS_W_R, CRISV32F_INSN_ADDS_M_B_M
|
||||
, CRISV32F_INSN_ADDS_M_W_M, CRISV32F_INSN_ADDSCBR, CRISV32F_INSN_ADDSCWR, CRISV32F_INSN_ADDU_B_R
|
||||
, CRISV32F_INSN_ADDU_W_R, CRISV32F_INSN_ADDU_M_B_M, CRISV32F_INSN_ADDU_M_W_M, CRISV32F_INSN_ADDUCBR
|
||||
, CRISV32F_INSN_ADDUCWR, CRISV32F_INSN_SUB_B_R, CRISV32F_INSN_SUB_W_R, CRISV32F_INSN_SUB_D_R
|
||||
, CRISV32F_INSN_SUB_M_B_M, CRISV32F_INSN_SUB_M_W_M, CRISV32F_INSN_SUB_M_D_M, CRISV32F_INSN_SUBCBR
|
||||
, CRISV32F_INSN_SUBCWR, CRISV32F_INSN_SUBCDR, CRISV32F_INSN_SUBS_B_R, CRISV32F_INSN_SUBS_W_R
|
||||
, CRISV32F_INSN_SUBS_M_B_M, CRISV32F_INSN_SUBS_M_W_M, CRISV32F_INSN_SUBSCBR, CRISV32F_INSN_SUBSCWR
|
||||
, CRISV32F_INSN_SUBU_B_R, CRISV32F_INSN_SUBU_W_R, CRISV32F_INSN_SUBU_M_B_M, CRISV32F_INSN_SUBU_M_W_M
|
||||
, CRISV32F_INSN_SUBUCBR, CRISV32F_INSN_SUBUCWR, CRISV32F_INSN_ADDC_R, CRISV32F_INSN_ADDC_M
|
||||
, CRISV32F_INSN_ADDC_C, CRISV32F_INSN_LAPC_D, CRISV32F_INSN_LAPCQ, CRISV32F_INSN_ADDI_B_R
|
||||
, CRISV32F_INSN_ADDI_W_R, CRISV32F_INSN_ADDI_D_R, CRISV32F_INSN_NEG_B_R, CRISV32F_INSN_NEG_W_R
|
||||
, CRISV32F_INSN_NEG_D_R, CRISV32F_INSN_TEST_M_B_M, CRISV32F_INSN_TEST_M_W_M, CRISV32F_INSN_TEST_M_D_M
|
||||
, CRISV32F_INSN_MOVE_R_M_B_M, CRISV32F_INSN_MOVE_R_M_W_M, CRISV32F_INSN_MOVE_R_M_D_M, CRISV32F_INSN_MULS_B
|
||||
, CRISV32F_INSN_MULS_W, CRISV32F_INSN_MULS_D, CRISV32F_INSN_MULU_B, CRISV32F_INSN_MULU_W
|
||||
, CRISV32F_INSN_MULU_D, CRISV32F_INSN_MCP, CRISV32F_INSN_DSTEP, CRISV32F_INSN_ABS
|
||||
, CRISV32F_INSN_AND_B_R, CRISV32F_INSN_AND_W_R, CRISV32F_INSN_AND_D_R, CRISV32F_INSN_AND_M_B_M
|
||||
, CRISV32F_INSN_AND_M_W_M, CRISV32F_INSN_AND_M_D_M, CRISV32F_INSN_ANDCBR, CRISV32F_INSN_ANDCWR
|
||||
, CRISV32F_INSN_ANDCDR, CRISV32F_INSN_ANDQ, CRISV32F_INSN_ORR_B_R, CRISV32F_INSN_ORR_W_R
|
||||
, CRISV32F_INSN_ORR_D_R, CRISV32F_INSN_OR_M_B_M, CRISV32F_INSN_OR_M_W_M, CRISV32F_INSN_OR_M_D_M
|
||||
, CRISV32F_INSN_ORCBR, CRISV32F_INSN_ORCWR, CRISV32F_INSN_ORCDR, CRISV32F_INSN_ORQ
|
||||
, CRISV32F_INSN_XOR, CRISV32F_INSN_SWAP, CRISV32F_INSN_ASRR_B_R, CRISV32F_INSN_ASRR_W_R
|
||||
, CRISV32F_INSN_ASRR_D_R, CRISV32F_INSN_ASRQ, CRISV32F_INSN_LSRR_B_R, CRISV32F_INSN_LSRR_W_R
|
||||
, CRISV32F_INSN_LSRR_D_R, CRISV32F_INSN_LSRQ, CRISV32F_INSN_LSLR_B_R, CRISV32F_INSN_LSLR_W_R
|
||||
, CRISV32F_INSN_LSLR_D_R, CRISV32F_INSN_LSLQ, CRISV32F_INSN_BTST, CRISV32F_INSN_BTSTQ
|
||||
, CRISV32F_INSN_SETF, CRISV32F_INSN_CLEARF, CRISV32F_INSN_RFE, CRISV32F_INSN_SFE
|
||||
, CRISV32F_INSN_RFG, CRISV32F_INSN_RFN, CRISV32F_INSN_HALT, CRISV32F_INSN_BCC_B
|
||||
, CRISV32F_INSN_BA_B, CRISV32F_INSN_BCC_W, CRISV32F_INSN_BA_W, CRISV32F_INSN_JAS_R
|
||||
, CRISV32F_INSN_JAS_C, CRISV32F_INSN_JUMP_P, CRISV32F_INSN_BAS_C, CRISV32F_INSN_JASC_R
|
||||
, CRISV32F_INSN_JASC_C, CRISV32F_INSN_BASC_C, CRISV32F_INSN_BREAK, CRISV32F_INSN_BOUND_R_B_R
|
||||
, CRISV32F_INSN_BOUND_R_W_R, CRISV32F_INSN_BOUND_R_D_R, CRISV32F_INSN_BOUND_CB, CRISV32F_INSN_BOUND_CW
|
||||
, CRISV32F_INSN_BOUND_CD, CRISV32F_INSN_SCC, CRISV32F_INSN_LZ, CRISV32F_INSN_ADDOQ
|
||||
, CRISV32F_INSN_ADDO_M_B_M, CRISV32F_INSN_ADDO_M_W_M, CRISV32F_INSN_ADDO_M_D_M, CRISV32F_INSN_ADDO_CB
|
||||
, CRISV32F_INSN_ADDO_CW, CRISV32F_INSN_ADDO_CD, CRISV32F_INSN_ADDI_ACR_B_R, CRISV32F_INSN_ADDI_ACR_W_R
|
||||
, CRISV32F_INSN_ADDI_ACR_D_R, CRISV32F_INSN_FIDXI, CRISV32F_INSN_FTAGI, CRISV32F_INSN_FIDXD
|
||||
, CRISV32F_INSN_FTAGD, CRISV32F_INSN__MAX
|
||||
} CRISV32F_INSN_TYPE;
|
||||
|
||||
/* Enum declaration for semantic formats in cpu family crisv32f. */
|
||||
typedef enum crisv32f_sfmt_type {
|
||||
CRISV32F_SFMT_EMPTY, CRISV32F_SFMT_MOVE_B_R, CRISV32F_SFMT_MOVE_D_R, CRISV32F_SFMT_MOVEQ
|
||||
, CRISV32F_SFMT_MOVS_B_R, CRISV32F_SFMT_MOVECBR, CRISV32F_SFMT_MOVECWR, CRISV32F_SFMT_MOVECDR
|
||||
, CRISV32F_SFMT_MOVSCBR, CRISV32F_SFMT_MOVSCWR, CRISV32F_SFMT_MOVUCBR, CRISV32F_SFMT_MOVUCWR
|
||||
, CRISV32F_SFMT_ADDQ, CRISV32F_SFMT_CMP_R_B_R, CRISV32F_SFMT_CMP_M_B_M, CRISV32F_SFMT_CMP_M_W_M
|
||||
, CRISV32F_SFMT_CMP_M_D_M, CRISV32F_SFMT_CMPCBR, CRISV32F_SFMT_CMPCWR, CRISV32F_SFMT_CMPCDR
|
||||
, CRISV32F_SFMT_CMPQ, CRISV32F_SFMT_CMPUCBR, CRISV32F_SFMT_CMPUCWR, CRISV32F_SFMT_MOVE_M_B_M
|
||||
, CRISV32F_SFMT_MOVE_M_W_M, CRISV32F_SFMT_MOVE_M_D_M, CRISV32F_SFMT_MOVS_M_B_M, CRISV32F_SFMT_MOVS_M_W_M
|
||||
, CRISV32F_SFMT_MOVE_R_SPRV32, CRISV32F_SFMT_MOVE_SPR_RV32, CRISV32F_SFMT_MOVE_M_SPRV32, CRISV32F_SFMT_MOVE_C_SPRV32_P0
|
||||
, CRISV32F_SFMT_MOVE_SPR_MV32, CRISV32F_SFMT_MOVE_SS_R, CRISV32F_SFMT_MOVE_R_SS, CRISV32F_SFMT_MOVEM_R_M_V32
|
||||
, CRISV32F_SFMT_MOVEM_M_R_V32, CRISV32F_SFMT_ADD_B_R, CRISV32F_SFMT_ADD_D_R, CRISV32F_SFMT_ADD_M_B_M
|
||||
, CRISV32F_SFMT_ADD_M_W_M, CRISV32F_SFMT_ADD_M_D_M, CRISV32F_SFMT_ADDCBR, CRISV32F_SFMT_ADDCWR
|
||||
, CRISV32F_SFMT_ADDCDR, CRISV32F_SFMT_ADDS_M_B_M, CRISV32F_SFMT_ADDS_M_W_M, CRISV32F_SFMT_ADDSCBR
|
||||
, CRISV32F_SFMT_ADDSCWR, CRISV32F_SFMT_ADDC_M, CRISV32F_SFMT_LAPC_D, CRISV32F_SFMT_LAPCQ
|
||||
, CRISV32F_SFMT_ADDI_B_R, CRISV32F_SFMT_NEG_B_R, CRISV32F_SFMT_NEG_D_R, CRISV32F_SFMT_TEST_M_B_M
|
||||
, CRISV32F_SFMT_TEST_M_W_M, CRISV32F_SFMT_TEST_M_D_M, CRISV32F_SFMT_MOVE_R_M_B_M, CRISV32F_SFMT_MOVE_R_M_W_M
|
||||
, CRISV32F_SFMT_MOVE_R_M_D_M, CRISV32F_SFMT_MULS_B, CRISV32F_SFMT_MCP, CRISV32F_SFMT_DSTEP
|
||||
, CRISV32F_SFMT_AND_B_R, CRISV32F_SFMT_AND_W_R, CRISV32F_SFMT_AND_D_R, CRISV32F_SFMT_AND_M_B_M
|
||||
, CRISV32F_SFMT_AND_M_W_M, CRISV32F_SFMT_AND_M_D_M, CRISV32F_SFMT_ANDCBR, CRISV32F_SFMT_ANDCWR
|
||||
, CRISV32F_SFMT_ANDCDR, CRISV32F_SFMT_ANDQ, CRISV32F_SFMT_SWAP, CRISV32F_SFMT_ASRR_B_R
|
||||
, CRISV32F_SFMT_ASRQ, CRISV32F_SFMT_LSRR_B_R, CRISV32F_SFMT_LSRR_D_R, CRISV32F_SFMT_BTST
|
||||
, CRISV32F_SFMT_BTSTQ, CRISV32F_SFMT_SETF, CRISV32F_SFMT_RFE, CRISV32F_SFMT_SFE
|
||||
, CRISV32F_SFMT_RFG, CRISV32F_SFMT_RFN, CRISV32F_SFMT_HALT, CRISV32F_SFMT_BCC_B
|
||||
, CRISV32F_SFMT_BA_B, CRISV32F_SFMT_BCC_W, CRISV32F_SFMT_BA_W, CRISV32F_SFMT_JAS_R
|
||||
, CRISV32F_SFMT_JAS_C, CRISV32F_SFMT_JUMP_P, CRISV32F_SFMT_BAS_C, CRISV32F_SFMT_JASC_R
|
||||
, CRISV32F_SFMT_BREAK, CRISV32F_SFMT_BOUND_CB, CRISV32F_SFMT_BOUND_CW, CRISV32F_SFMT_BOUND_CD
|
||||
, CRISV32F_SFMT_SCC, CRISV32F_SFMT_ADDOQ, CRISV32F_SFMT_ADDO_M_B_M, CRISV32F_SFMT_ADDO_M_W_M
|
||||
, CRISV32F_SFMT_ADDO_M_D_M, CRISV32F_SFMT_ADDO_CB, CRISV32F_SFMT_ADDO_CW, CRISV32F_SFMT_ADDO_CD
|
||||
, CRISV32F_SFMT_ADDI_ACR_B_R, CRISV32F_SFMT_FIDXI
|
||||
} CRISV32F_SFMT_TYPE;
|
||||
|
||||
/* Function unit handlers (user written). */
|
||||
|
||||
extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
|
||||
extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
|
||||
extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
|
||||
extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
|
||||
extern int crisv32f_model_crisv32_u_jump_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ps*/);
|
||||
extern int crisv32f_model_crisv32_u_jump_r (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/);
|
||||
extern int crisv32f_model_crisv32_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv32f_model_crisv32_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
|
||||
extern int crisv32f_model_crisv32_u_movem_mtor (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
|
||||
extern int crisv32f_model_crisv32_u_movem_rtom (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
|
||||
extern int crisv32f_model_crisv32_u_mem_w (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv32f_model_crisv32_u_mem_r (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
extern int crisv32f_model_crisv32_u_mem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/);
|
||||
|
||||
/* Profiling before/after handlers (user written) */
|
||||
|
||||
extern void crisv32f_model_insn_before (SIM_CPU *, int /*first_p*/);
|
||||
extern void crisv32f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
|
||||
|
||||
#endif /* CRISV32F_DECODE_H */
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/* CRIS device support
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* Based on the i960 devices.c (for the purposes, the same as all the
|
||||
others). */
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
#ifdef HAVE_DV_SOCKSER
|
||||
#include "dv-sockser.h"
|
||||
#endif
|
||||
|
||||
/* Placeholder definition. */
|
||||
struct _device { char dummy; } cris_devices;
|
||||
|
||||
void
|
||||
device_error (device *me ATTRIBUTE_UNUSED,
|
||||
char *message ATTRIBUTE_UNUSED,
|
||||
...)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
int
|
||||
device_io_read_buffer (device *me ATTRIBUTE_UNUSED,
|
||||
void *source ATTRIBUTE_UNUSED,
|
||||
int space ATTRIBUTE_UNUSED,
|
||||
address_word addr ATTRIBUTE_UNUSED,
|
||||
unsigned nr_bytes ATTRIBUTE_UNUSED,
|
||||
SIM_DESC sd ATTRIBUTE_UNUSED,
|
||||
SIM_CPU *cpu ATTRIBUTE_UNUSED,
|
||||
sim_cia cia ATTRIBUTE_UNUSED)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
int
|
||||
device_io_write_buffer (device *me ATTRIBUTE_UNUSED,
|
||||
const void *source,
|
||||
int space ATTRIBUTE_UNUSED,
|
||||
address_word addr, unsigned nr_bytes,
|
||||
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
|
||||
{
|
||||
static const unsigned char ok[] = { 4, 0, 0, 0x90};
|
||||
static const unsigned char bad[] = { 8, 0, 0, 0x90};
|
||||
|
||||
if (addr == 0x90000004 && memcmp (source, ok, sizeof ok) == 0)
|
||||
cris_break_13_handler (cpu, 1, 0, 0, 0, 0, 0, 0, cia);
|
||||
else if (addr == 0x90000008
|
||||
&& memcmp (source, bad, sizeof bad) == 0)
|
||||
cris_break_13_handler (cpu, 1, 34, 0, 0, 0, 0, 0, cia);
|
||||
|
||||
/* If it wasn't one of those, send an invalid-memory signal. */
|
||||
sim_core_signal (sd, cpu, cia, 0, nr_bytes, addr,
|
||||
write_transfer, sim_core_unmapped_signal);
|
||||
}
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
# Simulator main loop for CRIS. -*- C -*-
|
||||
# Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
# Contributed by Axis Communications.
|
||||
#
|
||||
# This file is part of the GNU simulators.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License along
|
||||
# with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
# Based on the fr30 file.
|
||||
|
||||
# Syntax:
|
||||
# /bin/sh mainloop.in command
|
||||
#
|
||||
# Command is one of:
|
||||
#
|
||||
# init
|
||||
# support
|
||||
# extract-{simple,scache,pbb}
|
||||
# {full,fast}-exec-{simple,scache,pbb}
|
||||
#
|
||||
# A target need only provide a "full" version of one of simple,scache,pbb.
|
||||
# If the target wants it can also provide a fast version of same.
|
||||
# It can't provide more than this, however for illustration's sake the CRIS
|
||||
# port provides examples of all.
|
||||
|
||||
# ??? After a few more ports are done, revisit.
|
||||
# Will eventually need to machine generate a lot of this.
|
||||
|
||||
case "x$1" in
|
||||
|
||||
xsupport)
|
||||
|
||||
cat <<EOF
|
||||
/* It seems we don't have a templated header file corresponding to
|
||||
cris-tmpl.c, so we have to get out declarations the hackish way. */
|
||||
extern void @cpu@_specific_init (SIM_CPU *current_cpu);
|
||||
|
||||
static INLINE const IDESC *
|
||||
extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
|
||||
int fast_p)
|
||||
{
|
||||
const IDESC *id = @cpu@_decode (current_cpu, pc, insn,
|
||||
#if CGEN_INT_INSN_P
|
||||
insn,
|
||||
#endif
|
||||
abuf);
|
||||
@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
|
||||
if (! fast_p)
|
||||
{
|
||||
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
|
||||
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
|
||||
@cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
|
||||
}
|
||||
return id;
|
||||
}
|
||||
|
||||
static INLINE SEM_PC
|
||||
execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
|
||||
{
|
||||
SEM_PC vpc;
|
||||
|
||||
if (fast_p)
|
||||
{
|
||||
#if ! WITH_SEM_SWITCH_FAST
|
||||
#if WITH_SCACHE
|
||||
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
|
||||
#else
|
||||
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
|
||||
#endif
|
||||
#else
|
||||
abort ();
|
||||
#endif /* WITH_SEM_SWITCH_FAST */
|
||||
}
|
||||
else
|
||||
{
|
||||
#if ! WITH_SEM_SWITCH_FULL
|
||||
ARGBUF *abuf = &sc->argbuf;
|
||||
const IDESC *idesc = abuf->idesc;
|
||||
#if WITH_SCACHE_PBB
|
||||
int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
|
||||
#else
|
||||
int virtual_p = 0;
|
||||
#endif
|
||||
|
||||
if (! virtual_p)
|
||||
{
|
||||
/* FIXME: call x-before */
|
||||
if (ARGBUF_PROFILE_P (abuf))
|
||||
PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
|
||||
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
|
||||
if (PROFILE_MODEL_P (current_cpu)
|
||||
&& ARGBUF_PROFILE_P (abuf))
|
||||
@cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
|
||||
TRACE_INSN_INIT (current_cpu, abuf, 1);
|
||||
TRACE_INSN (current_cpu, idesc->idata,
|
||||
(const struct argbuf *) abuf, abuf->addr);
|
||||
}
|
||||
#if WITH_SCACHE
|
||||
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
|
||||
#else
|
||||
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
|
||||
#endif
|
||||
if (! virtual_p)
|
||||
{
|
||||
/* FIXME: call x-after */
|
||||
if (PROFILE_MODEL_P (current_cpu)
|
||||
&& ARGBUF_PROFILE_P (abuf))
|
||||
{
|
||||
int cycles;
|
||||
|
||||
cycles = (*idesc->timing->model_fn) (current_cpu, sc);
|
||||
@cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
|
||||
}
|
||||
TRACE_INSN_FINI (current_cpu, abuf, 1);
|
||||
}
|
||||
#else
|
||||
abort ();
|
||||
#endif /* WITH_SEM_SWITCH_FULL */
|
||||
}
|
||||
|
||||
return vpc;
|
||||
}
|
||||
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xinit)
|
||||
|
||||
cat <<EOF
|
||||
/* This seemed the only sane location to emit a call to a
|
||||
model-specific init function. It may not work for all simulator
|
||||
types. FIXME: Introduce a model-init hook. */
|
||||
|
||||
/* We use the same condition as the code that's expected to follow, so
|
||||
GCC can consolidate the code with only one conditional. */
|
||||
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
|
||||
@cpu@_specific_init (current_cpu);
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xextract-simple | xextract-scache)
|
||||
|
||||
# Inputs: current_cpu, vpc, sc, FAST_P
|
||||
# Outputs: sc filled in
|
||||
|
||||
cat <<EOF
|
||||
{
|
||||
CGEN_INSN_INT insn = GETIMEMUHI (current_cpu, vpc);
|
||||
extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
|
||||
}
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xextract-pbb)
|
||||
|
||||
# Inputs: current_cpu, pc, sc, max_insns, FAST_P
|
||||
# Outputs: sc, pc
|
||||
# sc must be left pointing past the last created entry.
|
||||
# pc must be left pointing past the last created entry.
|
||||
# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
|
||||
# to record the vpc of the cti insn.
|
||||
# SET_INSN_COUNT(n) must be called to record number of real insns.
|
||||
|
||||
cat <<EOF
|
||||
{
|
||||
const IDESC *idesc;
|
||||
int icount = 0;
|
||||
|
||||
/* Make sure the buffer doesn't overflow for profiled insns if
|
||||
max_insns happens to not be a multiple of 3. */
|
||||
if (!FAST_P)
|
||||
max_insns -= 2 + 3;
|
||||
else
|
||||
/* There might be two real insns handled per loop. */
|
||||
max_insns--;
|
||||
|
||||
while (max_insns > 0)
|
||||
{
|
||||
UHI insn = GETIMEMUHI (current_cpu, pc);
|
||||
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
|
||||
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
|
||||
int befaft_p = profile_p || trace_p;
|
||||
|
||||
if (befaft_p)
|
||||
{
|
||||
@cpu@_emit_before (current_cpu, sc, pc, 1);
|
||||
++sc;
|
||||
sc->argbuf.trace_p = trace_p;
|
||||
sc->argbuf.profile_p = profile_p;
|
||||
--max_insns;
|
||||
}
|
||||
|
||||
idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
|
||||
++sc;
|
||||
--max_insns;
|
||||
++icount;
|
||||
|
||||
if (befaft_p)
|
||||
{
|
||||
@cpu@_emit_after (current_cpu, sc, pc);
|
||||
++sc;
|
||||
--max_insns;
|
||||
}
|
||||
|
||||
pc += idesc->length;
|
||||
|
||||
if (IDESC_CTI_P (idesc))
|
||||
{
|
||||
SET_CTI_VPC (sc - 1);
|
||||
|
||||
/* Delay slot? Ignore for zero-instructions (bcc .+2) since
|
||||
those are treated as exit insns to avoid runaway sessions
|
||||
for invalid programs. */
|
||||
if (insn != 0 && CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
|
||||
{
|
||||
UHI insn;
|
||||
trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
|
||||
profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
|
||||
befaft_p = profile_p || trace_p;
|
||||
|
||||
if (befaft_p)
|
||||
{
|
||||
@cpu@_emit_before (current_cpu, sc, pc, 1);
|
||||
++sc;
|
||||
sc->argbuf.trace_p = trace_p;
|
||||
sc->argbuf.profile_p = profile_p;
|
||||
--max_insns;
|
||||
}
|
||||
|
||||
insn = GETIMEMUHI (current_cpu, pc);
|
||||
idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
|
||||
++sc;
|
||||
--max_insns;
|
||||
++icount;
|
||||
|
||||
if (befaft_p)
|
||||
{
|
||||
@cpu@_emit_after (current_cpu, sc, pc);
|
||||
++sc;
|
||||
--max_insns;
|
||||
}
|
||||
pc += idesc->length;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
Finish:
|
||||
SET_INSN_COUNT (icount);
|
||||
}
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xfull-exec-* | xfast-exec-*)
|
||||
|
||||
# Inputs: current_cpu, sc, FAST_P
|
||||
# Outputs: vpc
|
||||
# vpc contains the address of the next insn to execute
|
||||
|
||||
cat <<EOF
|
||||
{
|
||||
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
|
||||
#define DEFINE_SWITCH
|
||||
#include "sem@cpu@-switch.c"
|
||||
#else
|
||||
vpc = execute (current_cpu, vpc, FAST_P);
|
||||
#endif
|
||||
}
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
*)
|
||||
echo "Invalid argument to mainloop.in: $1" >&2
|
||||
exit 1
|
||||
;;
|
||||
|
||||
esac
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,590 @@
|
|||
/* Main simulator entry points specific to the CRIS.
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* Based on the fr30 file, mixing in bits from the i960 and pruning of
|
||||
dead code. */
|
||||
|
||||
#include "libiberty.h"
|
||||
#include "bfd.h"
|
||||
|
||||
#include "sim-main.h"
|
||||
#ifdef HAVE_STDLIB_H
|
||||
#include <stdlib.h>
|
||||
#endif
|
||||
#include "sim-options.h"
|
||||
#include "dis-asm.h"
|
||||
|
||||
/* Apparently the autoconf bits are missing (though HAVE_ENVIRON is used
|
||||
in other dirs; also lacking there). Patch around it for major systems. */
|
||||
#if defined (HAVE_ENVIRON) || defined (__GLIBC__)
|
||||
extern char **environ;
|
||||
#define GET_ENVIRON() environ
|
||||
#else
|
||||
char *missing_environ[] = { "SHELL=/bin/sh", "PATH=/bin:/usr/bin", NULL };
|
||||
#define GET_ENVIRON() missing_environ
|
||||
#endif
|
||||
|
||||
/* AUX vector entries. */
|
||||
#define TARGET_AT_NULL 0
|
||||
#define TARGET_AT_PHDR 3
|
||||
#define TARGET_AT_PHENT 4
|
||||
#define TARGET_AT_PHNUM 5
|
||||
#define TARGET_AT_PAGESZ 6
|
||||
#define TARGET_AT_BASE 7
|
||||
#define TARGET_AT_FLAGS 8
|
||||
#define TARGET_AT_ENTRY 9
|
||||
#define TARGET_AT_UID 11
|
||||
#define TARGET_AT_EUID 12
|
||||
#define TARGET_AT_GID 13
|
||||
#define TARGET_AT_EGID 14
|
||||
#define TARGET_AT_HWCAP 16
|
||||
#define TARGET_AT_CLKTCK 17
|
||||
|
||||
/* Used with get_progbounds to find out how much memory is needed for the
|
||||
program. We don't want to allocate more, since that could mask
|
||||
invalid memory accesses program bugs. */
|
||||
struct progbounds {
|
||||
USI startmem;
|
||||
USI endmem;
|
||||
};
|
||||
|
||||
static void free_state (SIM_DESC);
|
||||
static void get_progbounds (bfd *, asection *, void *);
|
||||
static SIM_RC cris_option_handler (SIM_DESC, sim_cpu *, int, char *, int);
|
||||
|
||||
/* Since we don't build the cgen-opcode table, we use the old
|
||||
disassembler. */
|
||||
static CGEN_DISASSEMBLER cris_disassemble_insn;
|
||||
|
||||
/* By default, we set up stack and environment variables like the Linux
|
||||
kernel. */
|
||||
static char cris_bare_iron = 0;
|
||||
|
||||
/* Whether 0x9000000xx have simulator-specific meanings. */
|
||||
static char cris_have_900000xxif = 0;
|
||||
|
||||
/* Records simulator descriptor so utilities like cris_dump_regs can be
|
||||
called from gdb. */
|
||||
SIM_DESC current_state;
|
||||
|
||||
/* CRIS-specific options. */
|
||||
typedef enum {
|
||||
OPTION_CRIS_STATS = OPTION_START,
|
||||
OPTION_CRIS_TRACE,
|
||||
OPTION_CRIS_NAKED,
|
||||
OPTION_CRIS_900000XXIF,
|
||||
} CRIS_OPTIONS;
|
||||
|
||||
static const OPTION cris_options[] =
|
||||
{
|
||||
{ {"cris-cycles", required_argument, NULL, OPTION_CRIS_STATS},
|
||||
'\0', "basic|unaligned|schedulable|all",
|
||||
"Dump execution statistics",
|
||||
cris_option_handler, NULL },
|
||||
{ {"cris-trace", required_argument, NULL, OPTION_CRIS_TRACE},
|
||||
'\0', "basic",
|
||||
"Emit trace information while running",
|
||||
cris_option_handler, NULL },
|
||||
{ {"cris-naked", no_argument, NULL, OPTION_CRIS_NAKED},
|
||||
'\0', NULL, "Don't set up stack and environment",
|
||||
cris_option_handler, NULL },
|
||||
{ {"cris-900000xx", no_argument, NULL, OPTION_CRIS_900000XXIF},
|
||||
'\0', NULL, "Define addresses at 0x900000xx with simulator semantics",
|
||||
cris_option_handler, NULL },
|
||||
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
|
||||
};
|
||||
|
||||
/* Add the CRIS-specific option list to the simulator. */
|
||||
|
||||
SIM_RC
|
||||
cris_option_install (SIM_DESC sd)
|
||||
{
|
||||
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
|
||||
if (sim_add_option_table (sd, NULL, cris_options) != SIM_RC_OK)
|
||||
return SIM_RC_FAIL;
|
||||
return SIM_RC_OK;
|
||||
}
|
||||
|
||||
/* Handle CRIS-specific options. */
|
||||
|
||||
static SIM_RC
|
||||
cris_option_handler (SIM_DESC sd, sim_cpu *cpu ATTRIBUTE_UNUSED, int opt,
|
||||
char *arg, int is_command ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* The options are CRIS-specific, but cpu-specific option-handling is
|
||||
broken; required to being with "--cpu0-". We store the flags in an
|
||||
unused field in the global state structure and move the flags over
|
||||
to the module-specific CPU data when we store things in the
|
||||
cpu-specific structure. */
|
||||
char *tracefp = STATE_TRACE_FLAGS (sd);
|
||||
|
||||
switch ((CRIS_OPTIONS) opt)
|
||||
{
|
||||
case OPTION_CRIS_STATS:
|
||||
if (strcmp (arg, "basic") == 0)
|
||||
*tracefp = FLAG_CRIS_MISC_PROFILE_SIMPLE;
|
||||
else if (strcmp (arg, "unaligned") == 0)
|
||||
*tracefp
|
||||
= (FLAG_CRIS_MISC_PROFILE_UNALIGNED
|
||||
| FLAG_CRIS_MISC_PROFILE_SIMPLE);
|
||||
else if (strcmp (arg, "schedulable") == 0)
|
||||
*tracefp
|
||||
= (FLAG_CRIS_MISC_PROFILE_SCHEDULABLE
|
||||
| FLAG_CRIS_MISC_PROFILE_SIMPLE);
|
||||
else if (strcmp (arg, "all") == 0)
|
||||
*tracefp = FLAG_CRIS_MISC_PROFILE_ALL;
|
||||
else
|
||||
{
|
||||
/* We'll actually never get here; the caller handles the
|
||||
error case. */
|
||||
sim_io_eprintf (sd, "Unknown option `--cris-stats=%s'\n", arg);
|
||||
return SIM_RC_FAIL;
|
||||
}
|
||||
break;
|
||||
|
||||
case OPTION_CRIS_TRACE:
|
||||
if (strcmp (arg, "basic") == 0)
|
||||
*tracefp |= FLAG_CRIS_MISC_PROFILE_XSIM_TRACE;
|
||||
else
|
||||
{
|
||||
sim_io_eprintf (sd, "Unknown option `--cris-trace=%s'\n", arg);
|
||||
return SIM_RC_FAIL;
|
||||
}
|
||||
break;
|
||||
|
||||
case OPTION_CRIS_NAKED:
|
||||
cris_bare_iron = 1;
|
||||
break;
|
||||
|
||||
case OPTION_CRIS_900000XXIF:
|
||||
cris_have_900000xxif = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
/* We'll actually never get here; the caller handles the error
|
||||
case. */
|
||||
sim_io_eprintf (sd, "Unknown option `%s'\n", arg);
|
||||
return SIM_RC_FAIL;
|
||||
}
|
||||
|
||||
/* Imply --profile-model=on. */
|
||||
return sim_profile_set_option (sd, "-model", PROFILE_MODEL_IDX, "on");
|
||||
}
|
||||
|
||||
/* Cover function of sim_state_free to free the cpu buffers as well. */
|
||||
|
||||
static void
|
||||
free_state (SIM_DESC sd)
|
||||
{
|
||||
if (STATE_MODULES (sd) != NULL)
|
||||
sim_module_uninstall (sd);
|
||||
sim_cpu_free_all (sd);
|
||||
sim_state_free (sd);
|
||||
}
|
||||
|
||||
/* BFD section iterator to find the highest allocated section address
|
||||
(plus one). If we could, we should use the program header table
|
||||
instead, but we can't get to that using bfd. */
|
||||
|
||||
void
|
||||
get_progbounds (bfd *abfd ATTRIBUTE_UNUSED, asection *s, void *vp)
|
||||
{
|
||||
struct progbounds *pbp = (struct progbounds *) vp;
|
||||
|
||||
if ((bfd_get_section_flags (abfd, s) & SEC_ALLOC))
|
||||
{
|
||||
bfd_size_type sec_size = bfd_get_section_size (s);
|
||||
bfd_size_type sec_start = bfd_get_section_vma (abfd, s);
|
||||
bfd_size_type sec_end = sec_start + sec_size;
|
||||
|
||||
if (sec_end > pbp->endmem)
|
||||
pbp->endmem = sec_end;
|
||||
|
||||
if (sec_start < pbp->startmem)
|
||||
pbp->startmem = sec_start;
|
||||
}
|
||||
}
|
||||
|
||||
/* Create an instance of the simulator. */
|
||||
|
||||
SIM_DESC
|
||||
sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
|
||||
char **argv)
|
||||
{
|
||||
char c;
|
||||
int i;
|
||||
USI startmem = 0;
|
||||
USI endmem = CRIS_DEFAULT_MEM_SIZE;
|
||||
USI endbrk = endmem;
|
||||
USI stack_low = 0;
|
||||
SIM_DESC sd = sim_state_alloc (kind, callback);
|
||||
|
||||
/* Can't initialize to "" below. It's either a GCC bug in old
|
||||
releases (up to and including 2.95.3 (.4 in debian) or a bug in the
|
||||
standard ;-) that the rest of the elements won't be initialized. */
|
||||
bfd_byte sp_init[4] = {0, 0, 0, 0};
|
||||
|
||||
/* The cpu data is kept in a separately allocated chunk of memory. */
|
||||
if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
|
||||
{
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
|
||||
{
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* getopt will print the error message so we just have to exit if this fails.
|
||||
FIXME: Hmmm... in the case of gdb we need getopt to call
|
||||
print_filtered. */
|
||||
if (sim_parse_args (sd, argv) != SIM_RC_OK)
|
||||
{
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* If we have a binary program, endianness-setting would not be taken
|
||||
from elsewhere unfortunately, so set it here. At the time of this
|
||||
writing, it isn't used until sim_config, but that might change so
|
||||
set it here before memory is defined or touched. */
|
||||
current_target_byte_order = LITTLE_ENDIAN;
|
||||
|
||||
/* check for/establish the reference program image */
|
||||
if (sim_analyze_program (sd,
|
||||
(STATE_PROG_ARGV (sd) != NULL
|
||||
? *STATE_PROG_ARGV (sd)
|
||||
: NULL),
|
||||
abfd) != SIM_RC_OK)
|
||||
{
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* For CRIS simulator-specific use, we need to find out the bounds of
|
||||
the program as well, which is not done by sim_analyze_program
|
||||
above. */
|
||||
if (STATE_PROG_BFD (sd))
|
||||
{
|
||||
struct progbounds pb;
|
||||
|
||||
/* The sections should now be accessible using bfd functions. */
|
||||
pb.startmem = 0x7fffffff;
|
||||
pb.endmem = 0;
|
||||
bfd_map_over_sections (STATE_PROG_BFD (sd), get_progbounds, &pb);
|
||||
|
||||
/* We align the area that the program uses to page boundaries. */
|
||||
startmem = pb.startmem & ~8191;
|
||||
endbrk = pb.endmem;
|
||||
endmem = (endbrk + 8191) & ~8191;
|
||||
}
|
||||
|
||||
/* Find out how much room is needed for the environment and argv, create
|
||||
that memory and fill it. Only do this when there's a program
|
||||
specified. */
|
||||
if (STATE_PROG_BFD (sd) && !cris_bare_iron)
|
||||
{
|
||||
char *name = bfd_get_filename (STATE_PROG_BFD (sd));
|
||||
char **my_environ = GET_ENVIRON ();
|
||||
/* We use these maps to give the same behavior as the old xsim
|
||||
simulator. */
|
||||
USI envtop = 0x40000000;
|
||||
USI stacktop = 0x3e000000;
|
||||
USI envstart;
|
||||
int envc;
|
||||
int len = strlen (name) + 1;
|
||||
USI epp, epp0;
|
||||
USI stacklen;
|
||||
int i;
|
||||
char **prog_argv = STATE_PROG_ARGV (sd);
|
||||
int my_argc = 0;
|
||||
/* All CPU:s have the same memory map, apparently. */
|
||||
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
||||
USI csp;
|
||||
bfd_byte buf[4];
|
||||
|
||||
/* Count in the environment as well. */
|
||||
for (envc = 0; my_environ[envc] != NULL; envc++)
|
||||
len += strlen (my_environ[envc]) + 1;
|
||||
|
||||
for (i = 0; prog_argv[i] != NULL; my_argc++, i++)
|
||||
len += strlen (prog_argv[i]) + 1;
|
||||
|
||||
envstart = (envtop - len) & ~8191;
|
||||
|
||||
/* Create read-only block for the environment strings. */
|
||||
sim_core_attach (sd, NULL, 0, access_read, 0,
|
||||
envstart, (len + 8191) & ~8191,
|
||||
0, NULL, NULL);
|
||||
|
||||
/* This shouldn't happen. */
|
||||
if (envstart < stacktop)
|
||||
stacktop = envstart - 64 * 8192;
|
||||
|
||||
csp = stacktop;
|
||||
|
||||
/* Note that the linux kernel does not correctly compute the storage
|
||||
needs for the static-exe AUX vector. */
|
||||
csp -= 4 * 4 * 2;
|
||||
|
||||
csp -= (envc + 1) * 4;
|
||||
csp -= (my_argc + 1) * 4;
|
||||
csp -= 4;
|
||||
|
||||
/* Write the target representation of the start-up-value for the
|
||||
stack-pointer suitable for register initialization below. */
|
||||
bfd_putl32 (csp, sp_init);
|
||||
|
||||
/* If we make this 1M higher; say 8192*1024, we have to take
|
||||
special precautions for pthreads, because pthreads assumes that
|
||||
the memory that low isn't mmapped, and that it can mmap it
|
||||
without fallback in case of failure (and we fail ungracefully
|
||||
long before *that*: the memory isn't accounted for in our mmap
|
||||
list). */
|
||||
stack_low = (csp - (7168*1024)) & ~8191;
|
||||
|
||||
stacklen = stacktop - stack_low;
|
||||
|
||||
/* Tee hee, we have an executable stack. Well, it's necessary to
|
||||
test GCC trampolines... */
|
||||
sim_core_attach (sd, NULL, 0, access_read_write_exec, 0,
|
||||
stack_low, stacklen,
|
||||
0, NULL, NULL);
|
||||
|
||||
epp = epp0 = envstart;
|
||||
|
||||
/* Can't use sim_core_write_unaligned_4 without everything
|
||||
initialized when tracing, and then these writes would get into
|
||||
the trace. */
|
||||
#define write_dword(addr, data) \
|
||||
do \
|
||||
{ \
|
||||
USI data_ = data; \
|
||||
USI addr_ = addr; \
|
||||
bfd_putl32 (data_, buf); \
|
||||
if (sim_core_write_buffer (sd, cpu, 0, buf, addr_, 4) != 4) \
|
||||
goto abandon_chip; \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
write_dword (csp, my_argc);
|
||||
csp += 4;
|
||||
|
||||
for (i = 0; i < my_argc; i++, csp += 4)
|
||||
{
|
||||
size_t strln = strlen (prog_argv[i]) + 1;
|
||||
|
||||
if (sim_core_write_buffer (sd, cpu, 0, prog_argv[i], epp, strln)
|
||||
!= strln)
|
||||
goto abandon_chip;
|
||||
|
||||
write_dword (csp, envstart + epp - epp0);
|
||||
epp += strln;
|
||||
}
|
||||
|
||||
write_dword (csp, 0);
|
||||
csp += 4;
|
||||
|
||||
for (i = 0; i < envc; i++, csp += 4)
|
||||
{
|
||||
unsigned int strln = strlen (my_environ[i]) + 1;
|
||||
|
||||
if (sim_core_write_buffer (sd, cpu, 0, my_environ[i], epp, strln)
|
||||
!= strln)
|
||||
goto abandon_chip;
|
||||
|
||||
write_dword (csp, envstart + epp - epp0);
|
||||
epp += strln;
|
||||
}
|
||||
|
||||
write_dword (csp, 0);
|
||||
csp += 4;
|
||||
|
||||
#define NEW_AUX_ENT(nr, id, val) \
|
||||
do \
|
||||
{ \
|
||||
write_dword (csp + (nr) * 4 * 2, (id)); \
|
||||
write_dword (csp + (nr) * 4 * 2 + 4, (val)); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* Note that there are some extra AUX entries for a dynlinked
|
||||
program loaded image. */
|
||||
|
||||
/* AUX entries always present. */
|
||||
NEW_AUX_ENT (0, TARGET_AT_HWCAP, 0);
|
||||
NEW_AUX_ENT (1, TARGET_AT_PAGESZ, 8192);
|
||||
NEW_AUX_ENT (2, TARGET_AT_CLKTCK, 100);
|
||||
|
||||
csp += 4 * 2 * 3;
|
||||
NEW_AUX_ENT (0, TARGET_AT_NULL, 0);
|
||||
#undef NEW_AUX_ENT
|
||||
|
||||
/* Register R10 should hold 0 at static start (no initfunc), but
|
||||
that's the default, so don't bother. */
|
||||
}
|
||||
|
||||
/* Allocate core managed memory if none specified by user. */
|
||||
if (sim_core_read_buffer (sd, NULL, read_map, &c, startmem, 1) == 0)
|
||||
sim_do_commandf (sd, "memory region 0x%lx,0x%lx", startmem,
|
||||
endmem - startmem);
|
||||
|
||||
/* Allocate simulator I/O managed memory if none specified by user. */
|
||||
if (cris_have_900000xxif)
|
||||
{
|
||||
if (sim_core_read_buffer (sd, NULL, read_map, &c, 0x90000000, 1) == 0)
|
||||
sim_core_attach (sd, NULL, 0, access_write, 0, 0x90000000, 0x100,
|
||||
0, &cris_devices, NULL);
|
||||
else
|
||||
{
|
||||
(*callback->
|
||||
printf_filtered) (callback,
|
||||
"Seeing --cris-900000xx with memory defined there\n");
|
||||
goto abandon_chip;
|
||||
}
|
||||
}
|
||||
|
||||
/* Establish any remaining configuration options. */
|
||||
if (sim_config (sd) != SIM_RC_OK)
|
||||
{
|
||||
abandon_chip:
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (sim_post_argv_init (sd) != SIM_RC_OK)
|
||||
{
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Open a copy of the cpu descriptor table. */
|
||||
{
|
||||
CGEN_CPU_DESC cd = cris_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
|
||||
CGEN_ENDIAN_LITTLE);
|
||||
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
|
||||
{
|
||||
SIM_CPU *cpu = STATE_CPU (sd, i);
|
||||
CPU_CPU_DESC (cpu) = cd;
|
||||
CPU_DISASSEMBLER (cpu) = cris_disassemble_insn;
|
||||
|
||||
/* See cris_option_handler for the reason why this is needed. */
|
||||
CPU_CRIS_MISC_PROFILE (cpu)->flags = STATE_TRACE_FLAGS (sd)[0];
|
||||
|
||||
/* Set SP to the stack we allocated above. */
|
||||
(* CPU_REG_STORE (cpu)) (cpu, H_GR_SP, (char *) sp_init, 4);
|
||||
|
||||
/* Set the simulator environment data. */
|
||||
cpu->highest_mmapped_page = NULL;
|
||||
cpu->endmem = endmem;
|
||||
cpu->endbrk = endbrk;
|
||||
cpu->stack_low = stack_low;
|
||||
cpu->syscalls = 0;
|
||||
cpu->m1threads = 0;
|
||||
cpu->threadno = 0;
|
||||
cpu->max_threadid = 0;
|
||||
cpu->thread_data = NULL;
|
||||
memset (cpu->sighandler, 0, sizeof (cpu->sighandler));
|
||||
cpu->make_thread_cpu_data = NULL;
|
||||
cpu->thread_cpu_data_size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize various cgen things not done by common framework.
|
||||
Must be done after cris_cgen_cpu_open. */
|
||||
cgen_init (sd);
|
||||
|
||||
/* Store in a global so things like cris_dump_regs can be invoked
|
||||
from the gdb command line. */
|
||||
current_state = sd;
|
||||
|
||||
cris_set_callbacks (callback);
|
||||
|
||||
return sd;
|
||||
}
|
||||
|
||||
void
|
||||
sim_close (SIM_DESC sd, int quitting ATTRIBUTE_UNUSED)
|
||||
{
|
||||
cris_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
|
||||
sim_module_uninstall (sd);
|
||||
}
|
||||
|
||||
SIM_RC
|
||||
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
|
||||
char **argv ATTRIBUTE_UNUSED,
|
||||
char **envp ATTRIBUTE_UNUSED)
|
||||
{
|
||||
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
|
||||
SIM_ADDR addr;
|
||||
|
||||
if (abfd != NULL)
|
||||
addr = bfd_get_start_address (abfd);
|
||||
else
|
||||
addr = 0;
|
||||
sim_pc_set (current_cpu, addr);
|
||||
|
||||
/* Other simulators have #if 0:d code that says
|
||||
STATE_ARGV (sd) = sim_copy_argv (argv);
|
||||
STATE_ENVP (sd) = sim_copy_argv (envp);
|
||||
Enabling that gives you not-found link-errors for sim_copy_argv.
|
||||
FIXME: Do archaeology to find out more. */
|
||||
|
||||
return SIM_RC_OK;
|
||||
}
|
||||
|
||||
void
|
||||
sim_do_command (SIM_DESC sd, char *cmd)
|
||||
{
|
||||
if (sim_args_command (sd, cmd) != SIM_RC_OK)
|
||||
sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
|
||||
}
|
||||
|
||||
/* Disassemble an instruction. */
|
||||
|
||||
static void
|
||||
cris_disassemble_insn (SIM_CPU *cpu,
|
||||
const CGEN_INSN *insn ATTRIBUTE_UNUSED,
|
||||
const ARGBUF *abuf ATTRIBUTE_UNUSED,
|
||||
IADDR pc, char *buf)
|
||||
{
|
||||
disassembler_ftype pinsn;
|
||||
struct disassemble_info disasm_info;
|
||||
SFILE sfile;
|
||||
SIM_DESC sd = CPU_STATE (cpu);
|
||||
|
||||
sfile.buffer = sfile.current = buf;
|
||||
INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
|
||||
(fprintf_ftype) sim_disasm_sprintf);
|
||||
disasm_info.endian =
|
||||
(bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
|
||||
: bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
|
||||
: BFD_ENDIAN_UNKNOWN);
|
||||
/* We live with the cast until the prototype is fixed, or else we get a
|
||||
warning because the functions differ in the signedness of one parameter. */
|
||||
disasm_info.read_memory_func =
|
||||
sim_disasm_read_memory;
|
||||
disasm_info.memory_error_func = sim_disasm_perror_memory;
|
||||
disasm_info.application_data = (PTR) cpu;
|
||||
pinsn = cris_get_disassembler (STATE_PROG_BFD (sd));
|
||||
(*pinsn) (pc, &disasm_info);
|
||||
}
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
/* Main header for the CRIS simulator, based on the m32r header.
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* All FIXME:s present in m32r apply here too; I just refuse to blindly
|
||||
carry them over, as I don't know if they're really things that need
|
||||
fixing. */
|
||||
|
||||
#ifndef SIM_MAIN_H
|
||||
#define SIM_MAIN_H
|
||||
|
||||
#define USING_SIM_BASE_H
|
||||
|
||||
struct _sim_cpu;
|
||||
typedef struct _sim_cpu SIM_CPU;
|
||||
|
||||
#include "symcat.h"
|
||||
#include "sim-basics.h"
|
||||
#include "cgen-types.h"
|
||||
#include "cris-desc.h"
|
||||
#include "cris-opc.h"
|
||||
#include "arch.h"
|
||||
|
||||
/* These must be defined before sim-base.h. */
|
||||
typedef USI sim_cia;
|
||||
|
||||
#define CIA_GET(cpu) CPU_PC_GET (cpu)
|
||||
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
|
||||
|
||||
#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
|
||||
do { \
|
||||
if (cpu) /* Null if ctrl-c. */ \
|
||||
sim_pc_set ((cpu), (cia)); \
|
||||
} while (0)
|
||||
#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
|
||||
do { \
|
||||
sim_pc_set ((cpu), (cia)); \
|
||||
} while (0)
|
||||
|
||||
#include "sim-base.h"
|
||||
#include "cgen-sim.h"
|
||||
#include "cris-sim.h"
|
||||
|
||||
/* For occurrences of ANDIF in decodev32.c. */
|
||||
#include "cgen-ops.h"
|
||||
|
||||
struct cris_sim_mmapped_page {
|
||||
USI addr;
|
||||
struct cris_sim_mmapped_page *prev;
|
||||
};
|
||||
|
||||
struct cris_thread_info {
|
||||
/* Identifier for this thread. */
|
||||
unsigned int threadid;
|
||||
|
||||
/* Identifier for parent thread. */
|
||||
unsigned int parent_threadid;
|
||||
|
||||
/* Signal to send to parent at exit. */
|
||||
int exitsig;
|
||||
|
||||
/* Exit status. */
|
||||
int exitval;
|
||||
|
||||
/* Only as storage to return the "set" value to the "get" method.
|
||||
I'm not sure whether this is useful per-thread. */
|
||||
USI priority;
|
||||
|
||||
struct
|
||||
{
|
||||
USI altstack;
|
||||
USI options;
|
||||
|
||||
char action;
|
||||
char pending;
|
||||
char blocked;
|
||||
char blocked_suspendsave;
|
||||
/* The handler stub unblocks the signal, so we don't need a separate
|
||||
"temporary save" for that. */
|
||||
} sigdata[64];
|
||||
|
||||
/* Register context, swapped with _sim_cpu.cpu_data. */
|
||||
void *cpu_context;
|
||||
|
||||
/* Similar, temporary copy for the state at a signal call. */
|
||||
void *cpu_context_atsignal;
|
||||
|
||||
/* The number of the reading and writing ends of a pipe if waiting for
|
||||
the reader, else 0. */
|
||||
int pipe_read_fd;
|
||||
int pipe_write_fd;
|
||||
|
||||
/* System time at last context switch when this thread ran. */
|
||||
USI last_execution;
|
||||
|
||||
/* Nonzero if we just executed a syscall. */
|
||||
char at_syscall;
|
||||
|
||||
/* Nonzero if any of sigaction[0..64].pending is true. */
|
||||
char sigpending;
|
||||
|
||||
/* Nonzero if in (rt_)sigsuspend call. Cleared at every sighandler
|
||||
call. */
|
||||
char sigsuspended;
|
||||
};
|
||||
|
||||
struct _sim_cpu {
|
||||
/* sim/common cpu base. */
|
||||
sim_cpu_base base;
|
||||
|
||||
/* Static parts of cgen. */
|
||||
CGEN_CPU cgen_cpu;
|
||||
|
||||
CRIS_MISC_PROFILE cris_misc_profile;
|
||||
#define CPU_CRIS_MISC_PROFILE(cpu) (& (cpu)->cris_misc_profile)
|
||||
|
||||
/* Copy of previous data; only valid when emitting trace-data after
|
||||
each insn. */
|
||||
CRIS_MISC_PROFILE cris_prev_misc_profile;
|
||||
#define CPU_CRIS_PREV_MISC_PROFILE(cpu) (& (cpu)->cris_prev_misc_profile)
|
||||
|
||||
/* Simulator environment data. */
|
||||
USI endmem;
|
||||
USI endbrk;
|
||||
USI stack_low;
|
||||
struct cris_sim_mmapped_page *highest_mmapped_page;
|
||||
|
||||
/* Number of syscalls performed or in progress, counting once extra
|
||||
for every time a blocked thread (internally, when threading) polls
|
||||
the (pipe) blockage. By default, this is also a time counter: to
|
||||
minimize performance noise from minor compiler changes,
|
||||
instructions take no time and syscalls always take 1ms. */
|
||||
USI syscalls;
|
||||
|
||||
/* Number of execution contexts minus one. */
|
||||
int m1threads;
|
||||
|
||||
/* Current thread number; index into thread_data when m1threads != 0. */
|
||||
int threadno;
|
||||
|
||||
/* When a new thread is created, it gets a unique number, which we
|
||||
count here. */
|
||||
int max_threadid;
|
||||
|
||||
/* Thread-specific info, for simulator thread support, created at
|
||||
"clone" call. Vector of [threads+1] when m1threads > 0. */
|
||||
struct cris_thread_info *thread_data;
|
||||
|
||||
/* "If CLONE_SIGHAND is set, the calling process and the child pro-
|
||||
cesses share the same table of signal handlers." ... "However, the
|
||||
calling process and child processes still have distinct signal
|
||||
masks and sets of pending signals." See struct cris_thread_info
|
||||
for sigmasks and sigpendings. */
|
||||
USI sighandler[64];
|
||||
|
||||
/* Function for initializing CPU thread context, which varies in size
|
||||
with each CPU model. They should be in some constant parts or
|
||||
initialized in *_init_cpu, but we can't modify that for now. */
|
||||
void* (*make_thread_cpu_data) (SIM_CPU *, void *);
|
||||
size_t thread_cpu_data_size;
|
||||
|
||||
/* CPU-model specific parts go here.
|
||||
Note that in files that don't need to access these pieces WANT_CPU_FOO
|
||||
won't be defined and thus these parts won't appear. This is ok in the
|
||||
sense that things work. It is a source of bugs though.
|
||||
One has to of course be careful to not take the size of this
|
||||
struct and no structure members accessed in non-cpu specific files can
|
||||
go after here. */
|
||||
#if defined (WANT_CPU_CRISV0F)
|
||||
CRISV0F_CPU_DATA cpu_data;
|
||||
#elif defined (WANT_CPU_CRISV3F)
|
||||
CRISV3F_CPU_DATA cpu_data;
|
||||
#elif defined (WANT_CPU_CRISV8F)
|
||||
CRISV8F_CPU_DATA cpu_data;
|
||||
#elif defined (WANT_CPU_CRISV10F)
|
||||
CRISV10F_CPU_DATA cpu_data;
|
||||
#elif defined (WANT_CPU_CRISV32F)
|
||||
CRISV32F_CPU_DATA cpu_data;
|
||||
#else
|
||||
/* Let's assume all cpu_data have the same alignment requirements, so
|
||||
they all are laid out at the same address. Since we can't get the
|
||||
exact definition, we also assume that it has no higher alignment
|
||||
requirements than a vector of, say, 16 pointers. (A single member
|
||||
is often special-cased, and possibly two as well so we don't want
|
||||
that). */
|
||||
union { void *dummy[16]; } cpu_data_placeholder;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The sim_state struct. */
|
||||
|
||||
struct sim_state {
|
||||
sim_cpu *cpu;
|
||||
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
|
||||
|
||||
CGEN_STATE cgen_state;
|
||||
|
||||
sim_state_base base;
|
||||
};
|
||||
|
||||
/* Misc. */
|
||||
|
||||
/* Catch address exceptions. */
|
||||
extern SIM_CORE_SIGNAL_FN cris_core_signal;
|
||||
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
|
||||
cris_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
|
||||
(TRANSFER), (ERROR))
|
||||
|
||||
/* Default memory size. */
|
||||
#define CRIS_DEFAULT_MEM_SIZE 0x800000 /* 8M */
|
||||
|
||||
extern device cris_devices;
|
||||
|
||||
#endif /* SIM_MAIN_H */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/* CRIS target configuration file. -*- C -*-
|
||||
Copyright (C) 2004, 2005 Free Software Foundation, Inc.
|
||||
Contributed by Axis Communications.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#ifndef CRIS_TCONFIG_H
|
||||
#define CRIS_TCONFIG_H
|
||||
|
||||
#include "ansidecl.h"
|
||||
#include "gdb/callback.h"
|
||||
#include "gdb/remote-sim.h"
|
||||
#include "sim-module.h"
|
||||
|
||||
/* There's basically a a big ??? FIXME: CHECK THIS on everything in this
|
||||
file. I just copied it from m32r, pruned some stuff and added
|
||||
HAVE_MODEL because it seemed useful. */
|
||||
|
||||
/* See sim-hload.c. We properly handle LMA. */
|
||||
#define SIM_HANDLES_LMA 1
|
||||
|
||||
/* For MSPR support. FIXME: revisit. */
|
||||
#define WITH_DEVICES 1
|
||||
|
||||
extern MODULE_INSTALL_FN cris_option_install;
|
||||
|
||||
/* FIXME: Revisit. */
|
||||
#ifdef HAVE_DV_SOCKSER
|
||||
extern MODULE_INSTALL_FN dv_sockser_install;
|
||||
#define MODULE_LIST dv_sockser_install, cris_option_install,
|
||||
#else
|
||||
#define MODULE_LIST cris_option_install,
|
||||
#endif
|
||||
|
||||
#define SIM_HAVE_MODEL
|
||||
|
||||
/* This is a global setting. Different cpu families can't mix-n-match -scache
|
||||
and -pbb. However some cpu families may use -simple while others use
|
||||
one of -scache/-pbb. */
|
||||
#define WITH_SCACHE_PBB 1
|
||||
|
||||
#endif /* CRIS_TCONFIG_H */
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue