Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
* interp.c (xfer_direct_word, xfer_direct_long, swap_direct_word, swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, xfer_little_long, swap_word,swap_long): Added. * interp.c (ColdReset): Provide function indirection to host<->simulated_target transfer routines. * interp.c (sim_store_register, sim_fetch_register): Updated to make use of indirected transfer routines.
This commit is contained in:
Jackie Smith Cashion
parent
aefee5c89f
commit
f7481d45a5
@ -1,3 +1,21 @@
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Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
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* interp.c (xfer_direct_word, xfer_direct_long,
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swap_direct_word, swap_direct_long, xfer_big_word,
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xfer_big_long, xfer_little_word, xfer_little_long,
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swap_word,swap_long): Added.
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* interp.c (ColdReset): Provide function indirection to
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host<->simulated_target transfer routines.
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* interp.c (sim_store_register, sim_fetch_register): Updated to
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make use of indirected transfer routines.
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Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
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* gencode.c (process_instructions): Ensure FP ABS instruction
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recognised.
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* interp.c (AbsoluteValue): Add routine. Also provide simple PMON
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system call support.
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Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
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* interp.c (sim_do_command): Complain if callback structure not
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@ -61,6 +61,9 @@ code on the hardware.
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#include "engine.c"
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#undef SIM_MANIFESTS
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/* This variable holds the GDB view of the target endianness: */
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extern int target_byte_order;
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/* The following reserved instruction value is used when a simulator
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trap is required. NOTE: Care must be taken, since this value may be
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used in later revisions of the MIPS ISA. */
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@ -405,7 +408,7 @@ unsigned int pipeline_ticks = 0;
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#define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
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#define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
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unsigned int state = (0 | simBE); /* big-endian simulator by default */
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unsigned int state = 0;
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unsigned int rcexit = 0; /* _exit() reason code holder */
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#define DELAYSLOT() {\
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@ -447,6 +450,19 @@ ut_reg profile_maxpc;
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int profile_shift = 0; /* address shift amount */
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#endif /* PROFILE */
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/* The following are used to provide shortcuts to the required version
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of host<->target copying. This avoids run-time conditionals, which
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would slow the simulator throughput. */
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typedef unsigned int (*fnptr_read_word) PARAMS((unsigned char *memory));
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typedef unsigned int (*fnptr_swap_word) PARAMS((unsigned int data));
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typedef uword64 (*fnptr_read_long) PARAMS((unsigned char *memory));
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typedef uword64 (*fnptr_swap_long) PARAMS((uword64 data));
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fnptr_read_word host_read_word;
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fnptr_read_long host_read_long;
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fnptr_swap_word host_swap_word;
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fnptr_swap_long host_swap_long;
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/*---------------------------------------------------------------------------*/
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/*-- GDB simulator interface ------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -459,10 +475,12 @@ static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64
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static uword64 LoadMemory PARAMS((int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw));
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static void SignalException PARAMS((int exception,...));
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static void simulate PARAMS((void));
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static long getnum(char *value);
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extern void sim_size(unsigned int newsize);
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extern void sim_set_profile(int frequency);
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static unsigned int power2(unsigned int value);
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static long getnum PARAMS((char *value));
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extern void sim_size PARAMS((unsigned int newsize));
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extern void sim_set_profile PARAMS((int frequency));
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static unsigned int power2 PARAMS((unsigned int value));
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/*---------------------------------------------------------------------------*/
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void
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sim_open (args)
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@ -1056,9 +1074,9 @@ sim_store_register (rn,memory)
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callback->printf_filtered(callback,"Warning: Invalid register width for %d (register store ignored)\n",rn);
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else {
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if (register_widths[rn] == 32)
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registers[rn] = *((unsigned int *)memory);
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registers[rn] = host_read_word(memory);
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else
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registers[rn] = *((uword64 *)memory);
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registers[rn] = host_read_long(memory);
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}
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return;
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@ -1077,9 +1095,9 @@ sim_fetch_register (rn,memory)
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callback->printf_filtered(callback,"Warning: Invalid register width for %d (register fetch ignored)\n",rn);
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else {
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if (register_widths[rn] == 32)
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*((unsigned int *)memory) = (registers[rn] & 0xFFFFFFFF);
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*((unsigned int *)memory) = host_swap_word(registers[rn] & 0xFFFFFFFF);
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else /* 64bit register */
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*((uword64 *)memory) = registers[rn];
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*((uword64 *)memory) = host_swap_long(registers[rn]);
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}
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return;
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}
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@ -1721,6 +1739,95 @@ void dotrace(tracefh,type,address,width,comment)
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}
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#endif /* TRACE */
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/*---------------------------------------------------------------------------*/
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/*-- host<->target transfers ------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* The following routines allow conditionals to be avoided during the
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simulation, at the cost of increasing the image and source size. */
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static unsigned int
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xfer_direct_word(memory)
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unsigned char *memory;
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{
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return *((unsigned int *)memory);
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}
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static uword64
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xfer_direct_long(memory)
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unsigned char *memory;
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{
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return *((uword64 *)memory);
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}
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static unsigned int
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swap_direct_word(data)
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unsigned int data;
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{
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return data;
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}
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static uword64
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swap_direct_long(data)
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uword64 data;
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{
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return data;
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}
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static unsigned int
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xfer_big_word(memory)
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unsigned char *memory;
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{
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return ((memory[0] << 24) | (memory[1] << 16) | (memory[2] << 8) | memory[3]);
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}
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static uword64
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xfer_big_long(memory)
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unsigned char *memory;
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{
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return (((uword64)memory[0] << 56) | ((uword64)memory[1] << 48)
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| ((uword64)memory[2] << 40) | ((uword64)memory[3] << 32)
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| (memory[4] << 24) | (memory[5] << 16) | (memory[6] << 8) | memory[7]);
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}
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static unsigned int
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xfer_little_word(memory)
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unsigned char *memory;
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{
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return ((memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | memory[0]);
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}
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static uword64
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xfer_little_long(memory)
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unsigned char *memory;
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{
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return (((uword64)memory[7] << 56) | ((uword64)memory[6] << 48)
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| ((uword64)memory[5] << 40) | ((uword64)memory[4] << 32)
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| (memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | memory[0]);
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}
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static unsigned int
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swap_word(data)
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unsigned int data;
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{
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unsigned int result;
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result = data ^ ((data << 16) | (data >> 16));
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result &= ~0x00FF0000;
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data = (data << 24) | (data >> 8);
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return data ^ (result >> 8);
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}
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static uword64
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swap_long(data)
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uword64 data;
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{
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unsigned int tmphi = WORD64HI(data);
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unsigned int tmplo = WORD64LO(data);
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tmphi = swap_word(tmphi);
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tmplo = swap_word(tmplo);
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/* Now swap the HI and LO parts */
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return SET64LO(tmphi) | SET64HI(tmplo);
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}
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/*---------------------------------------------------------------------------*/
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/*-- simulator engine -------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -1762,6 +1869,35 @@ ColdReset()
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}
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#endif /* HASFPU */
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/* In reality this check should be performed at various points
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within the simulation, since it is possible to change the
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endianness of user programs. However, we perform the check here
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to ensure that the start-of-day values agree: */
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state |= (BigEndianCPU ? simBE : 0);
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if ((target_byte_order == 1234) != !(state & simBE)) {
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fprintf(stderr,"ColdReset: GDB (%s) and simulator (%s) do not agree on target endianness\n",
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target_byte_order == 1234 ? "little" : "big",
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state & simBE ? "big" : "little");
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exit(1);
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}
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if ((state & simHOSTBE) == (state & simBE)) {
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host_read_word = xfer_direct_word;
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host_read_long = xfer_direct_long;
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host_swap_word = swap_direct_word;
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host_swap_long = swap_direct_long;
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} else if (state & simHOSTBE) {
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host_read_word = xfer_little_word;
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host_read_long = xfer_little_long;
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host_swap_word = swap_word;
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host_swap_long = swap_long;
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} else { /* HOST little-endian */
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host_read_word = xfer_big_word;
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host_read_long = xfer_big_long;
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host_swap_word = swap_word;
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host_swap_long = swap_long;
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}
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return;
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}
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@ -3441,9 +3577,6 @@ simulate ()
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callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction,WORD64HI(PC),WORD64LO(PC));
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#endif /* DEBUG */
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/*DBG*/ if (instruction == 0x46200005) /* ABS.D */
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/*DBG*/ callback->printf_filtered(callback,"DBG: ABS.D (0x%08X) instruction\n",instruction);
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#if !defined(FASTSIM) || defined(PROFILE)
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instruction_fetches++;
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/* Since we increment above, the value should only ever be zero if
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