Minor comment fixes in sim/common/sim-fpu.c.
This patch makes a fair number of fixes in the various comments of
sim-fpu.c, mostly to either better conform to the GNU Coding Standards
(sentences start with a capital letter, end with a period), or to
fix spelling mistakes.
sim/common/ChangeLog:
* sim-fpu.c: Minor comment fixes throughout.
This commit is contained in:
Joel Brobecker
parent
3c8e93b7fa
commit
f749ed6079
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@ -1,3 +1,7 @@
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2016-01-17 Joel Brobecker <brobecker@adacore.com>
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* sim-fpu.c: Minor comment fixes throughout.
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2016-01-17 Joel Brobecker <brobecker@adacore.com>
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* sim-fpu.c (print_bits): Minor reformatting (no code change).
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@ -73,7 +73,7 @@ print_bits (unsigned64 x,
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/* Quick and dirty conversion between a host double and host 64bit int */
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/* Quick and dirty conversion between a host double and host 64bit int. */
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typedef union
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{
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@ -175,7 +175,7 @@ typedef union
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#define MAX_UINT (is_64bit ? MAX_UINT64 : MAX_UINT32)
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#define NR_INTBITS (is_64bit ? 64 : 32)
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/* Squeese an unpacked sim_fpu struct into a 32/64 bit integer */
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/* Squeeze an unpacked sim_fpu struct into a 32/64 bit integer. */
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STATIC_INLINE_SIM_FPU (unsigned64)
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pack_fpu (const sim_fpu *src,
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int is_double)
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@ -187,11 +187,11 @@ pack_fpu (const sim_fpu *src,
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switch (src->class)
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{
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/* create a NaN */
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/* Create a NaN. */
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case sim_fpu_class_qnan:
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sign = src->sign;
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exp = EXPMAX;
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/* force fraction to correct class */
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/* Force fraction to correct class. */
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fraction = src->fraction;
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fraction >>= NR_GUARDS;
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#ifdef SIM_QUIET_NAN_NEGATED
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@ -203,7 +203,7 @@ pack_fpu (const sim_fpu *src,
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case sim_fpu_class_snan:
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sign = src->sign;
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exp = EXPMAX;
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/* force fraction to correct class */
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/* Force fraction to correct class. */
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fraction = src->fraction;
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fraction >>= NR_GUARDS;
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#ifdef SIM_QUIET_NAN_NEGATED
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@ -235,7 +235,7 @@ pack_fpu (const sim_fpu *src,
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int nr_shift = NORMAL_EXPMIN - src->normal_exp;
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if (nr_shift > NR_FRACBITS)
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{
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/* underflow, just make the number zero */
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/* Underflow, just make the number zero. */
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sign = src->sign;
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exp = 0;
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fraction = 0;
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@ -244,7 +244,7 @@ pack_fpu (const sim_fpu *src,
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{
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sign = src->sign;
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exp = 0;
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/* Shift by the value */
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/* Shift by the value. */
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fraction = src->fraction;
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fraction >>= NR_GUARDS;
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fraction >>= nr_shift;
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@ -263,7 +263,7 @@ pack_fpu (const sim_fpu *src,
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sign = src->sign;
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fraction = src->fraction;
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/* FIXME: Need to round according to WITH_SIM_FPU_ROUNDING
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or some such */
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or some such. */
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/* Round to nearest: If the guard bits are the all zero, but
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the first, then we're half way between two numbers,
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choose the one which makes the lsb of the answer 0. */
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@ -274,17 +274,17 @@ pack_fpu (const sim_fpu *src,
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}
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else
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{
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/* Add a one to the guards to force round to nearest */
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/* Add a one to the guards to force round to nearest. */
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fraction += GUARDROUND;
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}
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if ((fraction & IMPLICIT_2)) /* rounding resulted in carry */
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if ((fraction & IMPLICIT_2)) /* Rounding resulted in carry. */
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{
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exp += 1;
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fraction >>= 1;
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}
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fraction >>= NR_GUARDS;
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/* When exp == EXPMAX (overflow from carry) fraction must
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have been made zero */
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have been made zero. */
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ASSERT ((exp == EXPMAX) <= ((fraction & ~IMPLICIT_1) == 0));
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}
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break;
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@ -296,7 +296,7 @@ pack_fpu (const sim_fpu *src,
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| (exp << NR_FRACBITS)
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| LSMASKED64 (fraction, NR_FRACBITS - 1, 0));
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/* trace operation */
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/* Trace operation. */
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#if 0
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if (is_double)
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{
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@ -315,7 +315,7 @@ pack_fpu (const sim_fpu *src,
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}
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/* Unpack a 32/64 bit integer into a sim_fpu structure */
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/* Unpack a 32/64 bit integer into a sim_fpu structure. */
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STATIC_INLINE_SIM_FPU (void)
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unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
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{
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@ -328,7 +328,7 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
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/* Hmm. Looks like 0 */
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if (fraction == 0)
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{
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/* tastes like zero */
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/* Tastes like zero. */
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dst->class = sim_fpu_class_zero;
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dst->sign = sign;
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dst->normal_exp = 0;
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@ -355,7 +355,7 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
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/* Huge exponent*/
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if (fraction == 0)
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{
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/* Attached to a zero fraction - means infinity */
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/* Attached to a zero fraction - means infinity. */
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dst->class = sim_fpu_class_infinity;
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dst->sign = sign;
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/* dst->normal_exp = EXPBIAS; */
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@ -365,7 +365,7 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
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{
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int qnan;
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/* Non zero fraction, means NaN */
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/* Non zero fraction, means NaN. */
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dst->sign = sign;
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dst->fraction = (fraction << NR_GUARDS);
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#ifdef SIM_QUIET_NAN_NEGATED
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@ -381,14 +381,14 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
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}
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else
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{
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/* Nothing strange about this number */
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/* Nothing strange about this number. */
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dst->class = sim_fpu_class_number;
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dst->sign = sign;
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dst->fraction = ((fraction << NR_GUARDS) | IMPLICIT_1);
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dst->normal_exp = exp - EXPBIAS;
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}
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/* trace operation */
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/* Trace operation. */
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#if 0
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if (is_double)
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{
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@ -420,7 +420,7 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
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}
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/* Convert a floating point into an integer */
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/* Convert a floating point into an integer. */
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STATIC_INLINE_SIM_FPU (int)
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fpu2i (signed64 *i,
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const sim_fpu *s,
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@ -445,13 +445,13 @@ fpu2i (signed64 *i,
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*i = MIN_INT; /* FIXME */
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return sim_fpu_status_invalid_cvi;
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}
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/* map infinity onto MAX_INT... */
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/* Map infinity onto MAX_INT... */
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if (sim_fpu_is_infinity (s))
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{
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*i = s->sign ? MIN_INT : MAX_INT;
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return sim_fpu_status_invalid_cvi;
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}
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/* it is a number, but a small one */
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/* It is a number, but a small one. */
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if (s->normal_exp < 0)
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{
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*i = 0;
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@ -466,7 +466,7 @@ fpu2i (signed64 *i,
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return 0; /* exact */
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if (is_64bit) /* can't round */
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return sim_fpu_status_invalid_cvi; /* must be overflow */
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/* For a 32bit with MAX_INT, rounding is possible */
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/* For a 32bit with MAX_INT, rounding is possible. */
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switch (round)
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{
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case sim_fpu_round_default:
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@ -502,7 +502,7 @@ fpu2i (signed64 *i,
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*i = s->sign ? MIN_INT : MAX_INT;
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return sim_fpu_status_invalid_cvi;
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}
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/* normal number shift it into place */
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/* Normal number, shift it into place. */
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tmp = s->fraction;
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shift = (s->normal_exp - (NR_FRAC_GUARD));
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if (shift > 0)
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@ -520,7 +520,7 @@ fpu2i (signed64 *i,
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return status;
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}
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/* convert an integer into a floating point */
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/* Convert an integer into a floating point. */
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STATIC_INLINE_SIM_FPU (int)
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i2fpu (sim_fpu *f, signed64 i, int is_64bit)
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{
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@ -540,7 +540,7 @@ i2fpu (sim_fpu *f, signed64 i, int is_64bit)
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if (f->sign)
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{
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/* Special case for minint, since there is no corresponding
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+ve integer representation for it */
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+ve integer representation for it. */
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if (i == MIN_INT)
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{
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f->fraction = IMPLICIT_1;
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@ -593,7 +593,7 @@ i2fpu (sim_fpu *f, signed64 i, int is_64bit)
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}
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/* Convert a floating point into an integer */
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/* Convert a floating point into an integer. */
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STATIC_INLINE_SIM_FPU (int)
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fpu2u (unsigned64 *u, const sim_fpu *s, int is_64bit)
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{
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@ -610,19 +610,19 @@ fpu2u (unsigned64 *u, const sim_fpu *s, int is_64bit)
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*u = 0;
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return 0;
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}
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/* it is a negative number */
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/* It is a negative number. */
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if (s->sign)
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{
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*u = 0;
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return 0;
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}
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/* get reasonable MAX_USI_INT... */
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/* Get reasonable MAX_USI_INT... */
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if (sim_fpu_is_infinity (s))
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{
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*u = MAX_UINT;
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return 0;
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}
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/* it is a number, but a small one */
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/* It is a number, but a small one. */
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if (s->normal_exp < 0)
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{
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*u = 0;
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@ -650,7 +650,7 @@ fpu2u (unsigned64 *u, const sim_fpu *s, int is_64bit)
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return 0;
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}
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/* Convert an unsigned integer into a floating point */
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/* Convert an unsigned integer into a floating point. */
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STATIC_INLINE_SIM_FPU (int)
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u2fpu (sim_fpu *f, unsigned64 u, int is_64bit)
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{
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@ -739,7 +739,7 @@ sim_fpu_fractionto (sim_fpu *f,
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f->class = sim_fpu_class_number;
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f->sign = sign;
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f->normal_exp = normal_exp;
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/* shift the fraction to where sim-fpu expects it */
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/* Shift the fraction to where sim-fpu expects it. */
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if (shift >= 0)
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f->fraction = (fraction << shift);
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else
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@ -752,7 +752,7 @@ INLINE_SIM_FPU (unsigned64)
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sim_fpu_tofraction (const sim_fpu *d,
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int precision)
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{
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/* we have NR_FRAC_GUARD bits, we want only PRECISION bits */
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/* We have NR_FRAC_GUARD bits, we want only PRECISION bits. */
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int shift = (NR_FRAC_GUARD - precision);
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unsigned64 fraction = (d->fraction & ~IMPLICIT_1);
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if (shift >= 0)
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@ -824,7 +824,7 @@ do_normal_underflow (sim_fpu *f,
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/* Round a number using NR_GUARDS.
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Will return the rounded number or F->FRACTION == 0 when underflow */
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Will return the rounded number or F->FRACTION == 0 when underflow. */
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STATIC_INLINE_SIM_FPU (int)
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do_normal_round (sim_fpu *f,
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@ -866,7 +866,7 @@ do_normal_round (sim_fpu *f,
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break;
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}
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f->fraction &= ~guardmask;
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/* round if needed, handle resulting overflow */
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/* Round if needed, handle resulting overflow. */
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if ((status & sim_fpu_status_rounded))
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{
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f->fraction += fraclsb;
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@ -897,7 +897,7 @@ do_round (sim_fpu *f,
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return 0;
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break;
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case sim_fpu_class_snan:
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/* Quieten a SignalingNaN */
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/* Quieten a SignalingNaN. */
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f->class = sim_fpu_class_qnan;
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return sim_fpu_status_invalid_snan;
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break;
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@ -919,7 +919,7 @@ do_round (sim_fpu *f,
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&& !(denorm & sim_fpu_denorm_zero))
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{
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status = do_normal_round (f, shift + NR_GUARDS, round);
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if (f->fraction == 0) /* rounding underflowed */
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if (f->fraction == 0) /* Rounding underflowed. */
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{
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status |= do_normal_underflow (f, is_double, round);
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}
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@ -931,7 +931,7 @@ do_round (sim_fpu *f,
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before rounding, some after! */
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if (status & sim_fpu_status_inexact)
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status |= sim_fpu_status_underflow;
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/* Flag that resultant value has been denormalized */
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/* Flag that resultant value has been denormalized. */
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f->class = sim_fpu_class_denorm;
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}
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else if ((denorm & sim_fpu_denorm_underflow_inexact))
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@ -957,7 +957,7 @@ do_round (sim_fpu *f,
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/* f->class = sim_fpu_class_zero; */
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status |= do_normal_underflow (f, is_double, round);
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else if (f->normal_exp > NORMAL_EXPMAX)
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/* oops! rounding caused overflow */
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/* Oops! rounding caused overflow. */
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status |= do_normal_overflow (f, is_double, round);
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}
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ASSERT ((f->class == sim_fpu_class_number
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@ -1056,13 +1056,13 @@ sim_fpu_add (sim_fpu *f,
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/* use exp of larger */
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if (shift >= NR_FRAC_GUARD)
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{
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/* left has much bigger magnitute */
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/* left has much bigger magnitude */
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*f = *l;
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return sim_fpu_status_inexact;
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}
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if (shift <= - NR_FRAC_GUARD)
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{
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/* right has much bigger magnitute */
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/* right has much bigger magnitude */
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*f = *r;
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return sim_fpu_status_inexact;
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}
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@ -1074,7 +1074,7 @@ sim_fpu_add (sim_fpu *f,
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if (rfraction & LSMASK64 (shift - 1, 0))
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{
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status |= sim_fpu_status_inexact;
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rfraction |= LSBIT64 (shift); /* stick LSBit */
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rfraction |= LSBIT64 (shift); /* Stick LSBit. */
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}
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rfraction >>= shift;
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}
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@ -1084,7 +1084,7 @@ sim_fpu_add (sim_fpu *f,
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if (lfraction & LSMASK64 (- shift - 1, 0))
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{
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status |= sim_fpu_status_inexact;
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lfraction |= LSBIT64 (- shift); /* stick LSBit */
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lfraction |= LSBIT64 (- shift); /* Stick LSBit. */
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}
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lfraction >>= -shift;
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}
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@ -1093,7 +1093,7 @@ sim_fpu_add (sim_fpu *f,
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f->normal_exp = r->normal_exp;
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}
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/* perform the addition */
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/* Perform the addition. */
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if (l->sign)
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lfraction = - lfraction;
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if (r->sign)
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@ -1117,7 +1117,7 @@ sim_fpu_add (sim_fpu *f,
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f->fraction = - f->fraction;
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}
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/* normalize it */
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/* Normalize it. */
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if ((f->fraction & IMPLICIT_2))
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{
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f->fraction = (f->fraction >> 1) | (f->fraction & 1);
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@ -1209,13 +1209,13 @@ sim_fpu_sub (sim_fpu *f,
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/* use exp of larger */
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if (shift >= NR_FRAC_GUARD)
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{
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/* left has much bigger magnitute */
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/* left has much bigger magnitude */
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*f = *l;
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return sim_fpu_status_inexact;
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}
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if (shift <= - NR_FRAC_GUARD)
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{
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/* right has much bigger magnitute */
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/* right has much bigger magnitude */
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*f = *r;
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f->sign = !r->sign;
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return sim_fpu_status_inexact;
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@ -1228,7 +1228,7 @@ sim_fpu_sub (sim_fpu *f,
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if (rfraction & LSMASK64 (shift - 1, 0))
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{
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status |= sim_fpu_status_inexact;
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rfraction |= LSBIT64 (shift); /* stick LSBit */
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rfraction |= LSBIT64 (shift); /* Stick LSBit. */
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}
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rfraction >>= shift;
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}
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@ -1238,7 +1238,7 @@ sim_fpu_sub (sim_fpu *f,
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if (lfraction & LSMASK64 (- shift - 1, 0))
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{
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status |= sim_fpu_status_inexact;
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lfraction |= LSBIT64 (- shift); /* stick LSBit */
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lfraction |= LSBIT64 (- shift); /* Stick LSBit. */
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}
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lfraction >>= -shift;
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}
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@ -1247,7 +1247,7 @@ sim_fpu_sub (sim_fpu *f,
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f->normal_exp = r->normal_exp;
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}
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/* perform the subtraction */
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/* Perform the subtraction. */
|
||||
if (l->sign)
|
||||
lfraction = - lfraction;
|
||||
if (!r->sign)
|
||||
|
|
@ -1271,7 +1271,7 @@ sim_fpu_sub (sim_fpu *f,
|
|||
f->fraction = - f->fraction;
|
||||
}
|
||||
|
||||
/* normalize it */
|
||||
/* Normalize it. */
|
||||
if ((f->fraction & IMPLICIT_2))
|
||||
{
|
||||
f->fraction = (f->fraction >> 1) | (f->fraction & 1);
|
||||
|
|
@ -1348,7 +1348,7 @@ sim_fpu_mul (sim_fpu *f,
|
|||
return 0;
|
||||
}
|
||||
/* Calculate the mantissa by multiplying both 64bit numbers to get a
|
||||
128 bit number */
|
||||
128 bit number. */
|
||||
{
|
||||
unsigned64 low;
|
||||
unsigned64 high;
|
||||
|
|
@ -1391,7 +1391,7 @@ sim_fpu_mul (sim_fpu *f,
|
|||
ASSERT (high >= LSBIT64 ((NR_FRAC_GUARD * 2) - 64));
|
||||
ASSERT (LSBIT64 (((NR_FRAC_GUARD + 1) * 2) - 64) < IMPLICIT_1);
|
||||
|
||||
/* normalize */
|
||||
/* Normalize. */
|
||||
do
|
||||
{
|
||||
f->normal_exp--;
|
||||
|
|
@ -1488,7 +1488,7 @@ sim_fpu_div (sim_fpu *f,
|
|||
}
|
||||
|
||||
/* Calculate the mantissa by multiplying both 64bit numbers to get a
|
||||
128 bit number */
|
||||
128 bit number. */
|
||||
{
|
||||
/* quotient = ( ( numerator / denominator)
|
||||
x 2^(numerator exponent - denominator exponent)
|
||||
|
|
@ -1513,7 +1513,7 @@ sim_fpu_div (sim_fpu *f,
|
|||
}
|
||||
ASSERT (numerator >= denominator);
|
||||
|
||||
/* Gain extra precision, already used one spare bit */
|
||||
/* Gain extra precision, already used one spare bit. */
|
||||
numerator <<= NR_SPARE;
|
||||
denominator <<= NR_SPARE;
|
||||
|
||||
|
|
@ -1531,7 +1531,7 @@ sim_fpu_div (sim_fpu *f,
|
|||
numerator <<= 1;
|
||||
}
|
||||
|
||||
/* discard (but save) the extra bits */
|
||||
/* Discard (but save) the extra bits. */
|
||||
if ((quotient & LSMASK64 (NR_SPARE -1, 0)))
|
||||
quotient = (quotient >> NR_SPARE) | 1;
|
||||
else
|
||||
|
|
@ -1541,7 +1541,7 @@ sim_fpu_div (sim_fpu *f,
|
|||
ASSERT (f->fraction >= IMPLICIT_1 && f->fraction < IMPLICIT_2);
|
||||
if (numerator != 0)
|
||||
{
|
||||
f->fraction |= 1; /* stick remaining bits */
|
||||
f->fraction |= 1; /* Stick remaining bits. */
|
||||
return sim_fpu_status_inexact;
|
||||
}
|
||||
else
|
||||
|
|
@ -1588,7 +1588,7 @@ sim_fpu_max (sim_fpu *f,
|
|||
if (l->sign)
|
||||
*f = *r; /* -inf < anything */
|
||||
else
|
||||
*f = *l; /* +inf > anthing */
|
||||
*f = *l; /* +inf > anything */
|
||||
return 0;
|
||||
}
|
||||
if (sim_fpu_is_infinity (r))
|
||||
|
|
@ -1596,7 +1596,7 @@ sim_fpu_max (sim_fpu *f,
|
|||
if (r->sign)
|
||||
*f = *l; /* anything > -inf */
|
||||
else
|
||||
*f = *r; /* anthing < +inf */
|
||||
*f = *r; /* anything < +inf */
|
||||
return 0;
|
||||
}
|
||||
if (l->sign > r->sign)
|
||||
|
|
@ -1611,8 +1611,8 @@ sim_fpu_max (sim_fpu *f,
|
|||
}
|
||||
ASSERT (l->sign == r->sign);
|
||||
if (l->normal_exp > r->normal_exp
|
||||
|| (l->normal_exp == r->normal_exp &&
|
||||
l->fraction > r->fraction))
|
||||
|| (l->normal_exp == r->normal_exp
|
||||
&& l->fraction > r->fraction))
|
||||
{
|
||||
/* |l| > |r| */
|
||||
if (l->sign)
|
||||
|
|
@ -1694,8 +1694,8 @@ sim_fpu_min (sim_fpu *f,
|
|||
}
|
||||
ASSERT (l->sign == r->sign);
|
||||
if (l->normal_exp > r->normal_exp
|
||||
|| (l->normal_exp == r->normal_exp &&
|
||||
l->fraction > r->fraction))
|
||||
|| (l->normal_exp == r->normal_exp
|
||||
&& l->fraction > r->fraction))
|
||||
{
|
||||
/* |l| > |r| */
|
||||
if (l->sign)
|
||||
|
|
@ -1853,7 +1853,7 @@ sim_fpu_sqrt (sim_fpu *f,
|
|||
* If (2) is false, then q = q ; otherwise q = q + 2 .
|
||||
* i+1 i i+1 i
|
||||
*
|
||||
* With some algebric manipulation, it is not difficult to see
|
||||
* With some algebraic manipulation, it is not difficult to see
|
||||
* that (2) is equivalent to
|
||||
* -(i+1)
|
||||
* s + 2 <= y (3)
|
||||
|
|
@ -1898,14 +1898,14 @@ sim_fpu_sqrt (sim_fpu *f,
|
|||
* sqrt(+-0) = +-0 ... exact
|
||||
* sqrt(inf) = inf
|
||||
* sqrt(-ve) = NaN ... with invalid signal
|
||||
* sqrt(NaN) = NaN ... with invalid signal for signaling NaN
|
||||
* sqrt(NaN) = NaN ... with invalid signal for signalling NaN
|
||||
*
|
||||
* Other methods : see the appended file at the end of the program below.
|
||||
*---------------
|
||||
*/
|
||||
|
||||
{
|
||||
/* generate sqrt(x) bit by bit */
|
||||
/* Generate sqrt(x) bit by bit. */
|
||||
unsigned64 y;
|
||||
unsigned64 q;
|
||||
unsigned64 s;
|
||||
|
|
@ -1916,7 +1916,7 @@ sim_fpu_sqrt (sim_fpu *f,
|
|||
y = r->fraction;
|
||||
f->normal_exp = (r->normal_exp >> 1); /* exp = [exp/2] */
|
||||
|
||||
/* odd exp, double x to make it even */
|
||||
/* Odd exp, double x to make it even. */
|
||||
ASSERT (y >= IMPLICIT_1 && y < IMPLICIT_4);
|
||||
if ((r->normal_exp & 1))
|
||||
{
|
||||
|
|
@ -1946,7 +1946,7 @@ sim_fpu_sqrt (sim_fpu *f,
|
|||
f->fraction = q;
|
||||
if (y != 0)
|
||||
{
|
||||
f->fraction |= 1; /* stick remaining bits */
|
||||
f->fraction |= 1; /* Stick remaining bits. */
|
||||
return sim_fpu_status_inexact;
|
||||
}
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in New Issue