gas/
* config/tc-mips.c (is_opcode_valid): Remove expansionp. (macro_build): Change invocation of is_opcode_valid. (mips_ip): Likewise. gas/testsuite/ * gas/mips/mips-no-jalx.l: Delete. * gas/mips/mips-no-jalx.s: Delete. * gas/mips/mips-jalx-2.d: New. * gas/mips/mips-jalx-2.s: New. * gas/mips/mips.exp (mips-jalx-2): Run new test. (mips-no-jalx): Remove deleted test. include/ * opcode/mips.h (INSN_MIPS16): Remove. opcodes/ * mips-dis.c (mips_arch): Remove INSN_MIPS16. * mips-opc.c (I16): Remove. (mips_builtin_op): Reclassify jalx.
This commit is contained in:
Catherine Moore
parent
f9eeb9c926
commit
f79e2745b2
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@ -1,3 +1,9 @@
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2010-05-26 Catherine Moore <clm@codesourcery.com>
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* config/tc-mips.c (is_opcode_valid): Remove expansionp.
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(macro_build): Change invocation of is_opcode_valid.
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(mips_ip): Likewise.
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2010-05-25 Nick Clifton <nickc@redhat.com>
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* Makefile.am (MOSTLYCLEANFILES): Fix typo.
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@ -1817,11 +1817,10 @@ reg_lookup (char **s, unsigned int types, unsigned int *regnop)
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}
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/* Return TRUE if opcode MO is valid on the currently selected ISA and
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architecture. If EXPANSIONP is TRUE then this check is done while
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expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
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architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
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static bfd_boolean
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is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
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is_opcode_valid (const struct mips_opcode *mo)
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{
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int isa = mips_opts.isa;
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int fp_s, fp_d;
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@ -1841,11 +1840,6 @@ is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
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if (mips_opts.ase_smartmips)
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isa |= INSN_SMARTMIPS;
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/* For user code we don't check for mips_opts.mips16 since we want
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to allow jalx if -mips16 was specified on the command line. */
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if (expansionp ? mips_opts.mips16 : file_ase_mips16)
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isa |= INSN_MIPS16;
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/* Don't accept instructions based on the ISA if the CPU does not implement
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all the coprocessor insns. */
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if (NO_ISA_COP (mips_opts.arch)
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@ -3638,7 +3632,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
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macros will never generate MDMX, MIPS-3D, or MT instructions. */
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if (strcmp (fmt, mo->args) == 0
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&& mo->pinfo != INSN_MACRO
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&& is_opcode_valid (mo, TRUE))
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&& is_opcode_valid (mo))
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break;
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++mo;
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@ -8776,7 +8770,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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gas_assert (strcmp (insn->name, str) == 0);
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ok = is_opcode_valid (insn, FALSE);
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ok = is_opcode_valid (insn);
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if (! ok)
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{
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if (insn + 1 < &mips_opcodes[NUMOPCODES]
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@ -1,3 +1,12 @@
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2010-05-26 Catherine Moore <clm@codesoucery.com>
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* gas/mips/mips-no-jalx.l: Delete.
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* gas/mips/mips-no-jalx.s: Delete.
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* gas/mips/mips-jalx-2.d: New.
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* gas/mips/mips-jalx-2.s: New.
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* gas/mips/mips.exp (mips-jalx-2): Run new test.
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(mips-no-jalx): Remove deleted test.
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2010-05-25 Daniel Jacobowitz <dan@codesourcery.com>
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Joseph Myers <joseph@codesourcery.com>
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Andrew Stubbs <ams@codesourcery.com>
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@ -0,0 +1,15 @@
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#objdump: -d
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#as:
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#name: mips jalx-2
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.*: file format .*
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Disassembly of section .text:
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[ 0-9a-f]+ <text_sym>:
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[ 0-9a-f]+: 74000000 jalx 0 <.[^>]*>
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[ 0-9a-f]+: 00000000 nop
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[ 0-9a-f]+ <.[^>]*>:
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[ 0-9a-f]+: 6500 nop
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\.\.\.
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@ -0,0 +1,10 @@
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text_sym:
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.text
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jalx 1f
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.set mips16
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.align 1
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1: nop
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.set nomips16
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.align 2
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.fill 8
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@ -1,2 +0,0 @@
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.*: Assembler messages:
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.*:3: Error: opcode not supported (at this ISA level|on this processor: .*) \(mips.*\) `jalx external_label'
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@ -1,3 +0,0 @@
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# Test the generation of jalx opcodes
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.set nomips16
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jalx external_label
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@ -526,6 +526,7 @@ if { [istarget mips*-*-vxworks*] } {
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# Check jalx handling
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run_dump_test "mips16-jalx"
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run_dump_test "mips-jalx"
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run_dump_test "mips-jalx-2"
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# Check MIPS16 HI16/LO16 relocations
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run_dump_test "mips16-hilo"
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if $has_newabi {
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@ -533,7 +534,6 @@ if { [istarget mips*-*-vxworks*] } {
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}
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run_dump_test "mips16-hilo-match"
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}
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run_list_test "mips-no-jalx" "-32"
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run_dump_test "delay"
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run_dump_test "nodelay"
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run_dump_test "mips4010"
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@ -1,3 +1,7 @@
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2010-05-26 Catherine Moore <clm@codesourcery.com>
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* opcode/mips.h (INSN_MIPS16): Remove.
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2010-04-21 Joseph Myers <joseph@codesourcery.com>
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* tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
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@ -555,8 +555,9 @@ static const unsigned int mips_isa_table[] =
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/* DSP ASE */
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#define INSN_DSP 0x00001000
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#define INSN_DSP64 0x00002000
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/* MIPS 16 ASE */
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#define INSN_MIPS16 0x00004000
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/* 0x00004000 is unused. */
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/* MIPS-3D ASE */
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#define INSN_MIPS3D 0x00008000
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@ -1,3 +1,9 @@
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2010-05-26 Catherine Moore <clm@codesoourcery.com>
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* mips-dis.c (mips_arch): Remove INSN_MIPS16.
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* mips-opc.c (I16): Remove.
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(mips_builtin_op): Reclassify jalx.
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2010-05-19 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
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@ -472,13 +472,13 @@ const struct mips_arch_choice mips_arch_choices[] =
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MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
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page 1. */
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{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
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ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
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ISA_MIPS32 | INSN_SMARTMIPS,
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mips_cp0_names_mips3264,
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mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
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mips_hwr_names_numeric },
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{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
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(ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
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(ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
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| INSN_MIPS3D | INSN_MT),
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mips_cp0_names_mips3264r2,
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mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
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@ -486,13 +486,13 @@ const struct mips_arch_choice mips_arch_choices[] =
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/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
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{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
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ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
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ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
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mips_cp0_names_mips3264,
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mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
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mips_hwr_names_numeric },
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{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
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(ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
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(ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
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| INSN_DSP64 | INSN_MT | INSN_MDMX),
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mips_cp0_names_mips3264r2,
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mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
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@ -524,7 +524,7 @@ const struct mips_arch_choice mips_arch_choices[] =
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/* This entry, mips16, is here only for ISA/processor selection; do
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not print its name. */
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{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
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{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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};
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@ -96,9 +96,6 @@
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#define I4_33 INSN_ISA4_32R2
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#define I5_33 INSN_ISA5_32R2
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/* MIPS16 ASE support. */
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#define I16 INSN_MIPS16
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/* MIPS64 MIPS-3D ASE support. */
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#define M3D INSN_MIPS3D
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@ -739,7 +736,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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assembler, but will never match user input (because the line above
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will match first). */
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{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
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{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
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{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 },
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{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
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{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
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{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
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