* config/tc-arm.c (parse_operands): Encode APSR_nzcv as r15.
(do_vmrs): New function. (do_vmsr): New function. (insns): Add vmrs and vmsr. * gas/arm/vfp1xD.s: Add vmrs and vmsr instructions. * gas/arm/vfp1xD.d: Update expected disassembly.
This commit is contained in:
parent
c4d1af07ab
commit
f7c21dc7b8
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@ -1,3 +1,10 @@
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2009-11-16 Viktor Kutuzov <vkutuzov@accesssoftek.com>
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* config/tc-arm.c (parse_operands): Encode APSR_nzcv as r15.
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(do_vmrs): New function.
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(do_vmsr): New function.
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(insns): Add vmrs and vmsr.
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2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (md_assemble): Check destination operand
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@ -6303,6 +6303,8 @@ parse_operands (char *str, const unsigned char *pattern)
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if (found != 15)
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goto failure;
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inst.operands[i].isvec = 1;
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/* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
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inst.operands[i].reg = REG_PC;
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}
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else
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goto failure;
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@ -7614,6 +7616,49 @@ do_vfp_nsyn_msr (void)
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return SUCCESS;
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}
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static void
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do_vmrs (void)
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{
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unsigned Rt = inst.operands[0].reg;
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if (thumb_mode && inst.operands[0].reg == REG_SP)
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{
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inst.error = BAD_SP;
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return;
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}
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/* APSR_ sets isvec. All other refs to PC are illegal. */
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if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
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{
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inst.error = BAD_PC;
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return;
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}
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if (inst.operands[1].reg != 1)
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first_error (_("operand 1 must be FPSCR"));
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inst.instruction |= (Rt << 12);
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}
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static void
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do_vmsr (void)
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{
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unsigned Rt = inst.operands[1].reg;
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if (thumb_mode)
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reject_bad_reg (Rt);
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else if (Rt == REG_PC)
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{
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inst.error = BAD_PC;
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return;
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}
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if (inst.operands[0].reg != 1)
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first_error (_("operand 0 must be FPSCR"));
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inst.instruction |= (Rt << 12);
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}
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static void
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do_mrs (void)
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{
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@ -17168,6 +17213,8 @@ static const struct asm_opcode insns[] =
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cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
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cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
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cCE("fmstat", ef1fa10, 0, (), noargs),
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cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
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cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
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cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
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cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
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cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
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@ -1,3 +1,8 @@
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2009-11-16 Viktor Kutuzov <vkutuzov@accesssoftek.com>
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* gas/arm/vfp1xD.s: Add vmrs and vmsr instructions.
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* gas/arm/vfp1xD.d: Update expected disassembly.
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2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/lock-1-intel.d: Updated.
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@ -249,5 +249,34 @@ Disassembly of section .text:
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0+3bc <[^>]*> eee70a10 (vmsr|fmxr) mvfr0, r0
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0+3c0 <[^>]*> eee60a10 (vmsr|fmxr) mvfr1, r0
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0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) <impl def 0xc>, r0
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0+3c8 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+3cc <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+3c8 <[^>]*> eef10a10 vmrs r0, fpscr
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0+3cc <[^>]*> eef11a10 vmrs r1, fpscr
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0+3d0 <[^>]*> eef12a10 vmrs r2, fpscr
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0+3d4 <[^>]*> eef13a10 vmrs r3, fpscr
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0+3d8 <[^>]*> eef14a10 vmrs r4, fpscr
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0+3dc <[^>]*> eef15a10 vmrs r5, fpscr
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0+3e0 <[^>]*> eef16a10 vmrs r6, fpscr
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0+3e4 <[^>]*> eef17a10 vmrs r7, fpscr
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0+3e8 <[^>]*> eef18a10 vmrs r8, fpscr
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0+3ec <[^>]*> eef19a10 vmrs r9, fpscr
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0+3f0 <[^>]*> eef1aa10 vmrs sl, fpscr
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0+3f4 <[^>]*> eef1ba10 vmrs fp, fpscr
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0+3f8 <[^>]*> eef1ca10 vmrs ip, fpscr
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0+3fc <[^>]*> eef1ea10 vmrs lr, fpscr
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0+400 <[^>]*> eef1fa10 vmrs APSR_nzcv, fpscr
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0+404 <[^>]*> eee10a10 vmsr fpscr, r0
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0+408 <[^>]*> eee11a10 vmsr fpscr, r1
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0+40c <[^>]*> eee12a10 vmsr fpscr, r2
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0+410 <[^>]*> eee13a10 vmsr fpscr, r3
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0+414 <[^>]*> eee14a10 vmsr fpscr, r4
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0+418 <[^>]*> eee15a10 vmsr fpscr, r5
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0+41c <[^>]*> eee16a10 vmsr fpscr, r6
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0+420 <[^>]*> eee17a10 vmsr fpscr, r7
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0+424 <[^>]*> eee18a10 vmsr fpscr, r8
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0+428 <[^>]*> eee19a10 vmsr fpscr, r9
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0+42c <[^>]*> eee1aa10 vmsr fpscr, sl
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0+430 <[^>]*> eee1ba10 vmsr fpscr, fp
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0+434 <[^>]*> eee1ca10 vmsr fpscr, ip
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0+438 <[^>]*> eee1ea10 vmsr fpscr, lr
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0+43c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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@ -349,5 +349,36 @@ F:
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fmxr mvfr1, r0
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fmxr c12, r0
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nop
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@ ARM VMSR/VMRS instructions
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vmrs r0, FPSCR
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vmrs r1, FPSCR
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vmrs r2, FPSCR
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vmrs r3, FPSCR
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vmrs r4, FPSCR
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vmrs r5, FPSCR
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vmrs r6, FPSCR
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vmrs r7, FPSCR
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vmrs r8, FPSCR
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vmrs r9, FPSCR
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vmrs r10, FPSCR
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vmrs r11, FPSCR
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vmrs r12, FPSCR
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vmrs r14, FPSCR
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vmrs APSR_nzcv, FPSCR
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vmsr FPSCR, r0
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vmsr FPSCR, r1
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vmsr FPSCR, r2
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vmsr FPSCR, r3
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vmsr FPSCR, r4
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vmsr FPSCR, r5
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vmsr FPSCR, r6
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vmsr FPSCR, r7
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vmsr FPSCR, r8
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vmsr FPSCR, r9
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vmsr FPSCR, r10
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vmsr FPSCR, r11
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vmsr FPSCR, r12
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vmsr FPSCR, r14
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nop
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