Arm: Backport hlt to all architectures.
The software trap instruction HLT that was introduced in Armv8-a is used
as the semihosting trap instruction in AArch64. In order to allow systems
configured to run AArch64 code to also run AArch32 with semihosting it was
decided that AArch32 should also use HLT in the case of the "mixed mode"
environment. This requires that HLT also be backported to all earlier
architectures. The instruction is in the undefined encoding space earlier
architectures but must trigger a semihosting trap [3].
The Arm Architectural Reference Manual [1] doesn't explicitly mention this
however this is an explicit requirement in the Semihosting-v2 protocol [2].
[1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
[3] 19a6e31c9d
gas/ChangeLog:
* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
hlt to armv1.
* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
* testsuite/gas/arm/hlt.d: New test.
* testsuite/gas/arm/hlt.s: New test.
opcodes/ChangeLog:
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
This commit is contained in:
Tamar Christina
parent
bd756351a6
commit
f7dd2fb2e2
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@ -1,3 +1,11 @@
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
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hlt to armv1.
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* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
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* testsuite/gas/arm/hlt.d: New test.
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* testsuite/gas/arm/hlt.s: New test.
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
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@ -20187,11 +20187,22 @@ static const struct asm_opcode insns[] =
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#define THUMB_VARIANT & arm_ext_v8
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tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
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TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
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TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
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ldrexd, t_ldrexd),
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TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
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strexd, t_strexd),
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/* Defined in V8 but is in undefined encoding space for earlier
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architectures. However earlier architectures are required to treat
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this instuction as a semihosting trap as well. Hence while not explicitly
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defined as such, it is in fact correct to define the instruction for all
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architectures. */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v1
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v1
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TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
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/* ARMv8 T32 only. */
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#undef ARM_VARIANT
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#define ARM_VARIANT NULL
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@ -5,4 +5,6 @@ Attribute Section: aeabi
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File Attributes
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Tag_CPU_arch: v8
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Tag_CPU_arch_profile: Application
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Tag_ARM_ISA_use: Yes
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Tag_THUMB_ISA_use: Thumb-2
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@ -0,0 +1,35 @@
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#objdump: -d
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# This test is only valid on ELF based ports.
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#notarget: *-*-pe *-*-wince
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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[^:]+:\s+ba80 hlt 0x0000
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[^:]+:\s+ba8f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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[^:]+:\s+ba80 hlt 0x0000
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[^:]+:\s+ba8f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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[^:]+:\s+ba80 hlt 0x0000
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[^:]+:\s+ba8f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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[^:]+:\s+ba80 hlt 0x0000
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[^:]+:\s+ba8f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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[^:]+:\s+ba80 hlt 0x0000
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[^:]+:\s+ba8f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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[^:]+:\s+e1000070 hlt 0x0000
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[^:]+:\s+e100007f hlt 0x000f
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@ -0,0 +1,22 @@
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# Test that hlt is available for all architectures.
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.macro gen_for_arch arch, has_thumb
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.arch \arch
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.ifc "yes","\has_thumb"
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.thumb
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hlt
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hlt 0xf
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.endif
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.arm
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hlt
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hlt 0xf
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.endm
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gen_for_arch armv8-a, yes
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gen_for_arch armv7-a, yes
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gen_for_arch armv6, yes
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gen_for_arch armv5t, yes
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gen_for_arch armv4t, yes
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gen_for_arch armv3, no
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gen_for_arch armv2, no
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gen_for_arch armv1, no
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@ -1,3 +1,7 @@
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23212
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@ -1788,7 +1788,8 @@ static const struct opcode32 arm_opcodes[] =
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/* V8 instructions. */
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
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0x0320f005, 0x0fffffff, "sevl"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
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/* Defined in V8 but is in NOP space so available to all arch. */
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
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0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
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