merge binutils and gdb sparc disassemblers
This commit is contained in:
Jim Kingdon
parent
d1c89c2817
commit
f7ed13c7d5
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@ -69,24 +69,3 @@ strip.1
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version.c
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Do-last:
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v9dirty="sparc-pinsn.c"
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if ( echo $* | grep keep\-v9 > /dev/null ) ; then
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echo Keeping v9 in ${v9dirty}
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else
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for i in ${v9dirty} ; do
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echo Sanitizing v9 in $i
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rm -f new
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sed '/^#ifndef[ ]NO_V9/,/^#endif/d' < $i > new
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if grep -s -i v9 new ; then
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echo ***** SANITIZING V9 IN $i FAILED *****
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fi
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if [ -n "${safe}" ] ; then
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mv $i .Recover
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else
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rm $i
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fi
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mv new $i
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done
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fi
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@ -1,5 +1,9 @@
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Wed Mar 31 10:25:29 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
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* objdump.c (disassemble_data): print_insn_sparc is now a
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`disassemble' not a `print'.
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Makefile.in: Remove sparc-pinsn.c (now in libopcodes.a).
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* objdump.c (disassemble_data): Use new read_memory_func stuff.
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Thu Mar 25 10:38:11 1993 Ken Raeburn (raeburn@cambridge.cygnus.com)
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@ -112,7 +112,7 @@ INCLUDES = -I. -I$(srcdir) -I$(BASEDIR)/include -I$(BASEDIR)/bfd
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# When adding .o files, to make VPATH work in Sun Make, you have to
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# also add a foo.o: foo.c line at the bottom of the file.
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DISASMS = i960-pinsn.o sparc-pinsn.o am29k-pinsn.o
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DISASMS = i960-pinsn.o am29k-pinsn.o
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#
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## Random definitions
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@ -156,7 +156,7 @@ testsuite:
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check: all
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/bin/sh $(srcdir)/sanity.sh .
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test-install:
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installcheck:
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/bin/sh $(srcdir)/sanity.sh $(bindir)
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info: binutils.info
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@ -411,7 +411,6 @@ not-ranlib.o:not-ranlib.c
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not-strip.o:not-strip.c
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objdump.o: objdump.c
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size.o: size.c
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sparc-pinsn.o: sparc-pinsn.c
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strip.o:strip.c
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version.o: $(srcdir)/version.c
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$(CC) $(CFLAGS) $(INCLUDES) $(HDEFINES) $(TDEFINES) -DVERSION='"$(VERSION)"' -c $(srcdir)/version.c
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@ -311,7 +311,6 @@ disassemble_data (abfd)
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disassembler_ftype disassemble = 0; /* New style */
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unsigned int print_insn_a29k ();
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unsigned int print_insn_i960 ();
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unsigned int print_insn_sparc ();
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unsigned int print_insn_h8300 ();
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enum bfd_architecture a;
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struct disassemble_info disasm_info;
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@ -378,7 +377,7 @@ disassemble_data (abfd)
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switch (a)
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{
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case bfd_arch_sparc:
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print = print_insn_sparc;
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disassemble = print_insn_sparc;
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break;
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case bfd_arch_z8k:
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if (bfd_get_mach(abfd) == bfd_mach_z8001)
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@ -1,3 +1,7 @@
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Wed Mar 31 12:52:12 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
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* sparc-pinsn.c: Much abridged, just calls version in libopcodes.a.
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Wed Mar 31 21:23:41 1993 K. Richard Pixley (rich@rtl.cygnus.com)
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* core.c (dis_asm_read_memory): drop fourth arg which conflicts
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@ -1,7 +1,7 @@
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/* Print SPARC instructions for GDB, the GNU Debugger.
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Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
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/* Print sparc instructions for GDB, the GNU debugger.
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Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -18,460 +18,19 @@ along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "defs.h"
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#include "symtab.h"
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#include "opcode/sparc.h"
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#include "gdbcore.h"
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#include <string.h>
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#include "target.h"
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#include "dis-asm.h"
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#define freg_names (®_names[4 * 8])
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/* Print the instruction at address MEMADDR in debugged memory,
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on STREAM. Returns length of the instruction, in bytes. */
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union sparc_insn
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{
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unsigned long int code;
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struct
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{
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unsigned int anop:2;
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#define op ldst.anop
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unsigned int anrd:5;
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#define rd ldst.anrd
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unsigned int op3:6;
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unsigned int anrs1:5;
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#define rs1 ldst.anrs1
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unsigned int i:1;
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unsigned int anasi:8;
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#define asi ldst.anasi
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unsigned int anrs2:5;
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#define rs2 ldst.anrs2
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#define shcnt rs2
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} ldst;
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struct
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{
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unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
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unsigned int IMM13:13;
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#define imm13 IMM13.IMM13
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} IMM13;
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struct
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{
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unsigned int anop:2;
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unsigned int a:1;
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unsigned int cond:4;
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unsigned int op2:3;
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unsigned int DISP22:22;
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#define disp22 branch.DISP22
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} branch;
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#define imm22 disp22
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struct
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{
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unsigned int anop:2;
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unsigned int adisp30:30;
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#define disp30 call.adisp30
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} call;
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};
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/* Nonzero if INSN is the opcode for a delayed branch. */
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static int
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is_delayed_branch (insn)
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union sparc_insn insn;
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{
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unsigned int i;
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for (i = 0; i < NUMOPCODES; ++i)
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{
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const struct sparc_opcode *opcode = &sparc_opcodes[i];
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if ((opcode->match & insn.code) == opcode->match
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&& (opcode->lose & insn.code) == 0)
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return (opcode->flags & F_DELAYED);
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}
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return 0;
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}
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static int opcodes_sorted = 0;
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extern void qsort ();
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/* Print one instruction from MEMADDR on STREAM.
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We suffix the instruction with a comment that gives the absolute
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address involved, as well as its symbolic form, if the instruction
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is preceded by a findable `sethi' and it either adds an immediate
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displacement to that register, or it is an `add' or `or' instruction
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on that register. */
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int
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print_insn (memaddr, stream)
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CORE_ADDR memaddr;
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FILE *stream;
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{
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union sparc_insn insn;
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disassemble_info info;
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register unsigned int i;
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GDB_INIT_DISASSEMBLE_INFO(info, stream);
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if (!opcodes_sorted)
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{
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static int compare_opcodes ();
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qsort ((char *) sparc_opcodes, NUMOPCODES,
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sizeof (sparc_opcodes[0]), compare_opcodes);
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opcodes_sorted = 1;
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}
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read_memory (memaddr, (char *) &insn, sizeof (insn));
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for (i = 0; i < NUMOPCODES; ++i)
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{
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const struct sparc_opcode *opcode = &sparc_opcodes[i];
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if ((opcode->match & insn.code) == opcode->match
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&& (opcode->lose & insn.code) == 0)
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{
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/* Nonzero means that we have found an instruction which has
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the effect of adding or or'ing the imm13 field to rs1. */
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int imm_added_to_rs1 = 0;
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/* Nonzero means that we have found a plus sign in the args
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field of the opcode table. */
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int found_plus = 0;
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/* Do we have an `add' or `or' instruction where rs1 is the same
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as rsd, and which has the i bit set? */
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if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
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/* (or) (add) */
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&& insn.rs1 == insn.rd)
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imm_added_to_rs1 = 1;
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if (insn.rs1 != insn.rd
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&& strchr (opcode->args, 'r') != 0)
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/* Can't do simple format if source and dest are different. */
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continue;
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fputs_filtered (opcode->name, stream);
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{
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register const char *s;
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if (opcode->args[0] != ',')
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fputs_filtered (" ", stream);
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for (s = opcode->args; *s != '\0'; ++s)
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{
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if (*s == ',')
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{
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fputs_filtered (",", stream);
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++s;
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if (*s == 'a')
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{
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fputs_filtered ("a", stream);
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++s;
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}
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fputs_filtered (" ", stream);
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}
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switch (*s)
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{
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case '+':
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found_plus = 1;
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/* note fall-through */
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default:
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fprintf_filtered (stream, "%c", *s);
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break;
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case '#':
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fputs_filtered ("0", stream);
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break;
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#define reg(n) fprintf_filtered (stream, "%%%s", reg_names[n])
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case '1':
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case 'r':
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reg (insn.rs1);
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break;
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case '2':
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reg (insn.rs2);
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break;
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case 'd':
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reg (insn.rd);
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break;
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#undef reg
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#define freg(n) fprintf_filtered (stream, "%%%s", freg_names[n])
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case 'e':
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case 'v': /* double/even */
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case 'V': /* quad/multiple of 4 */
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freg (insn.rs1);
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break;
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case 'f':
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case 'B': /* double/even */
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case 'R': /* quad/multiple of 4 */
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freg (insn.rs2);
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break;
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case 'g':
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case 'H': /* double/even */
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case 'J': /* quad/multiple of 4 */
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freg (insn.rd);
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break;
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#undef freg
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#define creg(n) fprintf_filtered (stream, "%%c%u", (unsigned int) (n))
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case 'b':
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creg (insn.rs1);
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break;
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case 'c':
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creg (insn.rs2);
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break;
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case 'D':
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creg (insn.rd);
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break;
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#undef creg
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case 'h':
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fprintf_filtered (stream, "%%hi(%#x)",
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(int) insn.imm22 << 10);
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break;
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case 'i':
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{
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/* We cannot trust the compiler to sign-extend
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when extracting the bitfield, hence the shifts. */
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int imm = ((int) insn.imm13 << 19) >> 19;
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/* Check to see whether we have a 1+i, and take
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note of that fact.
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FIXME: No longer true/relavant ???
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Note: because of the way we sort the table,
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we will be matching 1+i rather than i+1,
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so it is OK to assume that i is after +,
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not before it. */
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if (found_plus)
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imm_added_to_rs1 = 1;
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if (imm <= 9)
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fprintf_filtered (stream, "%d", imm);
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else
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fprintf_filtered (stream, "%#x", imm);
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}
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break;
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case 'L':
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print_address ((CORE_ADDR) memaddr + insn.disp30 * 4,
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stream);
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break;
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case 'l':
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if ((insn.code >> 22) == 0)
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/* Special case for `unimp'. Don't try to turn
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it's operand into a function offset. */
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fprintf_filtered (stream, "%#x",
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(int) (((int) insn.disp22 << 10) >> 10));
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else
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/* We cannot trust the compiler to sign-extend
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when extracting the bitfield, hence the shifts. */
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print_address ((CORE_ADDR)
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(memaddr
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+ (((int) insn.disp22 << 10) >> 10) * 4),
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stream);
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break;
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case 'A':
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fprintf_filtered (stream, "(%d)", (int) insn.asi);
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break;
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case 'C':
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fputs_filtered ("%csr", stream);
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break;
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case 'F':
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fputs_filtered ("%fsr", stream);
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break;
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case 'p':
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fputs_filtered ("%psr", stream);
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break;
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case 'q':
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fputs_filtered ("%fq", stream);
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break;
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case 'Q':
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fputs_filtered ("%cq", stream);
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break;
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case 't':
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fputs_filtered ("%tbr", stream);
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break;
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case 'w':
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fputs_filtered ("%wim", stream);
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break;
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case 'y':
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fputs_filtered ("%y", stream);
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break;
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}
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}
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}
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/* If we are adding or or'ing something to rs1, then
|
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check to see whether the previous instruction was
|
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a sethi to the same register as in the sethi.
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If so, attempt to print the result of the add or
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or (in this context add and or do the same thing)
|
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and its symbolic value. */
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if (imm_added_to_rs1)
|
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{
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union sparc_insn prev_insn;
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int errcode;
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errcode = target_read_memory (memaddr - 4,
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(char *)&prev_insn, sizeof (prev_insn));
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if (errcode == 0)
|
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{
|
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/* If it is a delayed branch, we need to look at the
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instruction before the delayed branch. This handles
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sequences such as
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sethi %o1, %hi(_foo), %o1
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call _printf
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or %o1, %lo(_foo), %o1
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*/
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if (is_delayed_branch (prev_insn))
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errcode = target_read_memory
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(memaddr - 8, (char *)&prev_insn, sizeof (prev_insn));
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}
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/* If there was a problem reading memory, then assume
|
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the previous instruction was not sethi. */
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if (errcode == 0)
|
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{
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/* Is it sethi to the same register? */
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if ((prev_insn.code & 0xc1c00000) == 0x01000000
|
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&& prev_insn.rd == insn.rs1)
|
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{
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fprintf_filtered (stream, "\t! ");
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/* We cannot trust the compiler to sign-extend
|
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when extracting the bitfield, hence the shifts. */
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print_address (((int) prev_insn.imm22 << 10)
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| (insn.imm13 << 19) >> 19, stream);
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}
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}
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}
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return sizeof (insn);
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}
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}
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printf_filtered ("%#8x", insn.code);
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return sizeof (insn);
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}
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/* Compare opcodes A and B. */
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static int
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compare_opcodes (a, b)
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char *a, *b;
|
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{
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struct sparc_opcode *op0 = (struct sparc_opcode *) a;
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struct sparc_opcode *op1 = (struct sparc_opcode *) b;
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unsigned long int match0 = op0->match, match1 = op1->match;
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unsigned long int lose0 = op0->lose, lose1 = op1->lose;
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register unsigned int i;
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/* If a bit is set in both match and lose, there is something
|
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wrong with the opcode table. */
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if (match0 & lose0)
|
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{
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fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
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op0->name, match0, lose0);
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op0->lose &= ~op0->match;
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lose0 = op0->lose;
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}
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if (match1 & lose1)
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{
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fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
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op1->name, match1, lose1);
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op1->lose &= ~op1->match;
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lose1 = op1->lose;
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}
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/* Because the bits that are variable in one opcode are constant in
|
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another, it is important to order the opcodes in the right order. */
|
||||
for (i = 0; i < 32; ++i)
|
||||
{
|
||||
unsigned long int x = 1 << i;
|
||||
int x0 = (match0 & x) != 0;
|
||||
int x1 = (match1 & x) != 0;
|
||||
|
||||
if (x0 != x1)
|
||||
return x1 - x0;
|
||||
}
|
||||
|
||||
for (i = 0; i < 32; ++i)
|
||||
{
|
||||
unsigned long int x = 1 << i;
|
||||
int x0 = (lose0 & x) != 0;
|
||||
int x1 = (lose1 & x) != 0;
|
||||
|
||||
if (x0 != x1)
|
||||
return x1 - x0;
|
||||
}
|
||||
|
||||
/* They are functionally equal. So as long as the opcode table is
|
||||
valid, we can put whichever one first we want, on aesthetic grounds. */
|
||||
|
||||
/* Our first aesthetic ground is that aliases defer to real insns. */
|
||||
{
|
||||
int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
|
||||
if (alias_diff != 0)
|
||||
/* Put the one that isn't an alias first. */
|
||||
return alias_diff;
|
||||
}
|
||||
|
||||
/* Except for aliases, two "identical" instructions had
|
||||
better have the same opcode. This is a sanity check on the table. */
|
||||
i = STRCMP (op0->name, op1->name);
|
||||
if (i)
|
||||
if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
|
||||
return i;
|
||||
else
|
||||
fprintf (stderr,
|
||||
"Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
|
||||
op0->name, op1->name);
|
||||
|
||||
/* Fewer arguments are preferred. */
|
||||
{
|
||||
int length_diff = strlen (op0->args) - strlen (op1->args);
|
||||
if (length_diff != 0)
|
||||
/* Put the one with fewer arguments first. */
|
||||
return length_diff;
|
||||
}
|
||||
|
||||
/* Put 1+i before i+1. */
|
||||
{
|
||||
char *p0 = (char *) strchr(op0->args, '+');
|
||||
char *p1 = (char *) strchr(op1->args, '+');
|
||||
|
||||
if (p0 && p1)
|
||||
{
|
||||
/* There is a plus in both operands. Note that a plus
|
||||
sign cannot be the first character in args,
|
||||
so the following [-1]'s are valid. */
|
||||
if (p0[-1] == 'i' && p1[1] == 'i')
|
||||
/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
|
||||
return 1;
|
||||
if (p0[1] == 'i' && p1[-1] == 'i')
|
||||
/* op0 is 1+i and op1 is i+1, so op0 goes first. */
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* They are, as far as we can tell, identical.
|
||||
Since qsort may have rearranged the table partially, there is
|
||||
no way to tell which one was first in the opcode table as
|
||||
written, so just say there are equal. */
|
||||
return 0;
|
||||
return print_insn_sparc (memaddr, &info);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
Wed Mar 31 17:40:16 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
|
||||
|
||||
* dis-asm.h: Add print_insn_sparc.
|
||||
|
||||
Wed Mar 31 17:51:42 1993 Ian Lance Taylor (ian@cygnus.com)
|
||||
|
||||
* bfd.h: Updated for BFD_RELOC_MIPS_GPREL and bfd_[gs]et_gp_size
|
||||
|
|
@ -11,7 +15,7 @@ Wed Mar 31 16:35:12 1993 Stu Grossman (grossman@cygnus.com)
|
|||
Tue Mar 30 19:09:23 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
|
||||
|
||||
* dis-asm.h (disassembler_info): Add read_memory_func,
|
||||
memory_error_func, buffer, buffer_length, and buffer_vma.
|
||||
memory_error_func, buffer, and length.
|
||||
({GDB_,}INIT_DISASSEMBLE_INFO): Set them.
|
||||
print_insn_*: Remove second argument.
|
||||
|
||||
|
|
|
|||
|
|
@ -80,3 +80,4 @@ extern int print_insn_m68k PARAMS ((bfd_vma,disassemble_info*));
|
|||
extern int print_insn_z8001 PARAMS ((bfd_vma,disassemble_info*));
|
||||
extern int print_insn_z8002 PARAMS ((bfd_vma,disassemble_info*));
|
||||
extern int print_insn_h8500 PARAMS ((bfd_vma,disassemble_info*));
|
||||
extern int print_insn_sparc PARAMS ((bfd_vma,disassemble_info*));
|
||||
|
|
|
|||
|
|
@ -52,4 +52,25 @@ else
|
|||
mv new sparc-opc.c
|
||||
fi
|
||||
|
||||
|
||||
v9dirty="sparc-pinsn.c"
|
||||
|
||||
if ( echo $* | grep keep\-v9 > /dev/null ) ; then
|
||||
echo Keeping v9 in ${v9dirty}
|
||||
else
|
||||
for i in ${v9dirty} ; do
|
||||
echo Sanitizing v9 in $i
|
||||
rm -f new
|
||||
sed '/^#ifndef[ ]NO_V9/,/^#endif/d' < $i > new
|
||||
if grep -s -i v9 new ; then
|
||||
echo ***** SANITIZING V9 IN $i FAILED *****
|
||||
fi
|
||||
if [ -n "${safe}" ] ; then
|
||||
mv $i .Recover
|
||||
else
|
||||
rm $i
|
||||
fi
|
||||
mv new $i
|
||||
done
|
||||
fi
|
||||
# End of file.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,25 @@
|
|||
Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
|
||||
|
||||
* Makefile.in: Add sparc-dis.c.
|
||||
sparc-dis.c: New file, merges binutils and gdb versions as follows:
|
||||
From GDB:
|
||||
Add `add' instruction to the set that get checked
|
||||
for a preceding `sethi' in order to print an absolute address.
|
||||
* (print_insn): Disassembly prefers real instructions.
|
||||
(is_delayed_branch): Speed up.
|
||||
* sparc-opcode.h: Add ALIAS bit to aliases. Fix up opcode tables.
|
||||
Still missing some float ops, and needs testing.
|
||||
* sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by
|
||||
F_ALIAS. Use printf, not fprintf, when not passing a file
|
||||
pointer...
|
||||
(compare_opcodes): Check that identical instructions have
|
||||
identical opcodes, complain otherwise.
|
||||
From binutils:
|
||||
* New 'm' arg.
|
||||
* Include reg_names.
|
||||
From neither:
|
||||
Use dis-asm.h/read_memory_func interface.
|
||||
|
||||
Wed Mar 31 20:49:06 1993 K. Richard Pixley (rich@rtl.cygnus.com)
|
||||
|
||||
* h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data):
|
||||
|
|
|
|||
|
|
@ -61,8 +61,10 @@ DEP = mkdep
|
|||
|
||||
TARGETLIB = libopcodes.a
|
||||
|
||||
|
||||
DIS_LIBS = i386-dis.o z8k-dis.o m68k-dis.o mips-dis.o h8500-dis.o dis-buf.o
|
||||
# To circumvent a Sun make VPATH bug, each file listed here
|
||||
# should also have a foo.o: foo.c line further along in this file.
|
||||
DIS_LIBS = i386-dis.o z8k-dis.o m68k-dis.o mips-dis.o h8500-dis.o dis-buf.o \
|
||||
sparc-dis.o
|
||||
|
||||
OFILES = $(DIS_LIBS) sparc-opc.o m68881-ext.o
|
||||
#### host and target dependent Makefile fragments come in here.
|
||||
|
|
@ -114,6 +116,7 @@ $(TARGETLIB): $(OFILES)
|
|||
sparc-opc.o: sparc-opc.c
|
||||
m68881-ext.o: m68881-ext.c
|
||||
h8500-dis.o: h8500-dis.c
|
||||
sparc-dis.o: sparc-dis.c
|
||||
|
||||
tags etags: TAGS
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue