New 'hack' generator
This commit is contained in:
Gavin Romig-Koch
parent
db48d8218f
commit
f87366ec28
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@ -1,3 +1,33 @@
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start-sanitize-vr4xxx
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1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
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* vr4run.c: New.
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* Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
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tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
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tmp-run-hack) : New.
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* configure.in (mips64vr4xxx): Switch to using the HACK
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generator. Set TARGET_ENABLE_FR.
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* m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
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DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
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Drop the "64" qualifier to get the HACK generator working.
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Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
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Add vr4121 where necessary.
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* mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
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qualifier to get the hack generator working.
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(do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
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(DSLL): Use do_dsll.
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(DSLLV): Use do_dsllv.
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(DSRA): Use do_dsra.
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(DSRL): Use do_dsrl.
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(DSRLV): Use do_dsrlv.
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(BC1): Move *vr4100,*vr4111, and *vr4121 to get the HACK
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generator working.
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(CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
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get the HACK generator working.
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* vr.igen: Add *vr4320 where missing.
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(MACC) Rename to get the HACK generator working.
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(DMACC,MACCS,DMACCS): Add the 64.
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start-sanitize-vr4320
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1998-12-14 Gavin Romig-Koch <gavin@cygnus.com>
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@ -69,16 +69,11 @@ SIM_OBJS = \
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# List of flags to always pass to $(CC).
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SIM_SUBTARGET=@SIM_SUBTARGET@
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SIM_NO_CFLAGS = -DWITH_IGEN=0
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SIM_IGEN_CFLAGS = -DWITH_IGEN=1
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SIM_M16_CFLAGS = -DWITH_IGEN=1
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# FIXME: Hack to find syscall.h? Better support for syscall.h
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# is in progress.
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SIM_EXTRA_CFLAGS = \
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$(SIM_SUBTARGET) \
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-I$(srcdir)/../../newlib/libc/sys/idt \
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$(SIM_@sim_gen@_CFLAGS)
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-I$(srcdir)/../../newlib/libc/sys/idt
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SIM_EXTRA_CLEAN = clean-extra
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@ -97,30 +92,6 @@ SIM_NO_INTERP = oengine.c
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interp.o: $(srcdir)/interp.c config.h sim-main.h $(SIM_@sim_gen@_INTERP)
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#
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# Old deprecated generator
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#
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SIM_NO_ALL = oengine.c
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oengine.c: gencode
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./gencode @SIMCONF@ > tmp-oengine
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mv tmp-oengine oengine.c
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gencode: gencode.o getopt.o getopt1.o
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$(CC_FOR_BUILD) -o $@ gencode.o getopt.o getopt1.o
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gencode.o: $(srcdir)/gencode.c
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$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/gencode.c
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getopt.o: $(srcdir)/../../libiberty/getopt.c
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$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt.c
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getopt1.o: $(srcdir)/../../libiberty/getopt1.c
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$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt1.c
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../igen/igen:
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cd ../igen && $(MAKE)
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@ -165,7 +136,6 @@ BUILT_SRC_FROM_GEN = \
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$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
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$(BUILT_SRC_FROM_IGEN): tmp-igen
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tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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@ -345,5 +315,206 @@ clean-extra:
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rm -f $(BUILT_SRC_FROM_GEN)
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rm -f $(BUILT_SRC_FROM_IGEN)
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rm -f $(BUILT_SRC_FROM_M16)
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rm -f tmp-igen
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rm -f tmp-m16
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rm -f tmp-*
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rm -f libhack.a hack
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rm -f m16* m32* itable*
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# start-sanitize-vr4xxx
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# HACK ....
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SIM_HACK_OBJ = \
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itable.o \
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m16vr4111_icache.o m16vr4111_idecode.o m16vr4111_model.o \
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m16vr4111_run.o m16vr4111_semantics.o m16vr4111_support.o \
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m16vr4121_icache.o m16vr4121_idecode.o m16vr4121_model.o \
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m16vr4121_run.o m16vr4121_semantics.o m16vr4121_support.o \
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m32mipsIV_engine.o m32mipsIV_icache.o m32mipsIV_idecode.o \
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m32mipsIV_model.o m32mipsIV_semantics.o m32mipsIV_support.o \
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m32vr4100_engine.o m32vr4100_icache.o m32vr4100_idecode.o \
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m32vr4100_model.o m32vr4100_semantics.o m32vr4100_support.o \
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m32vr4111_engine.o m32vr4111_icache.o m32vr4111_idecode.o \
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m32vr4111_model.o m32vr4111_semantics.o m32vr4111_support.o \
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m32vr4320_engine.o m32vr4320_icache.o m32vr4320_idecode.o \
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m32vr4320_model.o m32vr4320_semantics.o m32vr4320_support.o \
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m32vr4121_engine.o m32vr4121_icache.o m32vr4121_idecode.o \
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m32vr4121_model.o m32vr4121_semantics.o m32vr4121_support.o \
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vr4run.o
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HACK_OBJS = \
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itable.o m16vr4111_icache.o m16vr4111_idecode.o \
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m16vr4111_model.o m16vr4111_run.o m16vr4111_semantics.o \
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m16vr4111_support.o m16vr4121_icache.o m16vr4121_idecode.o \
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m16vr4121_model.o m16vr4121_run.o m16vr4121_semantics.o \
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m16vr4121_support.o m32mipsIV_engine.o m32mipsIV_icache.o \
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m32mipsIV_idecode.o m32mipsIV_model.o m32mipsIV_semantics.o \
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m32mipsIV_support.o m32vr4100_engine.o m32vr4100_icache.o \
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m32vr4100_idecode.o m32vr4100_model.o m32vr4100_semantics.o \
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m32vr4100_support.o m32vr4111_engine.o m32vr4111_icache.o \
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m32vr4111_idecode.o m32vr4111_model.o m32vr4111_semantics.o \
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m32vr4111_support.o m32vr4320_engine.o m32vr4320_icache.o \
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m32vr4320_idecode.o m32vr4320_model.o m32vr4320_semantics.o \
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m32vr4320_support.o m32vr4121_engine.o m32vr4121_icache.o \
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m32vr4121_idecode.o m32vr4121_model.o m32vr4121_semantics.o \
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m32vr4121_support.o \
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$(SIM_NEW_COMMON_OBJS) \
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$(MIPS_EXTRA_OBJS) \
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interp.o \
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sim-main.o \
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sim-hload.o \
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sim-engine.o \
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sim-stop.o \
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sim-resume.o \
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sim-reason.o \
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callback.o syscall.o targ-map.o \
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vr4run.o
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HACK_GEN_SRCS = \
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itable.c \
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m16vr4111_icache.c m16vr4111_idecode.c m16vr4111_model.c \
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m16vr4111_run.c m16vr4111_semantics.c m16vr4111_support.c \
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m16vr4121_icache.c m16vr4121_idecode.c m16vr4121_model.c \
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m16vr4121_run.c m16vr4121_semantics.c m16vr4121_support.c \
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m32mipsIV_engine.c m32mipsIV_icache.c m32mipsIV_idecode.c \
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m32mipsIV_model.c m32mipsIV_semantics.c m32mipsIV_support.c \
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m32vr4100_engine.c m32vr4100_icache.c m32vr4100_idecode.c \
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m32vr4100_model.c m32vr4100_semantics.c m32vr4100_support.c \
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m32vr4111_engine.c m32vr4111_icache.c m32vr4111_idecode.c \
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m32vr4111_model.c m32vr4111_semantics.c m32vr4111_support.c \
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m32vr4320_engine.c m32vr4320_icache.c m32vr4320_idecode.c \
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m32vr4320_model.c m32vr4320_semantics.c m32vr4320_support.c \
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m32vr4121_engine.c m32vr4121_icache.c m32vr4121_idecode.c \
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m32vr4121_model.c m32vr4121_semantics.c m32vr4121_support.c
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$(HACK_GEN_SRCS): tmp-hack
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libhack.a: $(HACK_OBJS)
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rm -f libhack.a
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$(AR) $(AR_FLAGS) libhack.a $(HACK_OBJS)
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$(RANLIB) libhack.a
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hack: tmp-hack $(SIM_RUN_OBJS) libhack.a
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$(CC) $(ALL_CFLAGS) -o hack$(EXEEXT) \
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$(SIM_RUN_OBJS) libhack.a $(EXTRA_LIBS)
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tmp-hack: tmp-m16-hack tmp-m32-hack tmp-itable-hack tmp-run-hack targ-vals.h
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tmp-m32-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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for t in m32mipsIV:mipsIV m32vr4100:vr4100 m32vr4111:vr4100 m32vr4320:vr4320 m32vr4121:vr4121 ; \
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do \
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p=`echo $${t} | sed -e 's/:.*//'` ; \
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m=`echo $${t} | sed -e 's/.*://'` ; \
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-N 0 \
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-M $${m} -F 32,64,f \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 32 \
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-H 31 \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-P $${p}_ \
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-x \
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-n $${p}_icache.h -hc tmp-icache.h \
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-n $${p}_icache.c -c tmp-icache.c \
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-n $${p}_semantics.h -hs tmp-semantics.h \
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-n $${p}_semantics.c -s tmp-semantics.c \
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-n $${p}_idecode.h -hd tmp-idecode.h \
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-n $${p}_idecode.c -d tmp-idecode.c \
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-n $${p}_model.h -hm tmp-model.h \
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-n $${p}_model.c -m tmp-model.c \
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-n $${p}_support.h -hf tmp-support.h \
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-n $${p}_support.c -f tmp-support.c \
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-n $${p}_engine.h -he tmp-engine.h \
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-n $${p}_engine.c -e tmp-engine.c \
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; \
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$(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
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$(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
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$(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
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$(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
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$(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
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$(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
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$(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
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$(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
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$(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
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$(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
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$(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
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$(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
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done
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touch tmp-m32-hack
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tmp-m16-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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for t in m16vr4111:vr4100 m16vr4121:vr4121 ; \
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do \
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p=`echo $${t} | sed -e 's/:.*//'` ; \
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m=`echo $${t} | sed -e 's/.*://'` ; \
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-N 0 \
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-M $${m},mips16 -F 16 \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 16 \
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-H 15 \
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-i $(IGEN_INSN) \
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-o $(M16_DC) \
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-P $${p}_ \
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-x \
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-n $${p}_icache.h -hc tmp-icache.h \
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-n $${p}_icache.c -c tmp-icache.c \
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-n $${p}_semantics.h -hs tmp-semantics.h \
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-n $${p}_semantics.c -s tmp-semantics.c \
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-n $${p}_idecode.h -hd tmp-idecode.h \
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-n $${p}_idecode.c -d tmp-idecode.c \
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-n $${p}_model.h -hm tmp-model.h \
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-n $${p}_model.c -m tmp-model.c \
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-n $${p}_support.h -hf tmp-support.h \
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-n $${p}_support.c -f tmp-support.c \
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-n $${p}_engine.h -he tmp-engine.h \
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; \
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$(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
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$(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
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$(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
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$(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
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$(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
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$(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
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$(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
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$(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
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$(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
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$(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
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$(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
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done
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touch tmp-m16-hack
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tmp-itable-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-Wnowidth \
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-N 0 \
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-F 32,64,f -M vr4100,vr4320,mipsIV,vr4121 -F 16 -M mips16 \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-i $(IGEN_INSN) \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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#
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$(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(srcdir)/../../move-if-change tmp-itable.c itable.c
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touch tmp-itable-hack
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tmp-run-hack: $(srcdir)/m16run.c
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for m in vr4111 vr4121 ; \
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do \
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sed < $(srcdir)/m16run.c > tmp-run \
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-e "s/^sim_/m16$${m}_/" \
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-e "s/m16_/m16$${m}_/" \
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-e "s/m32_/m32$${m}_/" ; \
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$(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
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done
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touch tmp-run-hack
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# end-sanitize-vr4xxx
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@ -169,9 +169,18 @@ case "${target}" in
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;;
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# end-sanitize-cygnus
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# start-sanitize-vr4xxx
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mips64vr4xxx*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mipsIV,vr4100,vr4121 -G gen-multi-sim=mipsIV"
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;;
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mips64vr4xxx*-*-*) sim_gen=HACK
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sim_igen_filter="32,64,f"
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;;
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# mips64vr4xxx*-*-*) sim_gen=IGEN
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# sim_igen_machine="-M mipsIV,vr4100,vr4121 -G gen-multi-sim=mipsIV"
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# ;;
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# mips64vr4xxx*-*-*) sim_gen=M16
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# sim_igen_machine="-M mipsIV,vr4100 -G gen-multi-sim=mipsV"
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# sim_m16_machine="-M vr4100"
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# sim_igen_filter="32,64,f"
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# sim_m16_filter="16"
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# ;;
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# end-sanitize-vr4xxx
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mips64vr41*) sim_gen=M16
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sim_igen_machine="-M vr4100"
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