Finish implementation of r5900 instructions.
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@ -1,3 +1,24 @@
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Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen (CxC1): Add tracing.
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start-sanitize-r5900
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Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* r5900.igen (StoreFP): Delete.
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(r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
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New functions.
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(rsqrt.s, sqrt.s): Implement.
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(r59cond): New function.
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(C.COND.S): Call r59cond in assembler line.
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(cvt.w.s, cvt.s.w): Implement.
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* mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
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instruction set.
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* sim-main.h: Define an enum of r5900 FCSR bit fields.
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end-sanitize-r5900
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start-sanitize-r5900
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Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
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@ -3718,19 +3718,38 @@
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{
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if (X)
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{
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/* control to */
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TRACE_ALU_INPUT1 (GPR[RT]);
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if (FS == 0)
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FCR0 = VL4_8(GPR[RT]);
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{
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FCR0 = VL4_8(GPR[RT]);
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TRACE_ALU_RESULT (FCR0);
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}
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else if (FS == 31)
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FCR31 = VL4_8(GPR[RT]);
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{
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FCR31 = VL4_8(GPR[RT]);
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SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
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TRACE_ALU_RESULT (FCR31);
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}
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else
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{
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TRACE_ALU_RESULT0 ();
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}
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/* else NOP */
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SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
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}
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else
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{ /* control from */
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if (FS == 0)
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GPR[RT] = SIGNEXTEND (FCR0, 32);
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{
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TRACE_ALU_INPUT1 (FCR0);
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GPR[RT] = SIGNEXTEND (FCR0, 32);
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}
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else if (FS == 31)
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GPR[RT] = SIGNEXTEND (FCR31, 32);
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{
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TRACE_ALU_INPUT1 (FCR31);
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GPR[RT] = SIGNEXTEND (FCR31, 32);
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}
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TRACE_ALU_RESULT (GPR[RT]);
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/* else NOP */
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}
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}
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@ -3746,9 +3765,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -3775,9 +3791,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -3806,9 +3819,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -3834,9 +3844,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -4711,9 +4718,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -188,6 +188,22 @@ convert (SD, CPU, cia, rm, op, from, to)
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/* start-sanitize-r5900 */
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/* Figure 10-5 FPU Control/Status Register.
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Note: some of these bits are different to what is found in a
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standard MIPS manual. */
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enum {
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R5900_FCSR_C = BIT (23), /* OK */
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R5900_FCSR_I = BIT (17),
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R5900_FCSR_D = BIT (16),
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R5900_FCSR_O = BIT (15),
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R5900_FCSR_U = BIT (14),
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R5900_FCSR_CAUSE = MASK (16,14),
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R5900_FCSR_SI = BIT (6),
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R5900_FCSR_SD = BIT (5),
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R5900_FCSR_SO = BIT (4),
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R5900_FCSR_SU = BIT (3),
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};
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typedef struct _sim_r5900_cpu {
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/* The R5900 has 32 x 128bit general purpose registers.
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