RISC-V: Fix disassemble for c.li, c.andi and c.addiw
ChangeLog 2017-05-03 Kito Cheng <kito.cheng@gmail.com> * riscv-dis.c (print_insn_args): Handle 'Co' operands.
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2017-05-03 Kito Cheng <kito.cheng@gmail.com>
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* riscv-dis.c (print_insn_args): Handle 'Co' operands.
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2017-05-01 Michael Clark <michaeljclark@mac.com>
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* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
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@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
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case 'i':
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print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
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break;
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case 'o':
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case 'j':
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print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
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break;
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