2006-09-08 Paul Brook <paul@codesourcery.com>
gas/ * config/tc-arm.c (insns): Allow ARM IT pseudo-insn on all cores. gas/testsuite/ * gas/arm/arm-it.s: New test. * gas/arm/arm-it.d: New test.
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2006-09-08 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (insns): Allow ARM IT pseudo-insn on all cores.
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2006-09-07 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (parse_operands): Mark operand as present.
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@ -14828,7 +14828,9 @@ static const struct asm_opcode insns[] =
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UT(cbnz, b900, 2, (RR, EXP), t_czb),
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UT(cbz, b100, 2, (RR, EXP), t_czb),
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/* ARM does not really have an IT instruction. */
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/* ARM does not really have an IT instruction, so always allow it. */
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#undef ARM_VARIANT
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#define ARM_VARIANT &arm_ext_v1
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TUE(it, 0, bf08, 1, (COND), it, t_it),
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TUE(itt, 0, bf0c, 1, (COND), it, t_it),
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TUE(ite, 0, bf04, 1, (COND), it, t_it),
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@ -1,3 +1,8 @@
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2006-09-08 Paul Brook <paul@codesourcery.com>
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* gas/arm/arm-it.s: New test.
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* gas/arm/arm-it.d: New test.
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2006-09-07 Paul Brook <paul@codesourcery.com>
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* gas/arm/neon-omit.s: Test three-argument variants.
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#name: ARM IT instruction
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#objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0
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0+004 <[^>]*> e1a0f00e ? mov pc, lr
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# Check that IT is accepted in ARM mode on older architectures
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.text
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.syntax unified
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.arch armv4
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label1:
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it eq
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moveq r0, #0
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mov pc, lr
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