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RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero. 

2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
	gas/
	* testsuite/gas/riscv/c-add-addi.d: New testcase.
	* testsuite/gas/riscv/c-add-addi.s: Likewise.
	opcodes/
	* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
	c.mv/c.li if rs1 is zero.

Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
This commit is contained in:
Jim Wilson 2020-02-19 14:51:07 -08:00
parent 741cb83912
commit fa16423949
5 changed files with 26 additions and 0 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/c-add-addi.d: New testcase.
* testsuite/gas/riscv/c-add-addi.s: Likewise.
2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25576

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gas/testsuite/gas/riscv/c-add-addi.d Normal file
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@ -0,0 +1,11 @@
#as:
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+0:[ ]+4605[ ]+li[ ]+a2,1
[ ]+2:[ ]+852e[ ]+mv[ ]+a0,a1

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gas/testsuite/gas/riscv/c-add-addi.s Normal file
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@ -0,0 +1,3 @@
.option rvc
addi a2, zero, 1
add a0, zero, a1

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
c.mv/c.li if rs1 is zero.
2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuABM with

2
opcodes/riscv-opc.c
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@ -269,12 +269,14 @@ const struct riscv_opcode riscv_opcodes[] =
{"addi", 0, INSN_CLASS_C, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
{"addi", 0, INSN_CLASS_C, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
{"addi", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
{"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
{"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
{"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
{"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
{"add", 0, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
{"add", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
{"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
{"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
{"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc
applied to an add instruction, for relaxation to use. */