txvu.h renamed to dvp.h
This commit is contained in:
Doug Evans
parent
1adee2cc07
commit
fa5dd27d09
@ -31,7 +31,7 @@ else
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lose_these_too="${tic80_files} ${lose_these_too}"
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fi
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sky_files="txvu.h"
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sky_files="dvp.h"
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if ( echo $* | grep keep\-sky > /dev/null ) ; then
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keep_these_too="${sky_files} ${keep_these_too}"
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@ -1,15 +1,7 @@
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start-sanitize-sky
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Tue Jan 27 14:01:16 1998 Doug Evans <devans@seba.cygnus.com>
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Wed Jan 28 09:52:31 1998 Doug Evans <devans@canuck.cygnus.com>
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* txvu.h (txvu_{opcode,operand}): New typedefs.
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(txvu_operand): Add opcode,operand,mods arguments consistently to
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each of the parse/insert/extract/print routines.
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Mon Jan 26 16:19:01 1998 Doug Evans <devans@seba.cygnus.com>
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* txvu.h (txvu_opcode): insert/extract/print take pointer to
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instruction rather than instruction itself. Result of insert is
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`void'. Add decls for dma, pke, gpuif support.
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* dvp.h: New file.
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end-sanitize-sky
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Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com>
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@ -33,12 +25,6 @@ Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com>
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(CGEN_{SYNTAX,FORMAT}): New types.
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(cgen_insn): Format and syntax separated from each other.
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start-sanitize-sky
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Mon Jan 5 13:33:21 1998 Doug Evans <devans@seba.cygnus.com>
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* txvu.h: New file
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end-sanitize-sky
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start-sanitize-d30v
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Tue Dec 16 15:15:52 1997 Michael Meissner <meissner@cygnus.com>
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@ -1,341 +0,0 @@
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/* Opcode table for the TXVU.
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Copyright 1998 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* Type to denote a TXVU instruction (at least a 32 bit unsigned int). */
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typedef unsigned int TXVU_INSN;
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/* Maximum number of operands and syntax chars an instruction can have. */
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#define TXVU_MAX_OPERANDS 16
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typedef struct txvu_opcode {
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char *mnemonic;
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/* The value stored is 128 + operand number.
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This allows ASCII chars to go here as well. */
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unsigned char syntax[TXVU_MAX_OPERANDS];
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TXVU_INSN mask, value; /* recognize insn if (op&mask)==value */
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int flags; /* various flag bits */
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/* Values for `flags'. */
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/* This insn is a conditional branch. */
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#define TXVU_OPCODE_COND_BRANCH 1
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/* These values are used to optimize assembly and disassembly. Each insn is
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on a list of related insns (same first letter for assembly, same insn code
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for disassembly). */
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/* FIXME: May wish to move this to separate table. */
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struct txvu_opcode *next_asm; /* Next instruction to try during assembly. */
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struct txvu_opcode *next_dis; /* Next instruction to try during disassembly. */
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/* Macros to create the hash values for the lists. */
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#define TXVU_HASH_UPPER_OPCODE(string) \
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(tolower ((string)[0]) >= 'a' && tolower ((string)[0]) <= 'z' \
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? tolower ((string)[0]) - 'a' : 26)
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#define TXVU_HASH_LOWER_OPCODE(string) \
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(tolower ((string)[0]) >= 'a' && tolower ((string)[0]) <= 'z' \
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? tolower ((string)[0]) - 'a' : 26)
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/* ??? The icode hashing is very simplistic.
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upper: bits 0x3c, can't use lower two bits because of bc field
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lower: upper 6 bits */
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#define TXVU_ICODE_HASH_SIZE 6 /* bits */
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#define TXVU_HASH_UPPER_ICODE(insn) \
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((insn) & 0x3c)
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#define TXVU_HASH_LOWER_ICODE(insn) \
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((((insn) & 0xfc) >> 26) & 0x3f)
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/* Macros to access `next_asm', `next_dis' so users needn't care about the
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underlying mechanism. */
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#define TXVU_OPCODE_NEXT_ASM(op) ((op)->next_asm)
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#define TXVU_OPCODE_NEXT_DIS(op) ((op)->next_dis)
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} txvu_opcode;
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/* The operand table. */
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typedef struct txvu_operand {
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/* The number of bits in the operand (may be unused for a modifier). */
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unsigned char bits;
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/* How far the operand is left shifted in the instruction, or
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the modifier's flag bit (may be unused for a modifier). */
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unsigned char shift;
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/* Various flag bits. */
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int flags;
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/* Values for `flags'. */
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/* This operand is a suffix to the opcode. */
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#define TXVU_OPERAND_SUFFIX 1
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define TXVU_OPERAND_RELATIVE_BRANCH 2
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/* This operand is an absolute branch address. The disassembler
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prints these symbolically if possible. */
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#define TXVU_OPERAND_ABSOLUTE_BRANCH 4
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/* This operand is an address. The disassembler
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prints these symbolically if possible. */
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#define TXVU_OPERAND_ADDRESS 8
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/* This operand takes signed values (default is unsigned).
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The default was chosen to be unsigned as most fields are unsigned
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(e.g. registers). */
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#define TXVU_OPERAND_SIGNED 0x10
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/* This operand takes signed values, but also accepts a full positive
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range of values. That is, if bits is 16, it takes any value from
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-0x8000 to 0xffff. */
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#define TXVU_OPERAND_SIGNOPT 0x20
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/* This operand should be regarded as a negative number for the
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purposes of overflow checking (i.e., the normal most negative
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number is disallowed and one more than the normal most positive
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number is allowed). This flag will only be set for a signed
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operand. */
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#define TXVU_OPERAND_NEGATIVE 0x40
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/* This operand doesn't really exist. The program uses these operands
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in special ways by creating insertion or extraction functions to have
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arbitrary processing performed during assembly/disassemble.
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Parse and print routines are ignored for FAKE operands. */
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#define TXVU_OPERAND_FAKE 0x80
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/*
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This operand can be either an asterisk or an expression...TODO */
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#define TXVU_OPERAND_DMA_COUNT 0x100
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/* Modifier values. */
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/* A dot is required before a suffix. e.g. .le */
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#define TXVU_MOD_DOT 0x1000
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/* Sum of all TXVU_MOD_XXX bits. */
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#define TXVU_MOD_BITS 0x7000
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/* Non-zero if the operand type is really a modifier. */
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#define TXVU_MOD_P(X) ((X) & TXVU_MOD_BITS)
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/* Parse function. This is used by the assembler.
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MODS is a list of modifiers preceding the operand in the syntax string.
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If the operand cannot be parsed an error message is stored in ERRMSG,
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otherwise ERRMSG is unchanged. */
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long (*parse) PARAMS ((const struct txvu_opcode *opcode,
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const struct txvu_operand *operand,
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int mods, char **str, const char **errmsg));
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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i |= (p & ((1 << o->bits) - 1)) << o->shift;
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(I is the instruction which we are filling in, O is a pointer to
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this structure, and OP is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will overwrite the appropriate
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bits of the instruction with the operand's value.
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MODS is a list of modifiers preceding the operand in the syntax string.
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If the ERRMSG argument is not NULL, then if the operand value is illegal,
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*ERRMSG will be set to a warning string (the operand will be inserted in
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any case). If the operand value is legal, *ERRMSG will be unchanged.
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OPCODE may be NULL, in which case the value isn't known. This happens
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when applying fixups. */
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void (*insert) PARAMS ((const struct txvu_opcode *opcode,
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const struct txvu_operand *operand,
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int mods, TXVU_INSN *insn,
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long value, const char **errmsg));
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & TXVU_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(I is the instruction, O is a pointer to this structure, and OP
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed.
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MODS is a list of modifiers preceding the operand in the syntax string.
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INSN is a pointer to one or two `TXVU_INSN's. The first element is
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the insn, the second is an immediate constant if present.
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FIXME: just thrown in here for now.
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*/
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long (*extract) PARAMS ((const struct txvu_opcode *opcode,
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const struct txvu_operand *operand,
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int mods, TXVU_INSN *insn, int *pinvalid));
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/* Print function. This is used by the disassembler. */
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void (*print) PARAMS ((const struct txvu_opcode *opcode,
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const struct txvu_operand *operand,
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int mods, TXVU_INSN *insn,
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disassemble_info *info, long value));
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} txvu_operand;
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/* Given an operand entry, return the table index. */
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#define TXVU_OPERAND_INDEX(op) ((op) - 128)
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/* VU support. */
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/* Positions, masks, and values of various fields used in multiple places
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(the opcode table, the disassembler, GAS). */
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#define TXVU_SHIFT_DEST 21
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#define TXVU_SHIFT_TREG 16
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#define TXVU_SHIFT_SREG 11
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#define TXVU_SHIFT_DREG 6
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#define TXVU_MASK_REG 31
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/* Bits for multiple dest choices. */
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#define TXVU_DEST_X 8
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#define TXVU_DEST_Y 4
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#define TXVU_DEST_Z 2
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#define TXVU_DEST_W 1
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/* Values for a single dest choice. */
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#define TXVU_SDEST_X 0
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#define TXVU_SDEST_Y 1
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#define TXVU_SDEST_Z 2
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#define TXVU_SDEST_W 3
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extern const txvu_operand txvu_operands[];
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extern /*const*/ txvu_opcode txvu_upper_opcodes[];
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extern /*const*/ txvu_opcode txvu_lower_opcodes[];
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extern const int txvu_upper_opcodes_count;
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extern const int txvu_lower_opcodes_count;
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const txvu_opcode *txvu_upper_opcode_lookup_asm PARAMS ((const char *));
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const txvu_opcode *txvu_lower_opcode_lookup_asm PARAMS ((const char *));
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const txvu_opcode *txvu_upper_opcode_lookup_dis PARAMS ((unsigned int));
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const txvu_opcode *txvu_lower_opcode_lookup_dis PARAMS ((unsigned int));
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/* PKE support. */
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/* PKE opcode flags.
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The usage here is a bit wasteful of bits, but there's enough bits
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and we can always make better usage later. */
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/* 2 word instruction */
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#define PKE_OPCODE_LEN2 1
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/* 5 word instruction */
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#define PKE_OPCODE_LEN5 2
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/* variable length instruction */
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#define PKE_OPCODE_LENVAR 4
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/* the mpg instruction */
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#define PKE_OPCODE_MPG 8
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/* the direct instruction */
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#define PKE_OPCODE_DIRECT 16
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/* the directhl instruction */
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#define PKE_OPCODE_DIRECTHL 32
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/* the unpack instruction */
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#define PKE_OPCODE_UNPACK 64
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/* Instruction flag bits. M,R are only applicable to `unpack'. */
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#define PKE_FLAG_I 1
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#define PKE_FLAG_M 2
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#define PKE_FLAG_R 4
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/* The "mode" operand of the "stmod" insn. */
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#define PKE_MODE_DIRECT 0
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#define PKE_MODE_ADD 1
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#define PKE_MODE_ADDROW 2
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/* Unpack types. */
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#define PKE_UNPACK_S_32 0
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#define PKE_UNPACK_S_16 1
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#define PKE_UNPACK_S_8 2
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#define PKE_UNPACK_V2_32 4
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#define PKE_UNPACK_V2_16 5
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#define PKE_UNPACK_V2_8 6
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#define PKE_UNPACK_V3_32 8
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#define PKE_UNPACK_V3_16 9
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#define PKE_UNPACK_V3_8 10
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#define PKE_UNPACK_V4_32 12
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#define PKE_UNPACK_V4_16 13
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#define PKE_UNPACK_V4_8 14
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#define PKE_UNPACK_V4_5 15
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extern const txvu_operand pke_operands[];
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extern /*const*/ txvu_opcode pke_opcodes[];
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extern const int pke_opcodes_count;
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const txvu_opcode *pke_opcode_lookup_asm PARAMS ((const char *));
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const txvu_opcode *pke_opcode_lookup_dis PARAMS ((unsigned int));
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/* Return non-zero if the just parsed pke insn has variable length. */
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int pke_varlen_p PARAMS ((void));
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/* Return length, in 32 bit words, of just parsed pke insn,
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or 0 if unknown. */
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int pke_len PARAMS ((void));
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/* DMA support. */
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/* DMA instruction flags. */
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#define DMA_FLAG_PCE0 1
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#define DMA_FLAG_PCE1 2
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#define DMA_FLAG_INT 4
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#define DMA_FLAG_SPR 8
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extern const txvu_operand dma_operands[];
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extern /*const*/ txvu_opcode dma_opcodes[];
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extern const int dma_opcodes_count;
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const txvu_opcode *dma_opcode_lookup_asm PARAMS ((const char *));
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const txvu_opcode *dma_opcode_lookup_dis PARAMS ((unsigned int));
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int txvu_dma_operand_count PARAMS((int));
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/* GPUIF support. */
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typedef enum {
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GPUIF_REG_PRIM = 0,
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GPUIF_REG_RGBAQ = 1,
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GPUIF_REG_ST = 2,
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GPUIF_REG_UV = 3,
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GPUIF_REG_XYZF2 = 4,
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GPUIF_REG_TEXCLUT_1 = 6,
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GPUIF_REG_TEXCLUT_2 = 7,
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GPUIF_REG_TEX0_1 = 8,
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GPUIF_REG_TEX0_2 = 9,
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GPUIF_REG_TEX1_1 = 10,
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GPUIF_REG_TEX1_2 = 11,
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GPUIF_REG_XYZF3 = 12,
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GPUIF_REG_PRMODE = 13,
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GPUIF_REG_A_D = 14,
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GPUIF_REG_NOP = 15
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} gpuif_reg;
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extern const txvu_operand gpuif_operands[];
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extern /*const*/ txvu_opcode gpuif_opcodes[];
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extern const int gpuif_opcodes_count;
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const txvu_opcode *gpuif_opcode_lookup_asm PARAMS ((const char *));
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const txvu_opcode *gpuif_opcode_lookup_dis PARAMS ((unsigned int));
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/* Utility fns in txvu-opc.c. */
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void txvu_opcode_init_tables PARAMS ((int));
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void txvu_opcode_init_parse PARAMS ((void));
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void txvu_opcode_init_print PARAMS ((void));
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