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AArch64: Add SVE DWARF registers 

The SVE DRAWF register names are missing from binutils, this may cause objdump
and readelf to ignore certain DRAWF output as the registers are unknown (most
notably CIEs).

This patch adds the registers in accordance to the "DWARF for ARM(r) 64-bit
Architecture (AARch64) with SVE support" documentation [1].

[1] https://developer.arm.com/docs/100985/latest/dwarf-for-the-arm-64-bit-architecture-aarch64-with-sve-support

binutils/ChangeLog:

	* dwarf.c (dwarf_regnames_aarch64): Add SVE registers.
	* testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test.
	* testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test.
This commit is contained in:
Tamar Christina 2019-05-21 11:03:45 +01:00
parent ce3ebcaae3
commit fab7c86ea4
4 changed files with 44 additions and 3 deletions
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6
binutils/ChangeLog
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@ -1,3 +1,9 @@
2019-05-21 Tamar Christina <tamar.christina@arm.com>
* dwarf.c (dwarf_regnames_aarch64): Add SVE registers.
* testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test.
* testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test.
2019-05-20 Faraz Shahbazker <fshahbazker@wavecomp.com>
PR 14798

10
binutils/dwarf.c
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@ -7175,13 +7175,17 @@ static const char *const dwarf_regnames_aarch64[] =
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",
NULL, "elr", NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, "vg", "ffr",
"p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
"p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15",
"z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
};
void

25
binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.d Normal file
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@ -0,0 +1,25 @@
#PROG: objcopy
#readelf: --debug-dump=frames
Contents of the .eh_frame section:
00000000 0000000000000018 00000000 CIE
Version: 1
Augmentation: "zR"
Code alignment factor: 4
Data alignment factor: -8
Return address column: 30
Augmentation data: 1b
DW_CFA_def_cfa: r31 \(sp\) ofs 0
DW_CFA_def_cfa_register: r96 \(z0\)
DW_CFA_def_cfa_offset: 5
DW_CFA_restore_extended: r96 \(z0\)
DW_CFA_nop
DW_CFA_nop
0000001c 0000000000000010 00000020 FDE cie=00000000 pc=0000000000000000..0000000000000000
DW_CFA_nop
DW_CFA_nop
DW_CFA_nop

6
binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.s Normal file
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@ -0,0 +1,6 @@
.arch armv8-a+sve
.cfi_startproc
.cfi_def_cfa_register 96
.cfi_adjust_cfa_offset 5
.cfi_restore 96
.cfi_endproc