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binutils-gdb
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Update testcase comment. 

addb.cgs addd.cgs addi.cgs andb.cgs andd.cgs andw.cgs
   ashub.cgs ashub_i.cgs ashud.cgs ashud_i.cgs ashuw.cgs
   ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs jump.cgs loadd.cgs
   loadw.cgs lshb.cgs lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs
   lshw_i.cgs movb.cgs movd.cgs movw.cgs movxb.cgs movxw.cgs
   movzb.cgs movzw.cgs mulb.cgs muluw.cgs mulw.cgs orb.cgs
   ord.cgs orw.cgs pop1.cgs pop2.cgs pop3.cgs popret1.cgs
   popret2.cgs popret3.cgs push1.cgs push2.cgs push3.cgs

Added BIT operation testcases:
  cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs tbitb.cgs tbit.cgs and tbitw.cgs
This commit is contained in:
M R Swami Reddy 2008-05-05 09:52:46 +00:00
parent e2b7ddeae3
commit fae9ec8dca
53 changed files with 315 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sim/testsuite/sim/cr16/addb.cgs
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# cr16 testcase for addb $dr,$sr
# cr16 testcase for addb $sr, reg
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/addd.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for addd $sr,$dr
# cr16 testcase for addd $sr, regp
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/addi.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for addi #$simm8, $dr
# cr16 testcase for addi $imm8, $dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/andb.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for and $dr,$sr
# cr16 testcase for and $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/andd.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for and $dr,$sr
# cr16 testcase for and $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/andw.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for and $dr,$sr
# cr16 testcase for and $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/ashub.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ashub $dr,$sr
# cr16 testcase for ashub $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/ashub_i.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ashub $dr,$sr
# cr16 testcase for ashub $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/ashud.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ashud $dr,$sr
# cr16 testcase for ashud $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/ashud_i.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ashud $dr,$sr
# cr16 testcase for ashud $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/ashuw.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ashuw $dr,$sr
# cr16 testcase for ashuw $sr,$dr
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/ashuw_i.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ashuw $dr,$sr
# cr16 testcase for ashuw $sr,$dr
# mach(): cr16
.include "testutils.inc"

35
sim/testsuite/sim/cr16/cbitb.cgs Normal file
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@ -0,0 +1,35 @@
# cr16 testcase for cbitb $bit_pos, ABS/REGP/REG
# mach: cr16
.include "testutils.inc"
start
.global cbitb
cbitb:
cbitb $0,_y
loadw _y, r1
cmpb $0xfe, r1
beq ok1
not_ok:
fail
ok1:
movd $_y, (r1,r0)
cbitb $1,0(r1,r0)
loadw _y, r1
cmpb $0xfc, r1
beq ok2
br not_ok
ok2:
movw $_y, r1
cbitb $2,0(r1)
loadw _y, r1
cmpb $0xf8, r1
beq ok3
br not_ok
ok3:
pass
_y: .word 0xff

35
sim/testsuite/sim/cr16/cbitw.cgs Normal file
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@ -0,0 +1,35 @@
# cr16 testcase for cbitw
# mach: cr16
.include "testutils.inc"
start
.global cbitw
cbitw:
cbitw $4,_y
loadw _y, r1
cmpb $0xef, r1
beq ok1
not_ok:
fail
ok1:
movd $_y, (r1,r0)
cbitw $5,0(r1,r0)
loadw _y, r1
cmpb $0xcf, r1
beq ok2
br not_ok
ok2:
movw $_y, r1
cbitw $6,0(r1)
loadw _y, r1
cmpb $0x8f, r1
beq ok3
br not_ok
ok3:
pass
_y: .word 0xff

2
sim/testsuite/sim/cr16/cmpi.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for cmpi $src2,#$simm16
# cr16 testcase for cmpi $imm16, reg
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/cmpw.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for cmp $src1,$src2
# cr16 testcase for cmp $imm, reg
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/jlt.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for jlt (repl)
# cr16 testcase for jlt (regp)
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/jump.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for jmp $sr
# cr16 testcase for jmp (regp)
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/loadd.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ldb $dr,@$sr
# cr16 testcase for loadd 0(regp),regp
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/loadw.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for ldb $dr,@$sr
# cr16 testcase for loadw 0(regp), (regp)
# mach(): cr16
.include "testutils.inc"

6
sim/testsuite/sim/cr16/lshb.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for sll $dr,$sr
# cr16 testcase for lshb count, reg
# mach(): cr16
.include "testutils.inc"
start
.global sll
sll:
.global lshb
lshb:
movb $6, r4
movb $1, r5
lshb r5, r4

2
sim/testsuite/sim/cr16/lshb_i.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for lshb_i $dr,#$uimm5
# cr16 testcase for lshb_i $uimm5, reg
# mach(): cr16
.include "testutils.inc"

6
sim/testsuite/sim/cr16/lshd.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for sll $dr,$sr
# cr16 testcase for lshd reg, regp
# mach(): cr16
.include "testutils.inc"
start
.global sll
sll:
.global lshd
lshd:
movd $0x12345678, (r4,r3)
movw $0x10, r5
lshd r5, (r4,r3)

2
sim/testsuite/sim/cr16/lshd_i.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for lshb_i $dr,#$uimm5
# cr16 testcase for lshb_i $uimm5, regp
# mach(): cr16
.include "testutils.inc"

6
sim/testsuite/sim/cr16/lshw.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for sll $dr,$sr
# cr16 testcase for lshw reg, reg
# mach(): cr16
.include "testutils.inc"
start
.global sll
sll:
.global lshw
lshw:
movw $0x1234, r4
movw $8, r5
lshw r5, r4

2
sim/testsuite/sim/cr16/lshw_i.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for lshb_i $dr,#$uimm5
# cr16 testcase for lshb_i $uimm4, reg
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/movb.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for movb $sr,$dr
# cr16 testcase for movb $imm, reg
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/movd.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for movd $sr,$dr
# cr16 testcase for movd $imm32, regp
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/movw.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for movw $sr,$dr
# cr16 testcase for movw $imm16, reg
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/movxb.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for movb $sr,$dr
# cr16 testcase for movb $imm4, reg
# mach(): cr16
.include "testutils.inc"

2
sim/testsuite/sim/cr16/movxw.cgs
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@ -1,4 +1,4 @@
# cr16 testcase for movw $sr,$dr
# cr16 testcase for movw reg, regp
# mach(): cr16
.include "testutils.inc"

6
sim/testsuite/sim/cr16/movzb.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for movb $sr,$dr
# cr16 testcase for movzb reg, reg
# mach(): cr16
.include "testutils.inc"
start
.global movb
movb:
.global movzb
movzb:
movw $0x120f, r4
movw $0x1200, r5

6
sim/testsuite/sim/cr16/movzw.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for movw $sr,$dr
# cr16 testcase for movzw reg, regp
# mach(): cr16
.include "testutils.inc"
start
.global movw
movw:
.global movzw
movzw:
movb $0xff, r4
movd $0x12345678,(r6, r5)

6
sim/testsuite/sim/cr16/mulb.cgs
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@ -7,11 +7,11 @@
.global mulb
mulb:
movw $0x2303,r4
movw $0x1207,r5
movw $0x1234,r4
movw $0x4567,r5
mulb r4, r5
cmpb $21, r5
cmpb $0xec, r5
beq ok1
not_ok:
fail

8
sim/testsuite/sim/cr16/muluw.cgs
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@ -1,16 +1,16 @@
# cr16 testcase for mul $dr,$sr
# cr16 testcase for muluw reg, regp
# mach(): cr16
.include "testutils.inc"
start
.global mul
mul:
.global muluw
muluw:
movw $0xfff,r4 # fix for 0xffff
movd $0xffffffff,(r6,r5)
muluw r4, (r6,r5)
test_h_grp "(r6,r5)", 0xfffff001
test_h_grp "(r6,r5)", 0xffef001
pass

6
sim/testsuite/sim/cr16/mulw.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for mul $dr,$sr
# cr16 testcase for mulw reg reg
# mach(): cr16
.include "testutils.inc"
start
.global mul
mul:
.global mulw
mulw:
movw $0x1234,r4
movw $0x1234,r5

6
sim/testsuite/sim/cr16/orb.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for or $sr,$dr
# cr16 testcase for orb $imm, reg
# mach(): cr16
.include "testutils.inc"
start
.global or
or:
.global orb
orb:
movb $3, r4
movb $6, r5

6
sim/testsuite/sim/cr16/ord.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for or $dr,$sr
# cr16 testcase for ord $imm32, regp
# mach(): cr16
.include "testutils.inc"
start
.global or
or:
.global ord
ord:
movd $0x33333333, (r4,r3)
movd $0x66666666, (r6,r5)

6
sim/testsuite/sim/cr16/orw.cgs
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@ -1,12 +1,12 @@
# cr16 testcase for or $dr,$sr
# cr16 testcase for orw reg, reg
# mach(): cr16
.include "testutils.inc"
start
.global or
or:
.global orw
orw:
movw $3, r4
movw $6, r5

2
sim/testsuite/sim/cr16/pop1.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global pop1
pop1:
movd $0x1000, (sp)
movw $0x2f50, r3

2
sim/testsuite/sim/cr16/pop2.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global pop2
pop2:
movd $0x1000, (sp)
movw $0x2f50, r3

2
sim/testsuite/sim/cr16/pop3.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global pop3
pop3:
movd $0x1006, (sp)
movd $0xabcd, (r3,r2)

2
sim/testsuite/sim/cr16/popret1.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global popret1
popret1:
movd $0x1000, (sp)
movw $0x2f50, r3

2
sim/testsuite/sim/cr16/popret2.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global popret2
popret2:
movd $0x1000, (sp)
movw $0x2f50, r3

2
sim/testsuite/sim/cr16/popret3.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global popret3
popret3:
movd $0x1006, (sp)
movd $ok, (ra)

2
sim/testsuite/sim/cr16/push1.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global push1
push1:
movd $0x100a, (sp)
movd $0xabcd, (ra)

2
sim/testsuite/sim/cr16/push2.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global push2
push2:
movd $0x1006, (sp)
movw $0x2f50, r5

2
sim/testsuite/sim/cr16/push3.cgs
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@ -4,6 +4,8 @@
.include "testutils.inc"
start
.global push1
push1:
movd $0x1006, (sp)
movd $0xabcd, (ra)

35
sim/testsuite/sim/cr16/sbitb.cgs Normal file
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@ -0,0 +1,35 @@
# cr16 testcase for sbitb $count, reg/regp/mem
# mach: cr16
.include "testutils.inc"
start
.global sbitb
sbitb:
sbitb $0,_y
loadw _y, r1
cmpb $0xf1, r1
beq ok1
not_ok:
fail
ok1:
movd $_y, (r1,r0)
sbitb $1,0(r1,r0)
loadw _y, r1
cmpb $0xf3, r1
beq ok2
br not_ok
ok2:
movw $_y, r1
sbitb $2,0(r1)
loadw _y, r1
cmpb $0xf7, r1
beq ok3
br not_ok
ok3:
pass
_y: .word 0xf0

35
sim/testsuite/sim/cr16/sbitw.cgs Normal file
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@ -0,0 +1,35 @@
# cr16 testcase for sbitw
# mach: cr16
.include "testutils.inc"
start
.global sbitw
sbitw:
sbitw $4,_y
loadw _y, r1
cmpb $0x1f, r1
beq ok1
not_ok:
fail
ok1:
movd $_y, (r1,r0)
sbitw $5,0(r1,r0)
loadw _y, r1
cmpb $0x3f, r1
beq ok2
br not_ok
ok2:
movw $_y, r1
sbitw $6,0(r1)
loadw _y, r1
cmpb $0x7f, r1
beq ok3
br not_ok
ok3:
pass
_y: .word 0x0f

31
sim/testsuite/sim/cr16/tbit.cgs Normal file
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@ -0,0 +1,31 @@
# cr16 testcase for tbit
# mach: cr16
.include "testutils.inc"
start
.global tbit
tbit:
movw $0, r1
lpr r1, psr
movw $0x7, r1
tbit $0, r1
spr psr, r1
cmpb $0x20, r1
beq ok1
not_ok:
fail
ok1:
movw $0, r1
lpr r1, psr
movw $0xa, r1
movw $0x1, r2
tbit r2,r1
spr psr, r1
cmpb $0x20, r1
beq ok2
br not_ok
ok2:
pass

33
sim/testsuite/sim/cr16/tbitb.cgs Normal file
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@ -0,0 +1,33 @@
# cr16 testcase for tbitb
# mach: cr16
.include "testutils.inc"
start
.global tbitb
tbitb:
movw $0, r1
lpr r1, psr
movw $_y, r1
tbitb $0, 0(r1)
spr psr, r1
cmpb $0x20, r1
beq ok1
not_ok:
fail
ok1:
movw $0, r1
lpr r1, psr
movd $_y, (r1,r0)
tbitb $1,0(r1,r0)
spr psr, r1
cmpb $0x20, r1
beq ok2
br not_ok
ok2:
pass
_y: .word 0xf7

33
sim/testsuite/sim/cr16/tbitw.cgs Normal file
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@ -0,0 +1,33 @@
# cr16 testcase for tbitw
# mach: cr16
.include "testutils.inc"
start
.global tbitw
tbitw:
movw $0, r1
lpr r1, psr
tbitw $0,_y
spr psr, r1
cmpb $0x20, r1
beq ok1
not_ok:
fail
ok1:
movw $0, r1
lpr r1, psr
movd $_y, (r1,r0)
tbitw $1,0(r1,r0)
loadw _y, r1
spr psr, r1
cmpb $0x20, r1
beq ok2
br not_ok
ok2:
pass
_y: .word 0xf7