[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag setting instructions from MTE which consists of the following instructions: - STG [<Xn|SP>, #<simm>] - STG [<Xn|SP>, #<simm>]! - STG [<Xn|SP>], #<simm> - STZG [<Xn|SP>, #<simm>] - STZG [<Xn|SP>, #<simm>]! - STZG [<Xn|SP>], #<simm> - ST2G [<Xn|SP>, #<simm>] - ST2G [<Xn|SP>, #<simm>]! - ST2G [<Xn|SP>], #<simm> - STZ2G [<Xn|SP>, #<simm>] - STZ2G [<Xn|SP>, #<simm>]! - STZ2G [<Xn|SP>], #<simm> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>] - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]! - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm> where <Xn|SP> : Is the 64-bit GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data for AARCH64_OPND_QLF_imm_tag. (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp for both offset and pre/post indexed versions. (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (fix_insn): Likewise. (warn_unpredictable_ldst): Exempt STGP. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g, stzg, stz2g and stgp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This commit is contained in:
Sudakshina Das
parent
b731bc3b1b
commit
fb3265b371
@ -1,3 +1,15 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_operands): Add switch case for
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AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
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(fix_insn): Likewise.
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(warn_unpredictable_ldst): Exempt STGP.
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* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
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stzg, stz2g and stgp.
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* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp,
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@ -6214,6 +6214,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_ADDR_SIMM9:
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case AARCH64_OPND_ADDR_SIMM9_2:
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case AARCH64_OPND_ADDR_SIMM11:
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case AARCH64_OPND_ADDR_SIMM13:
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| (!info->addr.preind && !info->addr.postind)
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@ -6773,6 +6775,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
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&& (opnds[0].reg.regno == opnds[2].addr.base_regno
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|| opnds[1].reg.regno == opnds[2].addr.base_regno)
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&& opnds[2].addr.base_regno != REG_SP
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/* Exempt STGP. */
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&& !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11)
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&& opnds[2].addr.writeback)
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as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
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/* Load operations must load different registers. */
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@ -7674,6 +7678,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
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case AARCH64_OPND_ADDR_SIMM9_2:
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case AARCH64_OPND_ADDR_SIMM10:
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case AARCH64_OPND_ADDR_UIMM12:
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case AARCH64_OPND_ADDR_SIMM11:
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case AARCH64_OPND_ADDR_SIMM13:
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/* Immediate offset in an address. */
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insn = get_aarch64_insn (buf);
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@ -55,3 +55,61 @@ Disassembly of section \.text:
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.*: badb037f cmpp x27, x27
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.*: bac003ff cmpp sp, x0
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.*: badf001f cmpp x0, sp
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.*: d920081f stg \[x0\]
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.*: d9200b7f stg \[x27\]
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.*: d93fb81f stg \[x0, #-80\]
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.*: d9200c1f stg \[x0, #0\]!
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.*: d920ac1f stg \[x0, #160\]!
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.*: d920041f stg \[x0\], #0
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.*: d93a641f stg \[x0\], #-1440
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.*: d92ffbff stg \[sp, #4080\]
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.*: d9300bff stg \[sp, #-4096\]
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.*: d92fffff stg \[sp, #4080\]!
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.*: d93007ff stg \[sp\], #-4096
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.*: d960081f stzg \[x0\]
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.*: d9600b7f stzg \[x27\]
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.*: d97fb81f stzg \[x0, #-80\]
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.*: d9600c1f stzg \[x0, #0\]!
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.*: d960ac1f stzg \[x0, #160\]!
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.*: d960041f stzg \[x0\], #0
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.*: d97a641f stzg \[x0\], #-1440
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.*: d96ffbff stzg \[sp, #4080\]
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.*: d9700bff stzg \[sp, #-4096\]
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.*: d96fffff stzg \[sp, #4080\]!
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.*: d97007ff stzg \[sp\], #-4096
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.*: d9a0081f st2g \[x0\]
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.*: d9a00b7f st2g \[x27\]
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.*: d9bfb81f st2g \[x0, #-80\]
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.*: d9a00c1f st2g \[x0, #0\]!
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.*: d9a0ac1f st2g \[x0, #160\]!
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.*: d9a0041f st2g \[x0\], #0
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.*: d9ba641f st2g \[x0\], #-1440
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.*: d9affbff st2g \[sp, #4080\]
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.*: d9b00bff st2g \[sp, #-4096\]
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.*: d9afffff st2g \[sp, #4080\]!
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.*: d9b007ff st2g \[sp\], #-4096
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.*: d9e0081f stz2g \[x0\]
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.*: d9e00b7f stz2g \[x27\]
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.*: d9ffb81f stz2g \[x0, #-80\]
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.*: d9e00c1f stz2g \[x0, #0\]!
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.*: d9e0ac1f stz2g \[x0, #160\]!
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.*: d9e0041f stz2g \[x0\], #0
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.*: d9fa641f stz2g \[x0\], #-1440
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.*: d9effbff stz2g \[sp, #4080\]
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.*: d9f00bff stz2g \[sp, #-4096\]
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.*: d9efffff stz2g \[sp, #4080\]!
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.*: d9f007ff stz2g \[sp\], #-4096
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.*: 69000000 stgp x0, x0, \[x0\]
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.*: 69006c00 stgp x0, x27, \[x0\]
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.*: 6900001b stgp x27, x0, \[x0\]
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.*: 69006c1b stgp x27, x27, \[x0\]
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.*: 69000360 stgp x0, x0, \[x27\]
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.*: 693d8000 stgp x0, x0, \[x0, #-80\]
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.*: 69800000 stgp x0, x0, \[x0, #0\]!
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.*: 69850000 stgp x0, x0, \[x0, #160\]!
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.*: 68800000 stgp x0, x0, \[x0\], #0
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.*: 68bb8000 stgp x0, x0, \[x0\], #-144
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.*: 691f801f stgp xzr, x0, \[x0, #1008\]
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.*: 69207c00 stgp x0, xzr, \[x0, #-1024\]
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.*: 699f83e0 stgp x0, x0, \[sp, #1008\]!
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.*: 68a003e0 stgp x0, x0, \[sp\], #-1024
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@ -16,6 +16,20 @@ func:
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\op x27, x27, #0, #0
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.endm
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.macro expand_stg op
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\op [x0, #0]
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\op [x27, #0]
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\op [x0, #-80]
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\op [x0, #0]!
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\op [x0, #160]!
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\op [x0], #0
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\op [x0], #-1440
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\op [sp, #4080]
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\op [sp, #-4096]
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\op [sp, #4080]!
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\op [sp], #-4096
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.endm
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# IRG
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expand_3_reg irg
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irg sp, x0
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@ -55,3 +69,23 @@ func:
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cmpp x27, x27
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cmpp sp, x0
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cmpp x0, sp
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expand_stg stg
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expand_stg stzg
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expand_stg st2g
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expand_stg stz2g
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stgp x0, x0, [x0, #0]
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stgp x0, x27, [x0, #0]
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stgp x27, x0, [x0, #0]
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stgp x27, x27, [x0, #0]
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stgp x0, x0, [x27, #0]
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stgp x0, x0, [x0, #-80]
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stgp x0, x0, [x0, #0]!
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stgp x0, x0, [x0, #160]!
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stgp x0, x0, [x0], #0
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stgp x0, x0, [x0], #-144
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stgp xzr, x0, [x0, #1008]
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stgp x0, xzr, [x0, #-1024]
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stgp x0, x0, [sp, #1008]!
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stgp x0, x0, [sp], #-1024
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@ -4,6 +4,12 @@
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4'
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[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 1 -- `stg \[x1,#15\]'
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[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `stzg \[x1,#-4097]!'
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[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `st2g \[x1],#4096'
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[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
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[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
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[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
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[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
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[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
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@ -20,3 +26,10 @@
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[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
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[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stg \[xzr,#0\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `st2g \[xzr,#0]!'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stzg \[xzr],#0'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stz2g \[xzr,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
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[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
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@ -8,6 +8,16 @@ func:
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addg x1, x2, #0x3f0, #0x10
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subg x1, x2, #0x3f0, -4
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# STG/STZG/ST2G : Fail imm
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stg [x1, #15]
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stzg [x1, #-4097]!
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st2g [x1], #4096
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# STGP : Fail imm
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stgp x1, x2, [x3, #1009]
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stgp x1, x2, [x3, #33]
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stgp x1, x2, [x3, #-1025]
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# Illegal SP/XZR registers
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irg xzr, x2, x3
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irg x1, xzr, x3
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@ -25,3 +35,10 @@ func:
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subps x1, x2, xzr
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cmpp xzr, x2
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cmpp x2, xzr
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stg [xzr, #0]
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st2g [xzr, #0]!
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stzg [xzr], #0
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stz2g [xzr, #0]
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stgp sp, x2, [x3]
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stgp x1, sp, [x3]
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stgp x0, x0, [xzr]
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@ -1,3 +1,9 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
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and AARCH64_OPND_ADDR_SIMM13.
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(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (aarch64_opnd): Add
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@ -286,7 +286,11 @@ enum aarch64_opnd
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the mnemonic name for LDUR/STUR instructions
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wherever there is no ambiguity. */
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AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
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AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
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16) immediate. */
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AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
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AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
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16) immediate. */
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AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
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AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
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AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
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@ -467,6 +471,10 @@ enum aarch64_opnd_qualifier
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AARCH64_OPND_QLF_P_Z,
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AARCH64_OPND_QLF_P_M,
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/* Used in scaled signed immediate that are scaled by a Tag granule
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like in stg, st2g, etc. */
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AARCH64_OPND_QLF_imm_tag,
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/* Constraint on value. */
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AARCH64_OPND_QLF_CR, /* CRn, CRm. */
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AARCH64_OPND_QLF_imm_0_7,
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@ -1,3 +1,18 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
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for AARCH64_OPND_QLF_imm_tag.
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(operand_general_constraint_met_p): Add case for
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AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
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(aarch64_print_operand): Likewise.
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* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
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(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
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for both offset and pre/post indexed versions.
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(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
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@ -201,390 +201,390 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 757: /* extr */
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value = 757; /* --> extr. */
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break;
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case 977: /* bic */
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case 976: /* and */
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value = 976; /* --> and. */
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case 987: /* bic */
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case 986: /* and */
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value = 986; /* --> and. */
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break;
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case 979: /* mov */
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case 978: /* orr */
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value = 978; /* --> orr. */
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case 989: /* mov */
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case 988: /* orr */
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value = 988; /* --> orr. */
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break;
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case 982: /* tst */
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case 981: /* ands */
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value = 981; /* --> ands. */
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case 992: /* tst */
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case 991: /* ands */
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value = 991; /* --> ands. */
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break;
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case 987: /* uxtw */
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case 986: /* mov */
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case 985: /* orr */
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value = 985; /* --> orr. */
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case 997: /* uxtw */
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case 996: /* mov */
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case 995: /* orr */
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value = 995; /* --> orr. */
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break;
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case 989: /* mvn */
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case 988: /* orn */
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value = 988; /* --> orn. */
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case 999: /* mvn */
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case 998: /* orn */
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value = 998; /* --> orn. */
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break;
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case 993: /* tst */
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case 992: /* ands */
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value = 992; /* --> ands. */
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case 1003: /* tst */
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case 1002: /* ands */
|
||||
value = 1002; /* --> ands. */
|
||||
break;
|
||||
case 1119: /* staddb */
|
||||
case 1023: /* ldaddb */
|
||||
value = 1023; /* --> ldaddb. */
|
||||
case 1129: /* staddb */
|
||||
case 1033: /* ldaddb */
|
||||
value = 1033; /* --> ldaddb. */
|
||||
break;
|
||||
case 1120: /* staddh */
|
||||
case 1024: /* ldaddh */
|
||||
value = 1024; /* --> ldaddh. */
|
||||
case 1130: /* staddh */
|
||||
case 1034: /* ldaddh */
|
||||
value = 1034; /* --> ldaddh. */
|
||||
break;
|
||||
case 1121: /* stadd */
|
||||
case 1025: /* ldadd */
|
||||
value = 1025; /* --> ldadd. */
|
||||
case 1131: /* stadd */
|
||||
case 1035: /* ldadd */
|
||||
value = 1035; /* --> ldadd. */
|
||||
break;
|
||||
case 1122: /* staddlb */
|
||||
case 1027: /* ldaddlb */
|
||||
value = 1027; /* --> ldaddlb. */
|
||||
case 1132: /* staddlb */
|
||||
case 1037: /* ldaddlb */
|
||||
value = 1037; /* --> ldaddlb. */
|
||||
break;
|
||||
case 1123: /* staddlh */
|
||||
case 1030: /* ldaddlh */
|
||||
value = 1030; /* --> ldaddlh. */
|
||||
case 1133: /* staddlh */
|
||||
case 1040: /* ldaddlh */
|
||||
value = 1040; /* --> ldaddlh. */
|
||||
break;
|
||||
case 1124: /* staddl */
|
||||
case 1033: /* ldaddl */
|
||||
value = 1033; /* --> ldaddl. */
|
||||
case 1134: /* staddl */
|
||||
case 1043: /* ldaddl */
|
||||
value = 1043; /* --> ldaddl. */
|
||||
break;
|
||||
case 1125: /* stclrb */
|
||||
case 1035: /* ldclrb */
|
||||
value = 1035; /* --> ldclrb. */
|
||||
case 1135: /* stclrb */
|
||||
case 1045: /* ldclrb */
|
||||
value = 1045; /* --> ldclrb. */
|
||||
break;
|
||||
case 1126: /* stclrh */
|
||||
case 1036: /* ldclrh */
|
||||
value = 1036; /* --> ldclrh. */
|
||||
case 1136: /* stclrh */
|
||||
case 1046: /* ldclrh */
|
||||
value = 1046; /* --> ldclrh. */
|
||||
break;
|
||||
case 1127: /* stclr */
|
||||
case 1037: /* ldclr */
|
||||
value = 1037; /* --> ldclr. */
|
||||
case 1137: /* stclr */
|
||||
case 1047: /* ldclr */
|
||||
value = 1047; /* --> ldclr. */
|
||||
break;
|
||||
case 1128: /* stclrlb */
|
||||
case 1039: /* ldclrlb */
|
||||
value = 1039; /* --> ldclrlb. */
|
||||
case 1138: /* stclrlb */
|
||||
case 1049: /* ldclrlb */
|
||||
value = 1049; /* --> ldclrlb. */
|
||||
break;
|
||||
case 1129: /* stclrlh */
|
||||
case 1042: /* ldclrlh */
|
||||
value = 1042; /* --> ldclrlh. */
|
||||
case 1139: /* stclrlh */
|
||||
case 1052: /* ldclrlh */
|
||||
value = 1052; /* --> ldclrlh. */
|
||||
break;
|
||||
case 1130: /* stclrl */
|
||||
case 1045: /* ldclrl */
|
||||
value = 1045; /* --> ldclrl. */
|
||||
case 1140: /* stclrl */
|
||||
case 1055: /* ldclrl */
|
||||
value = 1055; /* --> ldclrl. */
|
||||
break;
|
||||
case 1131: /* steorb */
|
||||
case 1047: /* ldeorb */
|
||||
value = 1047; /* --> ldeorb. */
|
||||
case 1141: /* steorb */
|
||||
case 1057: /* ldeorb */
|
||||
value = 1057; /* --> ldeorb. */
|
||||
break;
|
||||
case 1132: /* steorh */
|
||||
case 1048: /* ldeorh */
|
||||
value = 1048; /* --> ldeorh. */
|
||||
case 1142: /* steorh */
|
||||
case 1058: /* ldeorh */
|
||||
value = 1058; /* --> ldeorh. */
|
||||
break;
|
||||
case 1133: /* steor */
|
||||
case 1049: /* ldeor */
|
||||
value = 1049; /* --> ldeor. */
|
||||
case 1143: /* steor */
|
||||
case 1059: /* ldeor */
|
||||
value = 1059; /* --> ldeor. */
|
||||
break;
|
||||
case 1134: /* steorlb */
|
||||
case 1051: /* ldeorlb */
|
||||
value = 1051; /* --> ldeorlb. */
|
||||
case 1144: /* steorlb */
|
||||
case 1061: /* ldeorlb */
|
||||
value = 1061; /* --> ldeorlb. */
|
||||
break;
|
||||
case 1135: /* steorlh */
|
||||
case 1054: /* ldeorlh */
|
||||
value = 1054; /* --> ldeorlh. */
|
||||
case 1145: /* steorlh */
|
||||
case 1064: /* ldeorlh */
|
||||
value = 1064; /* --> ldeorlh. */
|
||||
break;
|
||||
case 1136: /* steorl */
|
||||
case 1057: /* ldeorl */
|
||||
value = 1057; /* --> ldeorl. */
|
||||
case 1146: /* steorl */
|
||||
case 1067: /* ldeorl */
|
||||
value = 1067; /* --> ldeorl. */
|
||||
break;
|
||||
case 1137: /* stsetb */
|
||||
case 1059: /* ldsetb */
|
||||
value = 1059; /* --> ldsetb. */
|
||||
case 1147: /* stsetb */
|
||||
case 1069: /* ldsetb */
|
||||
value = 1069; /* --> ldsetb. */
|
||||
break;
|
||||
case 1138: /* stseth */
|
||||
case 1060: /* ldseth */
|
||||
value = 1060; /* --> ldseth. */
|
||||
case 1148: /* stseth */
|
||||
case 1070: /* ldseth */
|
||||
value = 1070; /* --> ldseth. */
|
||||
break;
|
||||
case 1139: /* stset */
|
||||
case 1061: /* ldset */
|
||||
value = 1061; /* --> ldset. */
|
||||
case 1149: /* stset */
|
||||
case 1071: /* ldset */
|
||||
value = 1071; /* --> ldset. */
|
||||
break;
|
||||
case 1140: /* stsetlb */
|
||||
case 1063: /* ldsetlb */
|
||||
value = 1063; /* --> ldsetlb. */
|
||||
case 1150: /* stsetlb */
|
||||
case 1073: /* ldsetlb */
|
||||
value = 1073; /* --> ldsetlb. */
|
||||
break;
|
||||
case 1141: /* stsetlh */
|
||||
case 1066: /* ldsetlh */
|
||||
value = 1066; /* --> ldsetlh. */
|
||||
case 1151: /* stsetlh */
|
||||
case 1076: /* ldsetlh */
|
||||
value = 1076; /* --> ldsetlh. */
|
||||
break;
|
||||
case 1142: /* stsetl */
|
||||
case 1069: /* ldsetl */
|
||||
value = 1069; /* --> ldsetl. */
|
||||
case 1152: /* stsetl */
|
||||
case 1079: /* ldsetl */
|
||||
value = 1079; /* --> ldsetl. */
|
||||
break;
|
||||
case 1143: /* stsmaxb */
|
||||
case 1071: /* ldsmaxb */
|
||||
value = 1071; /* --> ldsmaxb. */
|
||||
case 1153: /* stsmaxb */
|
||||
case 1081: /* ldsmaxb */
|
||||
value = 1081; /* --> ldsmaxb. */
|
||||
break;
|
||||
case 1144: /* stsmaxh */
|
||||
case 1072: /* ldsmaxh */
|
||||
value = 1072; /* --> ldsmaxh. */
|
||||
case 1154: /* stsmaxh */
|
||||
case 1082: /* ldsmaxh */
|
||||
value = 1082; /* --> ldsmaxh. */
|
||||
break;
|
||||
case 1145: /* stsmax */
|
||||
case 1073: /* ldsmax */
|
||||
value = 1073; /* --> ldsmax. */
|
||||
case 1155: /* stsmax */
|
||||
case 1083: /* ldsmax */
|
||||
value = 1083; /* --> ldsmax. */
|
||||
break;
|
||||
case 1146: /* stsmaxlb */
|
||||
case 1075: /* ldsmaxlb */
|
||||
value = 1075; /* --> ldsmaxlb. */
|
||||
case 1156: /* stsmaxlb */
|
||||
case 1085: /* ldsmaxlb */
|
||||
value = 1085; /* --> ldsmaxlb. */
|
||||
break;
|
||||
case 1147: /* stsmaxlh */
|
||||
case 1078: /* ldsmaxlh */
|
||||
value = 1078; /* --> ldsmaxlh. */
|
||||
case 1157: /* stsmaxlh */
|
||||
case 1088: /* ldsmaxlh */
|
||||
value = 1088; /* --> ldsmaxlh. */
|
||||
break;
|
||||
case 1148: /* stsmaxl */
|
||||
case 1081: /* ldsmaxl */
|
||||
value = 1081; /* --> ldsmaxl. */
|
||||
case 1158: /* stsmaxl */
|
||||
case 1091: /* ldsmaxl */
|
||||
value = 1091; /* --> ldsmaxl. */
|
||||
break;
|
||||
case 1149: /* stsminb */
|
||||
case 1083: /* ldsminb */
|
||||
value = 1083; /* --> ldsminb. */
|
||||
case 1159: /* stsminb */
|
||||
case 1093: /* ldsminb */
|
||||
value = 1093; /* --> ldsminb. */
|
||||
break;
|
||||
case 1150: /* stsminh */
|
||||
case 1084: /* ldsminh */
|
||||
value = 1084; /* --> ldsminh. */
|
||||
case 1160: /* stsminh */
|
||||
case 1094: /* ldsminh */
|
||||
value = 1094; /* --> ldsminh. */
|
||||
break;
|
||||
case 1151: /* stsmin */
|
||||
case 1085: /* ldsmin */
|
||||
value = 1085; /* --> ldsmin. */
|
||||
case 1161: /* stsmin */
|
||||
case 1095: /* ldsmin */
|
||||
value = 1095; /* --> ldsmin. */
|
||||
break;
|
||||
case 1152: /* stsminlb */
|
||||
case 1087: /* ldsminlb */
|
||||
value = 1087; /* --> ldsminlb. */
|
||||
case 1162: /* stsminlb */
|
||||
case 1097: /* ldsminlb */
|
||||
value = 1097; /* --> ldsminlb. */
|
||||
break;
|
||||
case 1153: /* stsminlh */
|
||||
case 1090: /* ldsminlh */
|
||||
value = 1090; /* --> ldsminlh. */
|
||||
case 1163: /* stsminlh */
|
||||
case 1100: /* ldsminlh */
|
||||
value = 1100; /* --> ldsminlh. */
|
||||
break;
|
||||
case 1154: /* stsminl */
|
||||
case 1093: /* ldsminl */
|
||||
value = 1093; /* --> ldsminl. */
|
||||
case 1164: /* stsminl */
|
||||
case 1103: /* ldsminl */
|
||||
value = 1103; /* --> ldsminl. */
|
||||
break;
|
||||
case 1155: /* stumaxb */
|
||||
case 1095: /* ldumaxb */
|
||||
value = 1095; /* --> ldumaxb. */
|
||||
case 1165: /* stumaxb */
|
||||
case 1105: /* ldumaxb */
|
||||
value = 1105; /* --> ldumaxb. */
|
||||
break;
|
||||
case 1156: /* stumaxh */
|
||||
case 1096: /* ldumaxh */
|
||||
value = 1096; /* --> ldumaxh. */
|
||||
case 1166: /* stumaxh */
|
||||
case 1106: /* ldumaxh */
|
||||
value = 1106; /* --> ldumaxh. */
|
||||
break;
|
||||
case 1157: /* stumax */
|
||||
case 1097: /* ldumax */
|
||||
value = 1097; /* --> ldumax. */
|
||||
case 1167: /* stumax */
|
||||
case 1107: /* ldumax */
|
||||
value = 1107; /* --> ldumax. */
|
||||
break;
|
||||
case 1158: /* stumaxlb */
|
||||
case 1099: /* ldumaxlb */
|
||||
value = 1099; /* --> ldumaxlb. */
|
||||
case 1168: /* stumaxlb */
|
||||
case 1109: /* ldumaxlb */
|
||||
value = 1109; /* --> ldumaxlb. */
|
||||
break;
|
||||
case 1159: /* stumaxlh */
|
||||
case 1102: /* ldumaxlh */
|
||||
value = 1102; /* --> ldumaxlh. */
|
||||
case 1169: /* stumaxlh */
|
||||
case 1112: /* ldumaxlh */
|
||||
value = 1112; /* --> ldumaxlh. */
|
||||
break;
|
||||
case 1160: /* stumaxl */
|
||||
case 1105: /* ldumaxl */
|
||||
value = 1105; /* --> ldumaxl. */
|
||||
case 1170: /* stumaxl */
|
||||
case 1115: /* ldumaxl */
|
||||
value = 1115; /* --> ldumaxl. */
|
||||
break;
|
||||
case 1161: /* stuminb */
|
||||
case 1107: /* lduminb */
|
||||
value = 1107; /* --> lduminb. */
|
||||
case 1171: /* stuminb */
|
||||
case 1117: /* lduminb */
|
||||
value = 1117; /* --> lduminb. */
|
||||
break;
|
||||
case 1162: /* stuminh */
|
||||
case 1108: /* lduminh */
|
||||
value = 1108; /* --> lduminh. */
|
||||
case 1172: /* stuminh */
|
||||
case 1118: /* lduminh */
|
||||
value = 1118; /* --> lduminh. */
|
||||
break;
|
||||
case 1163: /* stumin */
|
||||
case 1109: /* ldumin */
|
||||
value = 1109; /* --> ldumin. */
|
||||
case 1173: /* stumin */
|
||||
case 1119: /* ldumin */
|
||||
value = 1119; /* --> ldumin. */
|
||||
break;
|
||||
case 1164: /* stuminlb */
|
||||
case 1111: /* lduminlb */
|
||||
value = 1111; /* --> lduminlb. */
|
||||
case 1174: /* stuminlb */
|
||||
case 1121: /* lduminlb */
|
||||
value = 1121; /* --> lduminlb. */
|
||||
break;
|
||||
case 1165: /* stuminlh */
|
||||
case 1114: /* lduminlh */
|
||||
value = 1114; /* --> lduminlh. */
|
||||
case 1175: /* stuminlh */
|
||||
case 1124: /* lduminlh */
|
||||
value = 1124; /* --> lduminlh. */
|
||||
break;
|
||||
case 1166: /* stuminl */
|
||||
case 1117: /* lduminl */
|
||||
value = 1117; /* --> lduminl. */
|
||||
case 1176: /* stuminl */
|
||||
case 1127: /* lduminl */
|
||||
value = 1127; /* --> lduminl. */
|
||||
break;
|
||||
case 1168: /* mov */
|
||||
case 1167: /* movn */
|
||||
value = 1167; /* --> movn. */
|
||||
case 1178: /* mov */
|
||||
case 1177: /* movn */
|
||||
value = 1177; /* --> movn. */
|
||||
break;
|
||||
case 1170: /* mov */
|
||||
case 1169: /* movz */
|
||||
value = 1169; /* --> movz. */
|
||||
case 1180: /* mov */
|
||||
case 1179: /* movz */
|
||||
value = 1179; /* --> movz. */
|
||||
break;
|
||||
case 1216: /* autibsp */
|
||||
case 1215: /* autibz */
|
||||
case 1214: /* autiasp */
|
||||
case 1213: /* autiaz */
|
||||
case 1212: /* pacibsp */
|
||||
case 1211: /* pacibz */
|
||||
case 1210: /* paciasp */
|
||||
case 1209: /* paciaz */
|
||||
case 1190: /* psb */
|
||||
case 1189: /* esb */
|
||||
case 1188: /* autib1716 */
|
||||
case 1187: /* autia1716 */
|
||||
case 1186: /* pacib1716 */
|
||||
case 1185: /* pacia1716 */
|
||||
case 1184: /* xpaclri */
|
||||
case 1183: /* sevl */
|
||||
case 1182: /* sev */
|
||||
case 1181: /* wfi */
|
||||
case 1180: /* wfe */
|
||||
case 1179: /* yield */
|
||||
case 1178: /* bti */
|
||||
case 1177: /* csdb */
|
||||
case 1176: /* nop */
|
||||
case 1175: /* hint */
|
||||
value = 1175; /* --> hint. */
|
||||
case 1226: /* autibsp */
|
||||
case 1225: /* autibz */
|
||||
case 1224: /* autiasp */
|
||||
case 1223: /* autiaz */
|
||||
case 1222: /* pacibsp */
|
||||
case 1221: /* pacibz */
|
||||
case 1220: /* paciasp */
|
||||
case 1219: /* paciaz */
|
||||
case 1200: /* psb */
|
||||
case 1199: /* esb */
|
||||
case 1198: /* autib1716 */
|
||||
case 1197: /* autia1716 */
|
||||
case 1196: /* pacib1716 */
|
||||
case 1195: /* pacia1716 */
|
||||
case 1194: /* xpaclri */
|
||||
case 1193: /* sevl */
|
||||
case 1192: /* sev */
|
||||
case 1191: /* wfi */
|
||||
case 1190: /* wfe */
|
||||
case 1189: /* yield */
|
||||
case 1188: /* bti */
|
||||
case 1187: /* csdb */
|
||||
case 1186: /* nop */
|
||||
case 1185: /* hint */
|
||||
value = 1185; /* --> hint. */
|
||||
break;
|
||||
case 1194: /* pssbb */
|
||||
case 1193: /* ssbb */
|
||||
case 1192: /* dsb */
|
||||
value = 1192; /* --> dsb. */
|
||||
case 1204: /* pssbb */
|
||||
case 1203: /* ssbb */
|
||||
case 1202: /* dsb */
|
||||
value = 1202; /* --> dsb. */
|
||||
break;
|
||||
case 1205: /* cpp */
|
||||
case 1204: /* dvp */
|
||||
case 1203: /* cfp */
|
||||
case 1202: /* tlbi */
|
||||
case 1201: /* ic */
|
||||
case 1200: /* dc */
|
||||
case 1199: /* at */
|
||||
case 1198: /* sys */
|
||||
value = 1198; /* --> sys. */
|
||||
case 1215: /* cpp */
|
||||
case 1214: /* dvp */
|
||||
case 1213: /* cfp */
|
||||
case 1212: /* tlbi */
|
||||
case 1211: /* ic */
|
||||
case 1210: /* dc */
|
||||
case 1209: /* at */
|
||||
case 1208: /* sys */
|
||||
value = 1208; /* --> sys. */
|
||||
break;
|
||||
case 2014: /* bic */
|
||||
case 1264: /* and */
|
||||
value = 1264; /* --> and. */
|
||||
case 2024: /* bic */
|
||||
case 1274: /* and */
|
||||
value = 1274; /* --> and. */
|
||||
break;
|
||||
case 1257: /* mov */
|
||||
case 1276: /* and */
|
||||
value = 1276; /* --> and. */
|
||||
break;
|
||||
case 1261: /* movs */
|
||||
case 1277: /* ands */
|
||||
value = 1277; /* --> ands. */
|
||||
break;
|
||||
case 2025: /* cmple */
|
||||
case 1312: /* cmpge */
|
||||
value = 1312; /* --> cmpge. */
|
||||
break;
|
||||
case 2028: /* cmplt */
|
||||
case 1315: /* cmpgt */
|
||||
value = 1315; /* --> cmpgt. */
|
||||
break;
|
||||
case 2026: /* cmplo */
|
||||
case 1317: /* cmphi */
|
||||
value = 1317; /* --> cmphi. */
|
||||
break;
|
||||
case 2027: /* cmpls */
|
||||
case 1320: /* cmphs */
|
||||
value = 1320; /* --> cmphs. */
|
||||
break;
|
||||
case 1254: /* mov */
|
||||
case 1342: /* cpy */
|
||||
value = 1342; /* --> cpy. */
|
||||
break;
|
||||
case 1256: /* mov */
|
||||
case 1343: /* cpy */
|
||||
value = 1343; /* --> cpy. */
|
||||
break;
|
||||
case 2035: /* fmov */
|
||||
case 1259: /* mov */
|
||||
case 1344: /* cpy */
|
||||
value = 1344; /* --> cpy. */
|
||||
break;
|
||||
case 1249: /* mov */
|
||||
case 1356: /* dup */
|
||||
value = 1356; /* --> dup. */
|
||||
break;
|
||||
case 1251: /* mov */
|
||||
case 1248: /* mov */
|
||||
case 1357: /* dup */
|
||||
value = 1357; /* --> dup. */
|
||||
break;
|
||||
case 2034: /* fmov */
|
||||
case 1253: /* mov */
|
||||
case 1358: /* dup */
|
||||
value = 1358; /* --> dup. */
|
||||
break;
|
||||
case 1252: /* mov */
|
||||
case 1359: /* dupm */
|
||||
value = 1359; /* --> dupm. */
|
||||
break;
|
||||
case 2029: /* eon */
|
||||
case 1361: /* eor */
|
||||
value = 1361; /* --> eor. */
|
||||
break;
|
||||
case 1262: /* not */
|
||||
case 1363: /* eor */
|
||||
value = 1363; /* --> eor. */
|
||||
break;
|
||||
case 1263: /* nots */
|
||||
case 1364: /* eors */
|
||||
value = 1364; /* --> eors. */
|
||||
break;
|
||||
case 2030: /* facle */
|
||||
case 1369: /* facge */
|
||||
value = 1369; /* --> facge. */
|
||||
break;
|
||||
case 2031: /* faclt */
|
||||
case 1370: /* facgt */
|
||||
value = 1370; /* --> facgt. */
|
||||
break;
|
||||
case 2032: /* fcmle */
|
||||
case 1383: /* fcmge */
|
||||
value = 1383; /* --> fcmge. */
|
||||
break;
|
||||
case 2033: /* fcmlt */
|
||||
case 1385: /* fcmgt */
|
||||
value = 1385; /* --> fcmgt. */
|
||||
break;
|
||||
case 1246: /* fmov */
|
||||
case 1391: /* fcpy */
|
||||
value = 1391; /* --> fcpy. */
|
||||
break;
|
||||
case 1245: /* fmov */
|
||||
case 1414: /* fdup */
|
||||
value = 1414; /* --> fdup. */
|
||||
break;
|
||||
case 1247: /* mov */
|
||||
case 1266: /* and */
|
||||
value = 1266; /* --> and. */
|
||||
case 1745: /* orr */
|
||||
value = 1745; /* --> orr. */
|
||||
break;
|
||||
case 1251: /* movs */
|
||||
case 1267: /* ands */
|
||||
value = 1267; /* --> ands. */
|
||||
case 2036: /* orn */
|
||||
case 1746: /* orr */
|
||||
value = 1746; /* --> orr. */
|
||||
break;
|
||||
case 2015: /* cmple */
|
||||
case 1302: /* cmpge */
|
||||
value = 1302; /* --> cmpge. */
|
||||
case 1250: /* mov */
|
||||
case 1748: /* orr */
|
||||
value = 1748; /* --> orr. */
|
||||
break;
|
||||
case 2018: /* cmplt */
|
||||
case 1305: /* cmpgt */
|
||||
value = 1305; /* --> cmpgt. */
|
||||
case 1260: /* movs */
|
||||
case 1749: /* orrs */
|
||||
value = 1749; /* --> orrs. */
|
||||
break;
|
||||
case 2016: /* cmplo */
|
||||
case 1307: /* cmphi */
|
||||
value = 1307; /* --> cmphi. */
|
||||
case 1255: /* mov */
|
||||
case 1811: /* sel */
|
||||
value = 1811; /* --> sel. */
|
||||
break;
|
||||
case 2017: /* cmpls */
|
||||
case 1310: /* cmphs */
|
||||
value = 1310; /* --> cmphs. */
|
||||
break;
|
||||
case 1244: /* mov */
|
||||
case 1332: /* cpy */
|
||||
value = 1332; /* --> cpy. */
|
||||
break;
|
||||
case 1246: /* mov */
|
||||
case 1333: /* cpy */
|
||||
value = 1333; /* --> cpy. */
|
||||
break;
|
||||
case 2025: /* fmov */
|
||||
case 1249: /* mov */
|
||||
case 1334: /* cpy */
|
||||
value = 1334; /* --> cpy. */
|
||||
break;
|
||||
case 1239: /* mov */
|
||||
case 1346: /* dup */
|
||||
value = 1346; /* --> dup. */
|
||||
break;
|
||||
case 1241: /* mov */
|
||||
case 1238: /* mov */
|
||||
case 1347: /* dup */
|
||||
value = 1347; /* --> dup. */
|
||||
break;
|
||||
case 2024: /* fmov */
|
||||
case 1243: /* mov */
|
||||
case 1348: /* dup */
|
||||
value = 1348; /* --> dup. */
|
||||
break;
|
||||
case 1242: /* mov */
|
||||
case 1349: /* dupm */
|
||||
value = 1349; /* --> dupm. */
|
||||
break;
|
||||
case 2019: /* eon */
|
||||
case 1351: /* eor */
|
||||
value = 1351; /* --> eor. */
|
||||
break;
|
||||
case 1252: /* not */
|
||||
case 1353: /* eor */
|
||||
value = 1353; /* --> eor. */
|
||||
break;
|
||||
case 1253: /* nots */
|
||||
case 1354: /* eors */
|
||||
value = 1354; /* --> eors. */
|
||||
break;
|
||||
case 2020: /* facle */
|
||||
case 1359: /* facge */
|
||||
value = 1359; /* --> facge. */
|
||||
break;
|
||||
case 2021: /* faclt */
|
||||
case 1360: /* facgt */
|
||||
value = 1360; /* --> facgt. */
|
||||
break;
|
||||
case 2022: /* fcmle */
|
||||
case 1373: /* fcmge */
|
||||
value = 1373; /* --> fcmge. */
|
||||
break;
|
||||
case 2023: /* fcmlt */
|
||||
case 1375: /* fcmgt */
|
||||
value = 1375; /* --> fcmgt. */
|
||||
break;
|
||||
case 1236: /* fmov */
|
||||
case 1381: /* fcpy */
|
||||
value = 1381; /* --> fcpy. */
|
||||
break;
|
||||
case 1235: /* fmov */
|
||||
case 1404: /* fdup */
|
||||
value = 1404; /* --> fdup. */
|
||||
break;
|
||||
case 1237: /* mov */
|
||||
case 1735: /* orr */
|
||||
value = 1735; /* --> orr. */
|
||||
break;
|
||||
case 2026: /* orn */
|
||||
case 1736: /* orr */
|
||||
value = 1736; /* --> orr. */
|
||||
break;
|
||||
case 1240: /* mov */
|
||||
case 1738: /* orr */
|
||||
value = 1738; /* --> orr. */
|
||||
break;
|
||||
case 1250: /* movs */
|
||||
case 1739: /* orrs */
|
||||
value = 1739; /* --> orrs. */
|
||||
break;
|
||||
case 1245: /* mov */
|
||||
case 1801: /* sel */
|
||||
value = 1801; /* --> sel. */
|
||||
break;
|
||||
case 1248: /* mov */
|
||||
case 1802: /* sel */
|
||||
value = 1802; /* --> sel. */
|
||||
case 1258: /* mov */
|
||||
case 1812: /* sel */
|
||||
value = 1812; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
@ -627,8 +627,6 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 27:
|
||||
case 28:
|
||||
case 29:
|
||||
case 157:
|
||||
case 158:
|
||||
case 159:
|
||||
case 160:
|
||||
case 161:
|
||||
@ -637,8 +635,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 164:
|
||||
case 165:
|
||||
case 166:
|
||||
case 179:
|
||||
case 180:
|
||||
case 167:
|
||||
case 168:
|
||||
case 181:
|
||||
case 182:
|
||||
case 183:
|
||||
@ -646,8 +644,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 185:
|
||||
case 186:
|
||||
case 187:
|
||||
case 191:
|
||||
case 194:
|
||||
case 188:
|
||||
case 189:
|
||||
case 193:
|
||||
case 196:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 13:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
@ -659,7 +659,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 31:
|
||||
case 32:
|
||||
case 33:
|
||||
case 196:
|
||||
case 198:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 34:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@ -693,16 +693,16 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 79:
|
||||
case 80:
|
||||
case 81:
|
||||
case 154:
|
||||
case 156:
|
||||
case 171:
|
||||
case 172:
|
||||
case 158:
|
||||
case 173:
|
||||
case 174:
|
||||
case 175:
|
||||
case 176:
|
||||
case 177:
|
||||
case 178:
|
||||
case 179:
|
||||
case 180:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 42:
|
||||
case 43:
|
||||
@ -712,10 +712,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 46:
|
||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
|
||||
case 50:
|
||||
case 145:
|
||||
case 147:
|
||||
return aarch64_ins_fpimm (self, info, code, inst, errors);
|
||||
case 67:
|
||||
case 152:
|
||||
case 154:
|
||||
return aarch64_ins_limm (self, info, code, inst, errors);
|
||||
case 68:
|
||||
return aarch64_ins_aimm (self, info, code, inst, errors);
|
||||
@ -725,67 +725,67 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_fbits (self, info, code, inst, errors);
|
||||
case 72:
|
||||
case 73:
|
||||
case 150:
|
||||
case 152:
|
||||
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
|
||||
case 74:
|
||||
case 149:
|
||||
case 151:
|
||||
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
|
||||
case 75:
|
||||
case 76:
|
||||
return aarch64_ins_cond (self, info, code, inst, errors);
|
||||
case 82:
|
||||
case 89:
|
||||
case 91:
|
||||
return aarch64_ins_addr_simple (self, info, code, inst, errors);
|
||||
case 83:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
|
||||
case 84:
|
||||
case 85:
|
||||
case 86:
|
||||
case 88:
|
||||
case 90:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst, errors);
|
||||
case 87:
|
||||
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
|
||||
case 88:
|
||||
case 89:
|
||||
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
|
||||
case 90:
|
||||
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
||||
case 91:
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
||||
case 92:
|
||||
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
||||
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
||||
case 93:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
||||
case 94:
|
||||
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
||||
case 95:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
||||
case 96:
|
||||
case 97:
|
||||
case 98:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
||||
case 99:
|
||||
case 100:
|
||||
return aarch64_ins_barrier (self, info, code, inst, errors);
|
||||
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
||||
case 101:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 102:
|
||||
return aarch64_ins_barrier (self, info, code, inst, errors);
|
||||
case 103:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 104:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
case 105:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
case 106:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
case 107:
|
||||
case 108:
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 109:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
case 110:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 111:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
case 112:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
case 113:
|
||||
case 114:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 115:
|
||||
case 116:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 117:
|
||||
case 118:
|
||||
case 119:
|
||||
@ -797,57 +797,59 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 125:
|
||||
case 126:
|
||||
case 127:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 128:
|
||||
case 129:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 130:
|
||||
case 131:
|
||||
case 132:
|
||||
case 133:
|
||||
case 134:
|
||||
case 135:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 136:
|
||||
case 137:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 138:
|
||||
case 139:
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 140:
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
case 141:
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 142:
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
case 143:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
case 144:
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
case 145:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
case 146:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 147:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
|
||||
case 148:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 149:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
case 150:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
|
||||
case 151:
|
||||
return aarch64_ins_inv_limm (self, info, code, inst, errors);
|
||||
case 153:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
||||
return aarch64_ins_inv_limm (self, info, code, inst, errors);
|
||||
case 155:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
||||
case 157:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst, errors);
|
||||
case 167:
|
||||
case 168:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 169:
|
||||
case 170:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 171:
|
||||
case 172:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
|
||||
case 188:
|
||||
case 189:
|
||||
case 190:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||
case 191:
|
||||
case 192:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||
case 194:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 193:
|
||||
case 195:
|
||||
case 197:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
@ -690,7 +690,8 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
|
||||
insert_field (FLD_Rn, code, info->addr.base_regno, 0);
|
||||
/* simm (imm9 or imm7) */
|
||||
imm = info->addr.offset.imm;
|
||||
if (self->fields[0] == FLD_imm7)
|
||||
if (self->fields[0] == FLD_imm7
|
||||
|| info->qualifier == AARCH64_OPND_QLF_imm_tag)
|
||||
/* scaled immediate in ld/st pair instructions.. */
|
||||
imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
|
||||
insert_field (self->fields[0], code, imm, 0);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1067,7 +1067,8 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
/* simm (imm9 or imm7) */
|
||||
imm = extract_field (self->fields[0], code, 0);
|
||||
info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
|
||||
if (self->fields[0] == FLD_imm7)
|
||||
if (self->fields[0] == FLD_imm7
|
||||
|| info->qualifier == AARCH64_OPND_QLF_imm_tag)
|
||||
/* scaled immediate in ld/st pair instructions. */
|
||||
info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
|
||||
/* qualifier */
|
||||
|
||||
@ -112,7 +112,9 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 11-bit signed immediate (multiple of 16) offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 13-bit signed immediate (multiple of 16) offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
|
||||
@ -230,48 +232,48 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
static const unsigned op_enum_table [] =
|
||||
{
|
||||
0,
|
||||
880,
|
||||
881,
|
||||
882,
|
||||
885,
|
||||
886,
|
||||
887,
|
||||
888,
|
||||
889,
|
||||
883,
|
||||
884,
|
||||
890,
|
||||
893,
|
||||
894,
|
||||
895,
|
||||
896,
|
||||
897,
|
||||
891,
|
||||
913,
|
||||
914,
|
||||
915,
|
||||
918,
|
||||
919,
|
||||
920,
|
||||
892,
|
||||
898,
|
||||
899,
|
||||
921,
|
||||
922,
|
||||
916,
|
||||
917,
|
||||
923,
|
||||
926,
|
||||
927,
|
||||
928,
|
||||
929,
|
||||
930,
|
||||
924,
|
||||
972,
|
||||
973,
|
||||
974,
|
||||
975,
|
||||
925,
|
||||
931,
|
||||
932,
|
||||
982,
|
||||
983,
|
||||
984,
|
||||
985,
|
||||
12,
|
||||
636,
|
||||
637,
|
||||
1167,
|
||||
1169,
|
||||
1171,
|
||||
979,
|
||||
1170,
|
||||
1168,
|
||||
1177,
|
||||
1179,
|
||||
1181,
|
||||
989,
|
||||
1180,
|
||||
1178,
|
||||
318,
|
||||
624,
|
||||
635,
|
||||
634,
|
||||
977,
|
||||
987,
|
||||
631,
|
||||
628,
|
||||
620,
|
||||
@ -281,7 +283,7 @@ static const unsigned op_enum_table [] =
|
||||
630,
|
||||
632,
|
||||
633,
|
||||
987,
|
||||
997,
|
||||
664,
|
||||
667,
|
||||
670,
|
||||
@ -298,17 +300,17 @@ static const unsigned op_enum_table [] =
|
||||
391,
|
||||
413,
|
||||
415,
|
||||
1240,
|
||||
1245,
|
||||
1238,
|
||||
1237,
|
||||
1241,
|
||||
1248,
|
||||
1250,
|
||||
1251,
|
||||
1255,
|
||||
1248,
|
||||
1247,
|
||||
1253,
|
||||
1252,
|
||||
1251,
|
||||
1258,
|
||||
1260,
|
||||
1261,
|
||||
1257,
|
||||
1263,
|
||||
1262,
|
||||
131,
|
||||
};
|
||||
|
||||
|
||||
@ -721,6 +721,9 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
|
||||
{0, 0, 0, "z", OQK_OPD_VARIANT},
|
||||
{0, 0, 0, "m", OQK_OPD_VARIANT},
|
||||
|
||||
/* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
|
||||
{16, 0, 0, "tag", OQK_OPD_VARIANT},
|
||||
|
||||
/* Qualifiers constraining the value range.
|
||||
First 3 fields:
|
||||
Lower bound, higher bound, unused. */
|
||||
@ -1668,6 +1671,36 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_ADDR_SIMM11:
|
||||
/* Signed 11 bits immediate offset (multiple of 16). */
|
||||
if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
|
||||
{
|
||||
set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!value_aligned_p (opnd->addr.offset.imm, 16))
|
||||
{
|
||||
set_unaligned_error (mismatch_detail, idx, 16);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_ADDR_SIMM13:
|
||||
/* Signed 13 bits immediate offset (multiple of 16). */
|
||||
if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
|
||||
{
|
||||
set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!value_aligned_p (opnd->addr.offset.imm, 16))
|
||||
{
|
||||
set_unaligned_error (mismatch_detail, idx, 16);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SIMD_ADDR_POST:
|
||||
/* AdvSIMD load/store multiple structures, post-index. */
|
||||
assert (idx == 1);
|
||||
@ -3559,6 +3592,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_ADDR_SIMM9:
|
||||
case AARCH64_OPND_ADDR_SIMM9_2:
|
||||
case AARCH64_OPND_ADDR_SIMM10:
|
||||
case AARCH64_OPND_ADDR_SIMM11:
|
||||
case AARCH64_OPND_ADDR_SIMM13:
|
||||
case AARCH64_OPND_ADDR_OFFSET:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
|
||||
|
||||
@ -125,6 +125,12 @@
|
||||
QLF1(X), \
|
||||
}
|
||||
|
||||
/* e.g. STG [<Xn|SP>, #<imm9>]. */
|
||||
#define QL_LDST_AT \
|
||||
{ \
|
||||
QLF1(imm_tag), \
|
||||
}
|
||||
|
||||
/* e.g. RBIT <Wd>, <Wn>. */
|
||||
#define QL_I2SAME \
|
||||
{ \
|
||||
@ -1218,6 +1224,12 @@
|
||||
QLF3(X, X, S_S), \
|
||||
}
|
||||
|
||||
/* e.g. STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */
|
||||
#define QL_STGP \
|
||||
{ \
|
||||
QLF3(X, X, imm_tag), \
|
||||
}
|
||||
|
||||
/* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */
|
||||
#define QL_LDST_PAIR_R \
|
||||
{ \
|
||||
@ -3218,6 +3230,15 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
|
||||
CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
|
||||
CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
|
||||
/* Load/store Allocation Tag instructions. */
|
||||
MEMTAG_INSN ("stg", 0xd920081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
MEMTAG_INSN ("stzg", 0xd960081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
MEMTAG_INSN ("st2g", 0xd9a0081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
MEMTAG_INSN ("stz2g",0xd9e0081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
MEMTAG_INSN ("stg", 0xd920041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
MEMTAG_INSN ("stzg", 0xd960041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
MEMTAG_INSN ("st2g", 0xd9a0041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
MEMTAG_INSN ("stz2g",0xd9e0041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
|
||||
/* Load/store register (unsigned immediate). */
|
||||
CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
|
||||
CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
|
||||
@ -3314,12 +3335,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
{"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
|
||||
MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
|
||||
/* Load/store register pair (indexed). */
|
||||
CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
|
||||
CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
|
||||
CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
{"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
|
||||
MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
|
||||
/* Load register (literal). */
|
||||
CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q),
|
||||
CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0),
|
||||
@ -4628,8 +4651,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"an address with 9-bit negative or unaligned immediate offset") \
|
||||
Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\
|
||||
"an address with 10-bit scaled, signed immediate offset") \
|
||||
Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\
|
||||
"an address with 11-bit signed immediate (multiple of 16) offset")\
|
||||
Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
|
||||
"an address with scaled, unsigned immediate offset") \
|
||||
Y(ADDRESS, addr_simm, "ADDR_SIMM13", 0, F(FLD_imm9,FLD_index),\
|
||||
"an address with 13-bit signed immediate (multiple of 16) offset")\
|
||||
Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
|
||||
"an address with base register (no offset)") \
|
||||
Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\
|
||||
|
||||
Loading…
Reference in New Issue
Block a user