gdb/riscv: Add gdb to dwarf register number mapping

Provide a mapping between GDB's register numbers and DWARF's register
numbers.  This resolves some failures that I was seeing on
gdb.base/store.exp when running on an rv64imfdc target.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function.
	(riscv_gdbarch_init): Register new function with gdbarch.
	* riscv-tdep.h: New enum to define RISC-V DWARF register numbers.

gdb/ChangeLog

@@ -1,3 +1,9 @@
+2018-12-22  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function.
+	(riscv_gdbarch_init): Register new function with gdbarch.
+	* riscv-tdep.h: New enum to define RISC-V DWARF register numbers.
+
 2018-12-21  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* minsyms.c (mst_str): New.

gdb/riscv-tdep.c

@@ -2946,6 +2946,20 @@ riscv_setup_register_aliases (struct gdbarch *gdbarch,
     }
 }
 
+/* Implement the "dwarf2_reg_to_regnum" gdbarch method.  */
+
+static int
+riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+{
+  if (reg < RISCV_DWARF_REGNUM_X31)
+    return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
+
+  else if (reg < RISCV_DWARF_REGNUM_F31)
+    return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
+
+  return -1;
+}
+
 /* Initialize the current architecture based on INFO.  If possible,
    re-use an architecture from ARCHES, which is a list of
    architectures already created during this debugging session.
@@ -3133,6 +3147,9 @@ riscv_gdbarch_init (struct gdbarch_info info,
   /* Register architecture.  */
   riscv_add_reggroups (gdbarch);
 
+  /* Internal <-> external register number maps.  */
+  set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum);
+
   /* We reserve all possible register numbers for the known registers.
      This means the target description mechanism will add any target
      specific registers after this number.  This helps make debugging GDB

gdb/riscv-tdep.h

@@ -56,6 +56,15 @@ enum
   RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
 };
 
+/* RiscV DWARF register numbers.  */
+enum
+{
+  RISCV_DWARF_REGNUM_X0 = 0,
+  RISCV_DWARF_REGNUM_X31 = 31,
+  RISCV_DWARF_REGNUM_F0 = 32,
+  RISCV_DWARF_REGNUM_F31 = 63,
+};
+
 /* RISC-V specific per-architecture information.  */
 struct gdbarch_tdep
 {