gdb/riscv: Add gdb to dwarf register number mapping
Provide a mapping between GDB's register numbers and DWARF's register numbers. This resolves some failures that I was seeing on gdb.base/store.exp when running on an rv64imfdc target. gdb/ChangeLog: * riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function. (riscv_gdbarch_init): Register new function with gdbarch. * riscv-tdep.h: New enum to define RISC-V DWARF register numbers.
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@ -1,3 +1,9 @@
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2018-12-22 Andrew Burgess <andrew.burgess@embecosm.com>
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* riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function.
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(riscv_gdbarch_init): Register new function with gdbarch.
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* riscv-tdep.h: New enum to define RISC-V DWARF register numbers.
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2018-12-21 Simon Marchi <simon.marchi@ericsson.com>
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2018-12-21 Simon Marchi <simon.marchi@ericsson.com>
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* minsyms.c (mst_str): New.
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* minsyms.c (mst_str): New.
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@ -2946,6 +2946,20 @@ riscv_setup_register_aliases (struct gdbarch *gdbarch,
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}
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}
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}
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}
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/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
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static int
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riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
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{
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if (reg < RISCV_DWARF_REGNUM_X31)
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return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
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else if (reg < RISCV_DWARF_REGNUM_F31)
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return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
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return -1;
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}
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/* Initialize the current architecture based on INFO. If possible,
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/* Initialize the current architecture based on INFO. If possible,
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re-use an architecture from ARCHES, which is a list of
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re-use an architecture from ARCHES, which is a list of
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architectures already created during this debugging session.
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architectures already created during this debugging session.
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@ -3133,6 +3147,9 @@ riscv_gdbarch_init (struct gdbarch_info info,
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/* Register architecture. */
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/* Register architecture. */
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riscv_add_reggroups (gdbarch);
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riscv_add_reggroups (gdbarch);
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/* Internal <-> external register number maps. */
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set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum);
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/* We reserve all possible register numbers for the known registers.
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/* We reserve all possible register numbers for the known registers.
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This means the target description mechanism will add any target
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This means the target description mechanism will add any target
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specific registers after this number. This helps make debugging GDB
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specific registers after this number. This helps make debugging GDB
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@ -56,6 +56,15 @@ enum
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RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
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RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
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};
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};
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/* RiscV DWARF register numbers. */
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enum
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{
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RISCV_DWARF_REGNUM_X0 = 0,
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RISCV_DWARF_REGNUM_X31 = 31,
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RISCV_DWARF_REGNUM_F0 = 32,
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RISCV_DWARF_REGNUM_F31 = 63,
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};
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/* RISC-V specific per-architecture information. */
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/* RISC-V specific per-architecture information. */
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struct gdbarch_tdep
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struct gdbarch_tdep
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{
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{
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