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opcodes/ 

* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
	replacing NODS.

	gas/testsuite/
	* gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay
	slot scheduling of ALNV.PS.
	* gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* gas/testsuite/gas/mips/micromips-trap.d: Likewise.
	* gas/testsuite/gas/mips/micromips.d: Likewise.
	* gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
This commit is contained in:
Maciej W. Rozycki 2013-08-23 14:12:59 +00:00
parent 021f8a30f4
commit fb6f389526
8 changed files with 23 additions and 26 deletions
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9
gas/testsuite/ChangeLog
View File

@ -1,3 +1,12 @@
2013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
* gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay
slot scheduling of ALNV.PS.
* gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* gas/testsuite/gas/mips/micromips-trap.d: Likewise.
* gas/testsuite/gas/mips/micromips.d: Likewise.
* gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
PR binutils/15834

3
gas/testsuite/gas/mips/micromips-insn32.d
View File

@ -5106,10 +5106,9 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5441 0099 alnv\.ps \$f0,\$f1,\$f2,v0
[ 0-9a-f]+: 5441 07d9 alnv\.ps \$f0,\$f1,\$f2,ra
[ 0-9a-f]+: 57fe efd9 alnv\.ps \$f29,\$f30,\$f31,ra
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0000 0000 nop
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0000 0000 nop

3
gas/testsuite/gas/mips/micromips-noinsn32.d
View File

@ -5085,10 +5085,9 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5441 0099 alnv\.ps \$f0,\$f1,\$f2,v0
[ 0-9a-f]+: 5441 07d9 alnv\.ps \$f0,\$f1,\$f2,ra
[ 0-9a-f]+: 57fe efd9 alnv\.ps \$f29,\$f30,\$f31,ra
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0c00 nop

3
gas/testsuite/gas/mips/micromips-trap.d
View File

@ -5091,10 +5091,9 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5441 0099 alnv\.ps \$f0,\$f1,\$f2,v0
[ 0-9a-f]+: 5441 07d9 alnv\.ps \$f0,\$f1,\$f2,ra
[ 0-9a-f]+: 57fe efd9 alnv\.ps \$f29,\$f30,\$f31,ra
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0c00 nop

3
gas/testsuite/gas/mips/micromips.d
View File

@ -5163,10 +5163,9 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5441 0099 alnv\.ps \$f0,\$f1,\$f2,v0
[ 0-9a-f]+: 5441 07d9 alnv\.ps \$f0,\$f1,\$f2,ra
[ 0-9a-f]+: 57fe efd9 alnv\.ps \$f29,\$f30,\$f31,ra
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
[ 0-9a-f]+: 0c00 nop

19
gas/testsuite/gas/mips/micromips@alnv_ps-swap.d
View File

@ -6,37 +6,28 @@
# Check that a register dependency between ALNV.PS and the following
# branch prevents from branch swapping (microMIPS).
# Note that currently swapping of ALNV.PS in microMIPS code is disabled
# altogether.
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
([0-9a-f]+) <[^>]*> cfff b \1 <foo\+0x[0-9a-f]+>
([0-9a-f]+) <[^>]*> cfff b \1 <foo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 foo
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <foo\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
([0-9a-f]+) <[^>]*> 4023 fffe bltzal v1,\1 <foo\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
[0-9a-f]+ <[^>]*> 45c3 jalr v1
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
[0-9a-f]+ <[^>]*> 0083 0f3c jalr a0,v1
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
[0-9a-f]+ <[^>]*> 007f 0f3c jalr v1,ra
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
([0-9a-f]+) <[^>]*> cfff b \1 <foo\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 foo
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <foo\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
@ -48,10 +39,8 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
[0-9a-f]+ <[^>]*> 45c3 jalr v1
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
[0-9a-f]+ <[^>]*> 0083 0f3c jalr a0,v1
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
[0-9a-f]+ <[^>]*> 007f 0f3c jalr v1,ra
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
\.\.\.

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
replacing NODS.
2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
PR binutils/15834

4
opcodes/micromips-opc.c
View File

@ -309,9 +309,7 @@ const struct mips_opcode micromips_opcodes[] =
{"addu", "md,me,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 },
/* We have no flag to mark the read from "y", so we use NODS to disable
delay slot scheduling of ALNV.PS altogether. */
{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|NODS|FP_D, 0, I1, 0, 0 },
{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
{"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },
{"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 },
{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },