Fix handling of XScale LDRD and STRD instructions with post indexed addressing modes.
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@ -1,3 +1,8 @@
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2001-05-11 Nick Clifton <nickc@cambridge.redhat.com>
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* armemu.c (ARMul_Emulate32): Fix handling of XScale LDRD and STRD
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instructions with post indexed addressing modes.
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2001-05-08 Jens-Christian Lache <lache@tu-harburg.de>
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2001-05-08 Jens-Christian Lache <lache@tu-harburg.de>
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* armsupp.c (ARMul_FixCPSR): Check Mode not Bank in order to
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* armsupp.c (ARMul_FixCPSR): Check Mode not Bank in order to
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@ -619,7 +619,7 @@ check_PMUintr:
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/* XScale Load Consecutive insn. */
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/* XScale Load Consecutive insn. */
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ARMword temp = GetLS7RHS (state, instr);
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ARMword temp = GetLS7RHS (state, instr);
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ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
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ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
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ARMword addr = BIT (24) ? temp2 : temp;
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ARMword addr = BIT (24) ? temp2 : LHS;
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if (BIT (12))
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if (BIT (12))
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ARMul_UndefInstr (state, instr);
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ARMul_UndefInstr (state, instr);
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@ -628,14 +628,14 @@ check_PMUintr:
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ARMul_Abort (state, ARMul_DataAbortV);
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ARMul_Abort (state, ARMul_DataAbortV);
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else
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else
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{
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{
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int wb = BIT (24) && BIT (21);
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int wb = BIT (21) || (! BIT (24));
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state->Reg[BITS (12, 15)] =
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state->Reg[BITS (12, 15)] =
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ARMul_LoadWordN (state, addr);
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ARMul_LoadWordN (state, addr);
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state->Reg[BITS (12, 15) + 1] =
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state->Reg[BITS (12, 15) + 1] =
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ARMul_LoadWordN (state, addr + 4);
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ARMul_LoadWordN (state, addr + 4);
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if (wb)
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if (wb)
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LSBase = addr;
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LSBase = temp2;
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}
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}
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goto donext;
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goto donext;
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@ -645,7 +645,7 @@ check_PMUintr:
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/* XScale Store Consecutive insn. */
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/* XScale Store Consecutive insn. */
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ARMword temp = GetLS7RHS (state, instr);
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ARMword temp = GetLS7RHS (state, instr);
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ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
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ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
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ARMword addr = BIT (24) ? temp2 : temp;
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ARMword addr = BIT (24) ? temp2 : LHS;
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if (BIT (12))
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if (BIT (12))
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ARMul_UndefInstr (state, instr);
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ARMul_UndefInstr (state, instr);
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@ -659,8 +659,8 @@ check_PMUintr:
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ARMul_StoreWordN (state, addr + 4,
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ARMul_StoreWordN (state, addr + 4,
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state->Reg[BITS (12, 15) + 1]);
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state->Reg[BITS (12, 15) + 1]);
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if (BIT (21))
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if (BIT (21)|| ! BIT (24))
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LSBase = addr;
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LSBase = temp2;
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}
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}
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goto donext;
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goto donext;
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