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[binutils][aarch64] New sve_size_tsz_bhs iclass. 

Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
	iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass decode.
This commit is contained in:
Matthew Malcomson 2019-05-09 10:29:26 +01:00
parent 31e36ab341
commit fd1dc4a0c1
5 changed files with 30 additions and 0 deletions
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5
include/ChangeLog
View File

@ -1,3 +1,8 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.

1
include/opcode/aarch64.h
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@ -601,6 +601,7 @@ enum aarch64_insn_class
sve_size_013,
sve_shift_tsz_hsd,
sve_shift_tsz_bhsd,
sve_size_tsz_bhs,
testbranch,
cryptosm3,
cryptosm4,

7
opcodes/ChangeLog
View File

@ -1,3 +1,10 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass decode.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.

6
opcodes/aarch64-asm.c
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@ -1673,6 +1673,12 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
aarch64_get_variant (inst) + 1, 0);
break;
case sve_size_tsz_bhs:
insert_fields (&inst->value,
(1 << aarch64_get_variant (inst)),
0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
break;
case sve_size_013:
variant = aarch64_get_variant (inst);
if (variant == 2)

11
opcodes/aarch64-dis.c
View File

@ -2843,6 +2843,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
}
break;
case sve_size_tsz_bhs:
i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
while (i != 1)
{
if (i & 1)
return FALSE;
i >>= 1;
variant += 1;
}
break;
case sve_shift_tsz_hsd:
i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
if (i == 0)