x86: fix various non-LIG templates
Quite a few templates were marked LIG while really the insns aren't. Introduce descriptive shorthands once again, instead of continuing to use the less legible original forms.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
563c7eef61
commit
fd71a3756e
@ -1,3 +1,16 @@
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2018-11-06 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/evex-lig-2.s,
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testsuite/gas/i386/x86-64-evex-lig-2.s: Add extract and insert
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cases.
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* testsuite/gas/i386/evex-lig-2.d,
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testsuite/gas/i386/x86-64-evex-lig-2.d: Adjust expectations.
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* testsuite/gas/i386/vex-lig-2.s,
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testsuite/gas/i386/vex-lig-2.d,
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testsuite/gas/i386/x86-64-vex-lig-2.s,
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testsuite/gas/i386/x86-64-vex-lig-2.d: New.
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* testsuite/gas/i386/i386.exp: Run new tests.
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2018-11-06 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/pseudos.s,
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@ -15,4 +15,21 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 f1 fd 08 d6 21 vmovq %xmm4,\(%ecx\)
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+[a-f0-9]+: 62 f1 fe 08 7e 21 vmovq \(%ecx\),%xmm4
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+[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
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+[a-f0-9]+: 62 f3 7d 08 17 c0 00 vextractps \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 17 00 00 vextractps \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: 62 f3 7d 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 14 00 00 vpextrb \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: 62 f1 7d 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 15 00 00 vpextrw \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: 62 f3 7d 08 16 c0 00 vpextrd \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 16 00 00 vpextrd \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: 62 f3 7d 08 21 c0 00 vinsertps \$0x0,%xmm0,%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 21 00 00 vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 20 00 00 vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: 62 f1 7d 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: 62 f1 7d 08 c4 00 00 vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 22 00 00 vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
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#pass
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@ -12,3 +12,28 @@ _start:
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{evex} vmovq (%ecx),%xmm4
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{evex} vmovq %xmm4,%xmm6
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{evex} vextractps $0, %xmm0, %eax
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{evex} vextractps $0, %xmm0, (%eax)
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{evex} vpextrb $0, %xmm0, %eax
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{evex} vpextrb $0, %xmm0, (%eax)
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{evex} vpextrw $0, %xmm0, %eax
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{evex} {store} vpextrw $0, %xmm0, %eax
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{evex} vpextrw $0, %xmm0, (%eax)
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{evex} vpextrd $0, %xmm0, %eax
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{evex} vpextrd $0, %xmm0, (%eax)
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{evex} vinsertps $0, %xmm0, %xmm0, %xmm0
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{evex} vinsertps $0, (%eax), %xmm0, %xmm0
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{evex} vpinsrb $0, %eax, %xmm0, %xmm0
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{evex} vpinsrb $0, (%eax), %xmm0, %xmm0
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{evex} vpinsrw $0, %eax, %xmm0, %xmm0
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{evex} vpinsrw $0, (%eax), %xmm0, %xmm0
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{evex} vpinsrd $0, %eax, %xmm0, %xmm0
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{evex} vpinsrd $0, (%eax), %xmm0, %xmm0
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@ -216,6 +216,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "avx-gather-intel"
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run_dump_test "avx-wig"
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run_dump_test "avx2-wig"
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run_dump_test "vex-lig-2"
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run_dump_test "avx512f"
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run_dump_test "avx512f-intel"
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run_dump_test "avx512f-opts"
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@ -739,6 +740,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-avx-gather-intel"
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run_dump_test "x86-64-avx-wig"
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run_dump_test "x86-64-avx2-wig"
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run_dump_test "x86-64-vex-lig-2"
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run_dump_test "x86-64-avx512f"
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run_dump_test "x86-64-avx512f-intel"
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run_dump_test "x86-64-avx512f-opts"
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74
gas/testsuite/gas/i386/vex-lig-2.d
Normal file
74
gas/testsuite/gas/i386/vex-lig-2.d
Normal file
@ -0,0 +1,74 @@
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#as: -mavxscalar=256
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#objdump: -dw
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#name: i386 VEX non-LIG insns with -mavxscalar=256
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: c5 f9 6e c0 vmovd %eax,%xmm0
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+[a-f0-9]+: c5 f9 6e 00 vmovd \(%eax\),%xmm0
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+[a-f0-9]+: c4 e1 79 6e c0 vmovd %eax,%xmm0
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+[a-f0-9]+: c4 e1 79 6e 00 vmovd \(%eax\),%xmm0
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+[a-f0-9]+: c5 f9 7e c0 vmovd %xmm0,%eax
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+[a-f0-9]+: c5 f9 7e 00 vmovd %xmm0,\(%eax\)
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+[a-f0-9]+: c4 e1 79 7e c0 vmovd %xmm0,%eax
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+[a-f0-9]+: c4 e1 79 7e 00 vmovd %xmm0,\(%eax\)
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+[a-f0-9]+: c5 fa 7e c0 vmovq %xmm0,%xmm0
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+[a-f0-9]+: c5 fa 7e 00 vmovq \(%eax\),%xmm0
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+[a-f0-9]+: c4 e1 7a 7e c0 vmovq %xmm0,%xmm0
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+[a-f0-9]+: c4 e1 7a 7e 00 vmovq \(%eax\),%xmm0
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+[a-f0-9]+: c5 f9 d6 c0 vmovq %xmm0,%xmm0
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+[a-f0-9]+: c5 f9 d6 00 vmovq %xmm0,\(%eax\)
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+[a-f0-9]+: c4 e1 79 d6 c0 vmovq %xmm0,%xmm0
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+[a-f0-9]+: c4 e1 79 d6 00 vmovq %xmm0,\(%eax\)
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+[a-f0-9]+: c4 e3 79 17 c0 00 vextractps \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 79 17 00 00 vextractps \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: c4 e3 79 14 c0 00 vpextrb \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 79 14 00 00 vpextrb \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: c5 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e1 79 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 79 15 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 79 15 00 00 vpextrw \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: c4 e3 79 16 c0 00 vpextrd \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 79 16 00 00 vpextrd \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: c4 e3 79 21 c0 00 vinsertps \$0x0,%xmm0,%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 79 21 00 00 vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 79 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 79 20 00 00 vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c5 f9 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: c5 f9 c4 00 00 vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e1 79 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e1 79 c4 00 00 vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 79 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 79 22 00 00 vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c5 f8 ae 10 vldmxcsr \(%eax\)
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+[a-f0-9]+: c5 f8 ae 18 vstmxcsr \(%eax\)
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+[a-f0-9]+: c4 e1 78 ae 10 vldmxcsr \(%eax\)
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+[a-f0-9]+: c4 e1 78 ae 18 vstmxcsr \(%eax\)
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+[a-f0-9]+: c4 e2 78 f2 00 andn \(%eax\),%eax,%eax
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+[a-f0-9]+: c4 e2 78 f7 00 bextr %eax,\(%eax\),%eax
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+[a-f0-9]+: c4 e2 78 f3 18 blsi \(%eax\),%eax
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+[a-f0-9]+: c4 e2 78 f3 10 blsmsk \(%eax\),%eax
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+[a-f0-9]+: c4 e2 78 f3 08 blsr \(%eax\),%eax
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+[a-f0-9]+: c4 e2 78 f5 00 bzhi %eax,\(%eax\),%eax
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+[a-f0-9]+: c4 e2 7b f6 00 mulx \(%eax\),%eax,%eax
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+[a-f0-9]+: c4 e2 7b f5 00 pdep \(%eax\),%eax,%eax
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+[a-f0-9]+: c4 e2 7a f5 00 pext \(%eax\),%eax,%eax
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+[a-f0-9]+: c4 e3 7b f0 00 00 rorx \$0x0,\(%eax\),%eax
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+[a-f0-9]+: c4 e2 7a f7 00 sarx %eax,\(%eax\),%eax
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+[a-f0-9]+: c4 e2 79 f7 00 shlx %eax,\(%eax\),%eax
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+[a-f0-9]+: c4 e2 7b f7 00 shrx %eax,\(%eax\),%eax
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+[a-f0-9]+: 8f ea 78 10 00 00 00 00 00 bextr \$0x0,\(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 01 08 blcfill \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 02 30 blci \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 01 28 blcic \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 02 08 blcmsk \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 01 18 blcs \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 01 10 blsfill \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 01 30 blsic \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 01 38 t1mskc \(%eax\),%eax
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+[a-f0-9]+: 8f e9 78 01 20 tzmsk \(%eax\),%eax
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#pass
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83
gas/testsuite/gas/i386/vex-lig-2.s
Normal file
83
gas/testsuite/gas/i386/vex-lig-2.s
Normal file
@ -0,0 +1,83 @@
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# Check VEX non-LIG instructions with with -mavxscalar=256
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.allow_index_reg
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.text
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_start:
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vmovd %eax, %xmm0
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vmovd (%eax), %xmm0
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{vex3} vmovd %eax, %xmm0
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{vex3} vmovd (%eax), %xmm0
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vmovd %xmm0, %eax
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vmovd %xmm0, (%eax)
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{vex3} vmovd %xmm0, %eax
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{vex3} vmovd %xmm0, (%eax)
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vmovq %xmm0, %xmm0
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vmovq (%eax), %xmm0
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{vex3} vmovq %xmm0, %xmm0
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{vex3} vmovq (%eax), %xmm0
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{store} vmovq %xmm0, %xmm0
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vmovq %xmm0, (%eax)
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{vex3} {store} vmovq %xmm0, %xmm0
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{vex3} vmovq %xmm0, (%eax)
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vextractps $0, %xmm0, %eax
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vextractps $0, %xmm0, (%eax)
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vpextrb $0, %xmm0, %eax
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vpextrb $0, %xmm0, (%eax)
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vpextrw $0, %xmm0, %eax
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{vex3} vpextrw $0, %xmm0, %eax
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{store} vpextrw $0, %xmm0, %eax
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vpextrw $0, %xmm0, (%eax)
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vpextrd $0, %xmm0, %eax
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vpextrd $0, %xmm0, (%eax)
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vinsertps $0, %xmm0, %xmm0, %xmm0
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vinsertps $0, (%eax), %xmm0, %xmm0
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vpinsrb $0, %eax, %xmm0, %xmm0
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vpinsrb $0, (%eax), %xmm0, %xmm0
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vpinsrw $0, %eax, %xmm0, %xmm0
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vpinsrw $0, (%eax), %xmm0, %xmm0
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{vex3} vpinsrw $0, %eax, %xmm0, %xmm0
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{vex3} vpinsrw $0, (%eax), %xmm0, %xmm0
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vpinsrd $0, %eax, %xmm0, %xmm0
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vpinsrd $0, (%eax), %xmm0, %xmm0
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vldmxcsr (%eax)
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vstmxcsr (%eax)
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{vex3} vldmxcsr (%eax)
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{vex3} vstmxcsr (%eax)
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andn (%eax), %eax, %eax
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bextr %eax, (%eax), %eax
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blsi (%eax), %eax
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blsmsk (%eax), %eax
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blsr (%eax), %eax
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bzhi %eax, (%eax), %eax
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mulx (%eax), %eax, %eax
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pdep (%eax), %eax, %eax
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pext (%eax), %eax, %eax
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rorx $0, (%eax), %eax
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sarx %eax, (%eax), %eax
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shlx %eax, (%eax), %eax
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shrx %eax, (%eax), %eax
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bextr $0, (%eax), %eax
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blcfill (%eax), %eax
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blci (%eax), %eax
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blcic (%eax), %eax
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blcmsk (%eax), %eax
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blcs (%eax), %eax
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blsfill (%eax), %eax
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blsic (%eax), %eax
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t1mskc (%eax), %eax
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tzmsk (%eax), %eax
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@ -17,4 +17,25 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 f1 fd 08 6e 21 vmovq \(%rcx\),%xmm4
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+[a-f0-9]+: 62 f1 fd 08 6e e1 vmovq %rcx,%xmm4
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+[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
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+[a-f0-9]+: 62 f3 7d 08 17 c0 00 vextractps \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 17 00 00 vextractps \$0x0,%xmm0,\(%rax\)
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+[a-f0-9]+: 62 f3 7d 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
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+[a-f0-9]+: 62 f1 7d 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
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+[a-f0-9]+: 62 f3 7d 08 16 c0 00 vpextrd \$0x0,%xmm0,%eax
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+[a-f0-9]+: 62 f3 7d 08 16 00 00 vpextrd \$0x0,%xmm0,\(%rax\)
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+[a-f0-9]+: 62 f3 fd 08 16 c0 00 vpextrq \$0x0,%xmm0,%rax
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+[a-f0-9]+: 62 f3 fd 08 16 00 00 vpextrq \$0x0,%xmm0,\(%rax\)
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+[a-f0-9]+: 62 f3 7d 08 21 c0 00 vinsertps \$0x0,%xmm0,%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 21 00 00 vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
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+[a-f0-9]+: 62 f1 7d 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: 62 f1 7d 08 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 7d 08 22 00 00 vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 fd 08 22 c0 00 vpinsrq \$0x0,%rax,%xmm0,%xmm0
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+[a-f0-9]+: 62 f3 fd 08 22 00 00 vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
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#pass
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@ -13,3 +13,34 @@ _start:
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{evex} vmovq (%rcx),%xmm4
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{evex} vmovq %rcx,%xmm4
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{evex} vmovq %xmm4,%xmm6
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{evex} vextractps $0, %xmm0, %eax
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{evex} vextractps $0, %xmm0, (%rax)
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{evex} vpextrb $0, %xmm0, %eax
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{evex} vpextrb $0, %xmm0, (%rax)
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{evex} vpextrw $0, %xmm0, %eax
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{evex} {store} vpextrw $0, %xmm0, %eax
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{evex} vpextrw $0, %xmm0, (%rax)
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{evex} vpextrd $0, %xmm0, %eax
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{evex} vpextrd $0, %xmm0, (%rax)
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{evex} vpextrq $0, %xmm0, %rax
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{evex} vpextrq $0, %xmm0, (%rax)
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|
||||
{evex} vinsertps $0, %xmm0, %xmm0, %xmm0
|
||||
{evex} vinsertps $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
{evex} vpinsrb $0, %eax, %xmm0, %xmm0
|
||||
{evex} vpinsrb $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
{evex} vpinsrw $0, %eax, %xmm0, %xmm0
|
||||
{evex} vpinsrw $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
{evex} vpinsrd $0, %eax, %xmm0, %xmm0
|
||||
{evex} vpinsrd $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
{evex} vpinsrq $0, %rax, %xmm0, %xmm0
|
||||
{evex} vpinsrq $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
78
gas/testsuite/gas/i386/x86-64-vex-lig-2.d
Normal file
78
gas/testsuite/gas/i386/x86-64-vex-lig-2.d
Normal file
@ -0,0 +1,78 @@
|
||||
#as: -mavxscalar=256
|
||||
#objdump: -dw
|
||||
#name: x86-64 VEX non-LIG insns with -mavxscalar=256
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
+[a-f0-9]+: c5 f9 6e c0 vmovd %eax,%xmm0
|
||||
+[a-f0-9]+: c5 f9 6e 00 vmovd \(%rax\),%xmm0
|
||||
+[a-f0-9]+: c4 e1 79 6e c0 vmovd %eax,%xmm0
|
||||
+[a-f0-9]+: c4 e1 79 6e 00 vmovd \(%rax\),%xmm0
|
||||
+[a-f0-9]+: c5 f9 7e c0 vmovd %xmm0,%eax
|
||||
+[a-f0-9]+: c5 f9 7e 00 vmovd %xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c4 e1 79 7e c0 vmovd %xmm0,%eax
|
||||
+[a-f0-9]+: c4 e1 79 7e 00 vmovd %xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c5 fa 7e c0 vmovq %xmm0,%xmm0
|
||||
+[a-f0-9]+: c5 fa 7e 00 vmovq \(%rax\),%xmm0
|
||||
+[a-f0-9]+: c4 e1 7a 7e c0 vmovq %xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e1 7a 7e 00 vmovq \(%rax\),%xmm0
|
||||
+[a-f0-9]+: c5 f9 d6 c0 vmovq %xmm0,%xmm0
|
||||
+[a-f0-9]+: c5 f9 d6 00 vmovq %xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c4 e1 79 d6 c0 vmovq %xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e1 79 d6 00 vmovq %xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c4 e3 79 17 c0 00 vextractps \$0x0,%xmm0,%eax
|
||||
+[a-f0-9]+: c4 e3 79 17 00 00 vextractps \$0x0,%xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c4 e3 79 14 c0 00 vpextrb \$0x0,%xmm0,%eax
|
||||
+[a-f0-9]+: c4 e3 79 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c5 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
|
||||
+[a-f0-9]+: c4 e1 79 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
|
||||
+[a-f0-9]+: c4 e3 79 15 c0 00 vpextrw \$0x0,%xmm0,%eax
|
||||
+[a-f0-9]+: c4 e3 79 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c4 e3 79 16 c0 00 vpextrd \$0x0,%xmm0,%eax
|
||||
+[a-f0-9]+: c4 e3 79 16 00 00 vpextrd \$0x0,%xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c4 e3 f9 16 c0 00 vpextrq \$0x0,%xmm0,%rax
|
||||
+[a-f0-9]+: c4 e3 f9 16 00 00 vpextrq \$0x0,%xmm0,\(%rax\)
|
||||
+[a-f0-9]+: c4 e3 79 21 c0 00 vinsertps \$0x0,%xmm0,%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e3 79 21 00 00 vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e3 79 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e3 79 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
|
||||
+[a-f0-9]+: c5 f9 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
|
||||
+[a-f0-9]+: c5 f9 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e1 79 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e1 79 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e3 79 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e3 79 22 00 00 vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e3 f9 22 c0 00 vpinsrq \$0x0,%rax,%xmm0,%xmm0
|
||||
+[a-f0-9]+: c4 e3 f9 22 00 00 vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
|
||||
+[a-f0-9]+: c5 f8 ae 10 vldmxcsr \(%rax\)
|
||||
+[a-f0-9]+: c5 f8 ae 18 vstmxcsr \(%rax\)
|
||||
+[a-f0-9]+: c4 e1 78 ae 10 vldmxcsr \(%rax\)
|
||||
+[a-f0-9]+: c4 e1 78 ae 18 vstmxcsr \(%rax\)
|
||||
+[a-f0-9]+: c4 e2 78 f2 00 andn \(%rax\),%eax,%eax
|
||||
+[a-f0-9]+: c4 e2 78 f7 00 bextr %eax,\(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 78 f3 18 blsi \(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 78 f3 10 blsmsk \(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 78 f3 08 blsr \(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 78 f5 00 bzhi %eax,\(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 7b f6 00 mulx \(%rax\),%eax,%eax
|
||||
+[a-f0-9]+: c4 e2 7b f5 00 pdep \(%rax\),%eax,%eax
|
||||
+[a-f0-9]+: c4 e2 7a f5 00 pext \(%rax\),%eax,%eax
|
||||
+[a-f0-9]+: c4 e3 7b f0 00 00 rorx \$0x0,\(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 7a f7 00 sarx %eax,\(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 79 f7 00 shlx %eax,\(%rax\),%eax
|
||||
+[a-f0-9]+: c4 e2 7b f7 00 shrx %eax,\(%rax\),%eax
|
||||
+[a-f0-9]+: 8f ea 78 10 00 00 00 00 00 bextr \$0x0,\(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 01 08 blcfill \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 02 30 blci \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 01 28 blcic \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 02 08 blcmsk \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 01 18 blcs \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 01 10 blsfill \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 01 30 blsic \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 01 38 t1mskc \(%rax\),%eax
|
||||
+[a-f0-9]+: 8f e9 78 01 20 tzmsk \(%rax\),%eax
|
||||
#pass
|
||||
89
gas/testsuite/gas/i386/x86-64-vex-lig-2.s
Normal file
89
gas/testsuite/gas/i386/x86-64-vex-lig-2.s
Normal file
@ -0,0 +1,89 @@
|
||||
# Check VEX non-LIG instructions with with -mavxscalar=256
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vmovd %eax, %xmm0
|
||||
vmovd (%rax), %xmm0
|
||||
{vex3} vmovd %eax, %xmm0
|
||||
{vex3} vmovd (%rax), %xmm0
|
||||
|
||||
vmovd %xmm0, %eax
|
||||
vmovd %xmm0, (%rax)
|
||||
{vex3} vmovd %xmm0, %eax
|
||||
{vex3} vmovd %xmm0, (%rax)
|
||||
|
||||
vmovq %xmm0, %xmm0
|
||||
vmovq (%rax), %xmm0
|
||||
{vex3} vmovq %xmm0, %xmm0
|
||||
{vex3} vmovq (%rax), %xmm0
|
||||
|
||||
{store} vmovq %xmm0, %xmm0
|
||||
vmovq %xmm0, (%rax)
|
||||
{vex3} {store} vmovq %xmm0, %xmm0
|
||||
{vex3} vmovq %xmm0, (%rax)
|
||||
|
||||
vextractps $0, %xmm0, %eax
|
||||
vextractps $0, %xmm0, (%rax)
|
||||
|
||||
vpextrb $0, %xmm0, %eax
|
||||
vpextrb $0, %xmm0, (%rax)
|
||||
|
||||
vpextrw $0, %xmm0, %eax
|
||||
{vex3} vpextrw $0, %xmm0, %eax
|
||||
{store} vpextrw $0, %xmm0, %eax
|
||||
vpextrw $0, %xmm0, (%rax)
|
||||
|
||||
vpextrd $0, %xmm0, %eax
|
||||
vpextrd $0, %xmm0, (%rax)
|
||||
|
||||
vpextrq $0, %xmm0, %rax
|
||||
vpextrq $0, %xmm0, (%rax)
|
||||
|
||||
vinsertps $0, %xmm0, %xmm0, %xmm0
|
||||
vinsertps $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
vpinsrb $0, %eax, %xmm0, %xmm0
|
||||
vpinsrb $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
vpinsrw $0, %eax, %xmm0, %xmm0
|
||||
vpinsrw $0, (%rax), %xmm0, %xmm0
|
||||
{vex3} vpinsrw $0, %eax, %xmm0, %xmm0
|
||||
{vex3} vpinsrw $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
vpinsrd $0, %eax, %xmm0, %xmm0
|
||||
vpinsrd $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
vpinsrq $0, %rax, %xmm0, %xmm0
|
||||
vpinsrq $0, (%rax), %xmm0, %xmm0
|
||||
|
||||
vldmxcsr (%rax)
|
||||
vstmxcsr (%rax)
|
||||
{vex3} vldmxcsr (%rax)
|
||||
{vex3} vstmxcsr (%rax)
|
||||
|
||||
andn (%rax), %eax, %eax
|
||||
bextr %eax, (%rax), %eax
|
||||
blsi (%rax), %eax
|
||||
blsmsk (%rax), %eax
|
||||
blsr (%rax), %eax
|
||||
|
||||
bzhi %eax, (%rax), %eax
|
||||
mulx (%rax), %eax, %eax
|
||||
pdep (%rax), %eax, %eax
|
||||
pext (%rax), %eax, %eax
|
||||
rorx $0, (%rax), %eax
|
||||
sarx %eax, (%rax), %eax
|
||||
shlx %eax, (%rax), %eax
|
||||
shrx %eax, (%rax), %eax
|
||||
|
||||
bextr $0, (%rax), %eax
|
||||
blcfill (%rax), %eax
|
||||
blci (%rax), %eax
|
||||
blcic (%rax), %eax
|
||||
blcmsk (%rax), %eax
|
||||
blcs (%rax), %eax
|
||||
blsfill (%rax), %eax
|
||||
blsic (%rax), %eax
|
||||
t1mskc (%rax), %eax
|
||||
tzmsk (%rax), %eax
|
||||
@ -1,3 +1,13 @@
|
||||
2018-11-06 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
|
||||
EVex512, EVexLIG, EVexDYN): New.
|
||||
(ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
|
||||
insns): Use Vex128 instead of Vex=3 (aka VexLIG).
|
||||
(vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
|
||||
of EVex=4 (aka EVexLIG).
|
||||
* i386-tbl.h: Re-generate.
|
||||
|
||||
2018-11-06 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
|
||||
|
||||
@ -30,6 +30,16 @@
|
||||
#define VexW1 VexW=VEXW1
|
||||
#define VexWIG VexW=VEXWIG
|
||||
|
||||
#define Vex128 Vex=VEX128
|
||||
#define Vex256 Vex=VEX256
|
||||
#define VexLIG Vex=VEXScalar
|
||||
|
||||
#define EVex128 EVex=EVEX128
|
||||
#define EVex256 EVex=EVEX256
|
||||
#define EVex512 EVex=EVEX512
|
||||
#define EVexLIG EVex=EVEXLIG
|
||||
#define EVexDYN EVex=EVEXDYN
|
||||
|
||||
### MARKER ###
|
||||
|
||||
// Move instructions.
|
||||
@ -1204,7 +1214,7 @@ divps, 2, 0x5e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|
|
||||
divps, 2, 0xf5e, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
divss, 2, 0xf35e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
divss, 2, 0xf30f5e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
ldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex }
|
||||
ldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex128|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex }
|
||||
ldmxcsr, 1, 0xfae, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Dword|Unspecified|BaseIndex }
|
||||
maskmovq, 2, 0xff7, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegMMX }
|
||||
maxps, 2, 0x5f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
@ -1305,7 +1315,7 @@ sqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|N
|
||||
sqrtps, 2, 0xf51, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
sqrtss, 2, 0xf351, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
sqrtss, 2, 0xf30f51, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
stmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex }
|
||||
stmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex128|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex }
|
||||
stmxcsr, 1, 0xfae, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Dword|Unspecified|BaseIndex }
|
||||
subps, 2, 0x5c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
subps, 2, 0xf5c, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
@ -1995,7 +2005,7 @@ vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|Chec
|
||||
vinsertf128, 4, 0x6618, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
|
||||
vinsertps, 4, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
|
||||
vldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
|
||||
vldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex128|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
|
||||
vmaskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
|
||||
vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
|
||||
vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
@ -2210,7 +2220,7 @@ vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|N
|
||||
vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vsqrtsd, 3, 0xf251, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vsqrtss, 3, 0xf351, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vstmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
|
||||
vstmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex128|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
|
||||
vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vsubsd, 3, 0xf25c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
@ -2502,14 +2512,14 @@ xend, 0, 0xf01d5, None, 3, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
|
||||
xtest, 0, 0xf01d6, None, 3, CpuHLE|CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
// BMI2 instructions.
|
||||
bzhi, 3, 0xf5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
mulx, 3, 0xf2f6, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
pdep, 3, 0xf2f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
pext, 3, 0xf3f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
rorx, 3, 0xf2f0, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=2|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
sarx, 3, 0xf3f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
shlx, 3, 0x66f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
shrx, 3, 0xf2f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
bzhi, 3, 0xf5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
mulx, 3, 0xf2f6, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
pdep, 3, 0xf2f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
pext, 3, 0xf3f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
rorx, 3, 0xf2f0, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=2|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
sarx, 3, 0xf3f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
shlx, 3, 0x66f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
shrx, 3, 0xf2f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
|
||||
// FMA4 instructions
|
||||
|
||||
@ -2707,24 +2717,24 @@ lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|IgnoreSize|No_bSuf|No_wSuf|No
|
||||
|
||||
// BMI instructions
|
||||
|
||||
andn, 3, 0xf2, None, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
bextr, 3, 0xf7, None, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsi, 2, 0xf3, 0x3, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsmsk, 2, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
andn, 3, 0xf2, None, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
bextr, 3, 0xf7, None, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsi, 2, 0xf3, 0x3, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsmsk, 2, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
tzcnt, 2, 0xf30fbc, None, 2, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
|
||||
// TBM instructions
|
||||
bextr, 3, 0x10, None, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=5|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcfill, 2, 0x01, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blci, 2, 0x02, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcic, 2, 0x01, 0x5, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
bextr, 3, 0x10, None, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=5|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcfill, 2, 0x01, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blci, 2, 0x02, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcic, 2, 0x01, 0x5, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|CheckRegSize|Vex128|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
|
||||
// AMD 3DNow! instructions.
|
||||
|
||||
@ -3470,8 +3480,8 @@ vextracti32x4, 3, 0x6639, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=2|Vex
|
||||
vextractf64x4, 3, 0x661B, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|VexOpcode=2|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vextracti64x4, 3, 0x663B, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|VexOpcode=2|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|RegMem }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX512F, Modrm|EVex128|VexOpcode=2|VexWIG|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX512F|Cpu64, Modrm|EVex128|VexOpcode=2|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|RegMem }
|
||||
|
||||
vfixupimmpd, 4, 0x6654, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vfixupimmpd, 5, 0x6654, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegZMM }
|
||||
@ -3665,7 +3675,7 @@ vinserti32x4, 4, 0x6638, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=2|VexVVV
|
||||
vinsertf64x4, 4, 0x661A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vinserti64x4, 4, 0x663A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
|
||||
vinsertps, 4, 0x6621, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vinsertps, 4, 0x6621, None, 1, CpuAVX512F, Modrm|EVex128|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vmaxpd, 3, 0x665F, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vmaxpd, 4, 0x665F, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
|
||||
@ -4289,16 +4299,16 @@ vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW, Modrm|Masking=2|VexOpcode=2|VexVVVV=1|
|
||||
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|VexOpcode=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
|
||||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW, Modrm|VexOpcode=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
|
||||
|
||||
vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Load|Modrm|EVex=4|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexWIG|VexVVVV=1|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexWIG|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Load|Modrm|EVex128|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=2|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=2|VexWIG|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=0|VexWIG|VexVVVV=1|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=0|VexWIG|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex128|VexOpcode=2|VexWIG|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
|
||||
@ -4434,12 +4444,12 @@ vinsertf32x8, 4, 0x661A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|VexOpcode=
|
||||
vinserti32x8, 4, 0x663A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
|
||||
vfpclassss, 3, 0x6667, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask }
|
||||
vpextrd, 3, 0x6616, None, 1, CpuAVX512DQ, Modrm|EVex=4|VexOpcode=2|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vpinsrd, 4, 0x6622, None, 1, CpuAVX512DQ, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpextrd, 3, 0x6616, None, 1, CpuAVX512DQ, Modrm|EVex128|VexOpcode=2|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vpinsrd, 4, 0x6622, None, 1, CpuAVX512DQ, Modrm|EVex128|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vfpclasssd, 3, 0x6667, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=2|VexOpcode=2|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask }
|
||||
vpextrq, 3, 0x6616, None, 1, CpuAVX512DQ, Modrm|EVex=4|VexOpcode=2|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
|
||||
vpinsrq, 4, 0x6622, None, 1, CpuAVX512DQ, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpextrq, 3, 0x6616, None, 1, CpuAVX512DQ, Modrm|EVex128|VexOpcode=2|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
|
||||
vpinsrq, 4, 0x6622, None, 1, CpuAVX512DQ, Modrm|EVex128|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vextractf64x2, 3, 0x6619, None, 1, CpuAVX512DQ, Modrm|MaskingMorZ|VexOpcode=2|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vextracti64x2, 3, 0x6639, None, 1, CpuAVX512DQ, Modrm|MaskingMorZ|VexOpcode=2|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
|
||||
@ -13734,7 +13734,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -15377,7 +15377,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -33058,7 +33058,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -33077,7 +33077,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -33216,7 +33216,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
1, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
1, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -33253,7 +33253,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -37333,7 +37333,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37352,7 +37352,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37390,7 +37390,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
1, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37428,7 +37428,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
2, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
2, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37504,7 +37504,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
3, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37523,7 +37523,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37542,7 +37542,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37849,7 +37849,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37871,7 +37871,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
3, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37915,7 +37915,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
1, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
1, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37959,7 +37959,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
2, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
2, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -38025,7 +38025,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
3, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -38047,7 +38047,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
3, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -43300,7 +43300,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -49627,7 +49627,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -49646,7 +49646,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -49665,7 +49665,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -49684,7 +49684,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -49703,7 +49703,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -49722,7 +49722,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -49741,7 +49741,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -49760,7 +49760,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -53403,7 +53403,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53422,7 +53422,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -53441,7 +53441,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -53460,7 +53460,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53476,7 +53476,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53492,7 +53492,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53524,7 +53524,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53540,7 +53540,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53556,7 +53556,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53572,7 +53572,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53588,7 +53588,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53604,7 +53604,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53620,7 +53620,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53636,7 +53636,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
@ -53652,7 +53652,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
|
||||
0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
|
||||
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Reference in New Issue
Block a user