Handle long jumps for .code16 and .arch < 386 by using a two
instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target. Add jumps/nojumps .arch modifier.
This commit is contained in:
Alan Modra
parent
c90cedf93e
commit
fddf5b5bc2
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@ -1,5 +1,25 @@
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2001-02-13 Alan Modra <alan@linuxcare.com.au>
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* doc/c-i386.texi (i386-Arch): Add "jumps"/"nojumps" blurb.
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Mention effect of < 386 architectures on jump promotion.
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(i386-Jumps): xref above. Don't assume long disp is 32 bits.
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* config/tc-i386.c (no_cond_jump_promotion): New.
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(set_cpu_arch): Parse "jumps" arch modifier.
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(insn_size): Modify usage comment.
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(ENCODE_RELAX_STATE): Reformat and protect macro arg.
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(SIZE_FROM_RELAX_STATE): Rename to DISP_SIZE_FROM_RELAX_STATE.
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(TYPE_FROM_RELAX_STATE): New define.
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(UNCOND_JUMP, COND_JUMP): Renumber.
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(md_relax_table): Reorder to suit.
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(COND_JUMP86): New define.
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(md_relax_table): Handle COND_JUMP86 cases. Add a few comments.
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(md_assemble): Create frag var for jumps of max size, encode relax
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state for COND_JUMP86.
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(md_estimate_size_before_relax): Handle COND_JUMP86 cases, and
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leave conditional jumps small if no_cond_jump_promotion.
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(md_convert_frag): Likewise.
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* expr.c (operator): Don't bump input_line_pointer for two char
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operators. Instead return operator size via new param num_chars.
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(expr): Use above to parse multi-char operators correctly.
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@ -273,15 +273,20 @@ static const char *cpu_arch_name = NULL;
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/* CPU feature flags. */
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static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
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/* If set, conditional jumps are not automatically promoted to handle
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larger than a byte offset. */
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static unsigned int no_cond_jump_promotion = 0;
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/* Interface to relax_segment.
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There are 2 relax states for 386 jump insns: one for conditional &
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one for unconditional jumps. This is because these two types of
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jumps add different sizes to frags when we're figuring out what
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sort of jump to choose to reach a given label. */
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There are 3 major relax states for 386 jump insns because the
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different types of jumps add different sizes to frags when we're
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figuring out what sort of jump to choose to reach a given label. */
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/* Types. */
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#define COND_JUMP 1
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#define UNCOND_JUMP 2
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#define UNCOND_JUMP 1
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#define COND_JUMP 2
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#define COND_JUMP86 3
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/* Sizes. */
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#define CODE16 1
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#define SMALL 0
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@ -297,10 +302,12 @@ static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
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#endif
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#endif
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#define ENCODE_RELAX_STATE(type,size) \
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((relax_substateT) ((type<<2) | (size)))
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#define SIZE_FROM_RELAX_STATE(s) \
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( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
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#define ENCODE_RELAX_STATE(type, size) \
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((relax_substateT) (((type) << 2) | (size)))
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#define TYPE_FROM_RELAX_STATE(s) \
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((s) >> 2)
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#define DISP_SIZE_FROM_RELAX_STATE(s) \
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((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
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/* This table is used by relax_frag to promote short jumps to long
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ones where necessary. SMALL (short) jumps may be promoted to BIG
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@ -322,6 +329,17 @@ const relax_typeS md_relax_table[] =
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{1, 1, 0, 0},
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{1, 1, 0, 0},
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/* UNCOND_JUMP states. */
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
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/* dword jmp adds 3 bytes to frag:
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0 extra opcode bytes, 3 extra displacement bytes. */
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{0, 0, 3, 0},
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/* word jmp adds 1 byte to frag:
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0 extra opcode bytes, 1 extra displacement byte. */
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{0, 0, 1, 0},
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/* COND_JUMP states. */
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
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/* dword conditionals adds 4 bytes to frag:
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@ -331,15 +349,15 @@ const relax_typeS md_relax_table[] =
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1 extra opcode byte, 1 extra displacement byte. */
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{0, 0, 2, 0},
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
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/* dword jmp adds 3 bytes to frag:
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0 extra opcode bytes, 3 extra displacement bytes. */
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{0, 0, 3, 0},
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/* word jmp adds 1 byte to frag:
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0 extra opcode bytes, 1 extra displacement byte. */
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{0, 0, 1, 0}
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/* COND_JUMP86 states. */
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
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{127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
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/* dword conditionals adds 4 bytes to frag:
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1 extra opcode byte, 3 extra displacement bytes. */
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{0, 0, 4, 0},
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/* word conditionals add 3 bytes to frag:
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1 extra opcode byte, 2 extra displacement bytes. */
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{0, 0, 3, 0}
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};
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static const arch_entry cpu_arch[] = {
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@ -726,7 +744,8 @@ set_cpu_arch (dummy)
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if (strcmp (string, cpu_arch[i].name) == 0)
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{
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cpu_arch_name = cpu_arch[i].name;
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cpu_arch_flags = cpu_arch[i].flags | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
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cpu_arch_flags = (cpu_arch[i].flags
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| (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
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break;
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}
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}
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@ -738,6 +757,23 @@ set_cpu_arch (dummy)
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else
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as_bad (_("missing cpu architecture"));
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no_cond_jump_promotion = 0;
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if (*input_line_pointer == ','
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&& ! is_end_of_line[(unsigned char) input_line_pointer[1]])
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{
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char *string = ++input_line_pointer;
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int e = get_symbol_end ();
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if (strcmp (string, "nojumps") == 0)
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no_cond_jump_promotion = 1;
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else if (strcmp (string, "jumps") == 0)
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;
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else
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as_bad (_("no such architecture modifier: `%s'"), string);
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*input_line_pointer = e;
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}
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demand_empty_rest_of_line ();
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}
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@ -1197,7 +1233,8 @@ md_assemble (line)
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/* Points to template once we've found it. */
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const template *t;
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/* Count the size of the instruction generated. */
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/* Count the size of the instruction generated. Does not include
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variable part of jump insns before relax. */
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int insn_size = 0;
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int j;
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@ -2671,7 +2708,6 @@ md_assemble (line)
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/* Output jumps. */
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if (i.tm.opcode_modifier & Jump)
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{
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int size;
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int code16;
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int prefix;
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@ -2692,10 +2728,6 @@ md_assemble (line)
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i.prefixes--;
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}
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size = 4;
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if (code16)
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size = 2;
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if (i.prefixes != 0 && !intel_syntax)
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as_warn (_("skipping prefixes on this instruction"));
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@ -2704,7 +2736,7 @@ md_assemble (line)
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instruction we may generate in md_convert_frag. This is 2
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bytes for the opcode and room for the prefix and largest
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displacement. */
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frag_grow (prefix + 2 + size);
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frag_grow (prefix + 2 + 4);
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insn_size += prefix + 1;
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/* Prefix and 1 opcode byte go in fr_fix. */
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p = frag_more (prefix + 1);
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@ -2716,11 +2748,13 @@ md_assemble (line)
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/* 1 possible extra opcode + displacement go in var part.
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Pass reloc in fr_var. */
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frag_var (rs_machine_dependent,
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1 + size,
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1 + 4,
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i.disp_reloc[0],
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((unsigned char) *p == JUMP_PC_RELATIVE
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? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
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: ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16),
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: ((cpu_arch_flags & Cpu386) != 0
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? ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16
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: ENCODE_RELAX_STATE (COND_JUMP86, SMALL) | code16)),
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i.op[0].disps->X_add_symbol,
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i.op[0].disps->X_add_number,
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p);
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@ -3909,10 +3943,10 @@ md_estimate_size_before_relax (fragP, segment)
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old_fr_fix = fragP->fr_fix;
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opcode = (unsigned char *) fragP->fr_opcode;
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switch (opcode[0])
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switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
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{
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case JUMP_PC_RELATIVE:
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/* Make jmp (0xeb) a dword displacement jump. */
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case UNCOND_JUMP:
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/* Make jmp (0xeb) a (d)word displacement jump. */
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opcode[0] = 0xe9;
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fragP->fr_fix += size;
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fix_new (fragP, old_fr_fix, size,
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@ -3921,9 +3955,33 @@ md_estimate_size_before_relax (fragP, segment)
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reloc_type);
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break;
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default:
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case COND_JUMP86:
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if (no_cond_jump_promotion)
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return 1;
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if (size == 2)
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{
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/* Negate the condition, and branch past an
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unconditional jump. */
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opcode[0] ^= 1;
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opcode[1] = 3;
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/* Insert an unconditional jump. */
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opcode[2] = 0xe9;
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/* We added two extra opcode bytes, and have a two byte
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offset. */
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fragP->fr_fix += 2 + 2;
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fix_new (fragP, old_fr_fix + 2, 2,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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reloc_type);
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break;
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}
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/* Fall through. */
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case COND_JUMP:
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if (no_cond_jump_promotion)
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return 1;
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/* This changes the byte-displacement jump 0x7N
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to the dword-displacement jump 0x0f,0x8N. */
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to the (d)word-displacement jump 0x0f,0x8N. */
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opcode[1] = opcode[0] + 0x10;
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opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
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/* We've added an opcode byte. */
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@ -3933,6 +3991,10 @@ md_estimate_size_before_relax (fragP, segment)
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fragP->fr_offset, 1,
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reloc_type);
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break;
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default:
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BAD_CASE (fragP->fr_subtype);
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break;
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}
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frag_wane (fragP);
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return fragP->fr_fix - old_fr_fix;
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@ -3986,51 +4048,65 @@ md_convert_frag (abfd, sec, fragP)
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/* Displacement from opcode start to fill into instruction. */
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displacement_from_opcode_start = target_address - opcode_address;
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switch (fragP->fr_subtype)
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if ((fragP->fr_subtype & BIG) == 0)
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{
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case ENCODE_RELAX_STATE (COND_JUMP, SMALL):
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case ENCODE_RELAX_STATE (COND_JUMP, SMALL16):
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case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL):
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case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16):
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/* Don't have to change opcode. */
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extension = 1; /* 1 opcode + 1 displacement */
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where_to_put_displacement = &opcode[1];
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break;
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case ENCODE_RELAX_STATE (COND_JUMP, BIG):
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extension = 5; /* 2 opcode + 4 displacement */
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opcode[1] = opcode[0] + 0x10;
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opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
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where_to_put_displacement = &opcode[2];
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break;
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case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
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extension = 4; /* 1 opcode + 4 displacement */
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opcode[0] = 0xe9;
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where_to_put_displacement = &opcode[1];
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break;
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case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
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extension = 3; /* 2 opcode + 2 displacement */
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opcode[1] = opcode[0] + 0x10;
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opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
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where_to_put_displacement = &opcode[2];
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break;
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case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
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extension = 2; /* 1 opcode + 2 displacement */
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opcode[0] = 0xe9;
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where_to_put_displacement = &opcode[1];
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break;
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default:
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BAD_CASE (fragP->fr_subtype);
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break;
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}
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else
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{
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if (no_cond_jump_promotion
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&& TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
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as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
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switch (fragP->fr_subtype)
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{
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case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
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extension = 4; /* 1 opcode + 4 displacement */
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opcode[0] = 0xe9;
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where_to_put_displacement = &opcode[1];
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break;
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case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
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extension = 2; /* 1 opcode + 2 displacement */
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opcode[0] = 0xe9;
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where_to_put_displacement = &opcode[1];
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break;
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case ENCODE_RELAX_STATE (COND_JUMP, BIG):
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case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
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extension = 5; /* 2 opcode + 4 displacement */
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opcode[1] = opcode[0] + 0x10;
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opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
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where_to_put_displacement = &opcode[2];
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break;
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case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
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extension = 3; /* 2 opcode + 2 displacement */
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opcode[1] = opcode[0] + 0x10;
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opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
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where_to_put_displacement = &opcode[2];
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break;
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case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
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extension = 4;
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opcode[0] ^= 1;
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opcode[1] = 3;
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opcode[2] = 0xe9;
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where_to_put_displacement = &opcode[3];
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break;
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default:
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BAD_CASE (fragP->fr_subtype);
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break;
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}
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}
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/* Now put displacement after opcode. */
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md_number_to_chars ((char *) where_to_put_displacement,
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(valueT) (displacement_from_opcode_start - extension),
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SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
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DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
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fragP->fr_fix += extension;
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}
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@ -26,7 +26,7 @@ extending the Intel architecture to 64-bits.
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* i386-Regs:: Register Naming
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* i386-Prefixes:: Instruction Prefixes
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* i386-Memory:: Memory References
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* i386-jumps:: Handling of Jump Instructions
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* i386-Jumps:: Handling of Jump Instructions
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* i386-Float:: Floating Point
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* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
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* i386-16bit:: Writing 16-bit Code
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@ -488,7 +488,7 @@ the default absolute addressing.
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Other addressing modes remain unchanged in x86-64 architecture, except
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registers used are 64-bit instead of 32-bit.
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@node i386-jumps
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@node i386-Jumps
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@section Handling of Jump Instructions
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@cindex jump optimization, i386
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@ -498,11 +498,11 @@ registers used are 64-bit instead of 32-bit.
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Jump instructions are always optimized to use the smallest possible
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displacements. This is accomplished by using byte (8-bit) displacement
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jumps whenever the target is sufficiently close. If a byte displacement
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is insufficient a long (32-bit) displacement is used. We do not support
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is insufficient a long displacement is used. We do not support
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word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
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instruction with the @samp{data16} instruction prefix), since the 80386
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insists upon masking @samp{%eip} to 16 bits after the word displacement
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is added.
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is added. (See also @pxref{i386-Arch})
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Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
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@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
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@ -696,13 +696,33 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{sledgehammer}
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@end multitable
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Apart from the warning, there is only one other effect on
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@code{@value{AS}} operation; If you specify a CPU other than
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Apart from the warning, there are only two other effects on
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@code{@value{AS}} operation; Firstly, if you specify a CPU other than
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@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
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will automatically use a two byte opcode sequence. The larger three
|
||||
byte opcode sequence is used on the 486 (and when no architecture is
|
||||
specified) because it executes faster on the 486. Note that you can
|
||||
explicitly request the two byte opcode by writing @samp{sarl %eax}.
|
||||
Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
|
||||
@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
|
||||
conditional jumps will be promoted when necessary to a two instruction
|
||||
sequence consisting of a conditional jump of the opposite sense around
|
||||
an unconditional jump to the target.
|
||||
|
||||
Following the CPU architecture, you may specify @samp{jumps} or
|
||||
@samp{nojumps} to control automatic promotion of conditional jumps.
|
||||
@samp{jumps} is the default, and enables jump promotion; All external
|
||||
jumps will be of the long variety, and file-local jumps will be promoted
|
||||
as necessary. (@pxref{i386-Jumps}) @samp{nojumps} leaves external
|
||||
conditional jumps as byte offset jumps, and warns about file-local
|
||||
conditional jumps that @code{@value{AS}} promotes.
|
||||
Unconditional jumps are treated as for @samp{jumps}.
|
||||
|
||||
For example
|
||||
|
||||
@smallexample
|
||||
.arch i8086,nojumps
|
||||
@end smallexample
|
||||
|
||||
@node i386-Notes
|
||||
@section Notes
|
||||
|
|
|
|||
Loading…
Reference in New Issue