Bunch of changes from Richard Earnshaw for generic bi-endian ARM aout targets.
Details in change logs.
This commit is contained in:
Ken Raeburn
parent
1b9016457d
commit
ff15324f63
10
ChangeLog
10
ChangeLog
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@ -1,3 +1,13 @@
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Thu May 18 18:08:49 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com>
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Changes for ARM based on patches from Richard Earnshaw:
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* config.sub: Handle armeb and armel.
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* configure.in: Omit arm linker only for riscix.
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Thu May 11 17:23:26 1995 Per Bothner <bothner@kalessin.cygnus.com>
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* config.guess: Update from FSF.
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Tue May 9 15:52:05 1995 Michael Meissner <meissner@cygnus.com>
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* config.sub: Recognize powerpcle as the little endian varient of
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@ -48,6 +48,7 @@ TODO
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VERSION
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aix386-core.c
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aout-adobe.c
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aout-arm.c
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aout-encap.c
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aout-ns32k.c
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aout-target.h
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@ -1,3 +1,37 @@
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Thu May 18 04:24:01 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com>
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Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
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* aoutx.h (aout_link_input_section_standard): If defined, call
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MY_relocatable_reloc before doing a partial relocation.
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* aout-arm.c: (WRITE_HEADERS): Delete.
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(NAME): Define version to override default in aoutx.h
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(MY(howto_table)): Reformat. Alter some entries slightly.
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(RELOC_ARM_BITS_NEG_{BIG,LITTLE}): Define.
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(MY(reloc_howto), MY(put_reloc), MY(relocatable_reloc)): New functions.
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(MY_reloc_howto, MY_put_reloc, MY_relocatable_reloc): Define.
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(MY(fix_pcrel_26)): Renamed from aoutarm_fix_pcrel_26, return
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bfd_reloc_ok not bfd_reloc_continue.
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(MY(fix_pcrel_26_done)): Likewise.
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(MY(bfd_reloc_type_lookup)): Renamed from aoutarm_reloc_type_lookup.
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(MY_bfd_link_hash_table_create, MY_bfd_link_add_symbols,
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MY_bfd_final_link): Delete.
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(MY_swap_std_reloc_in, MY_swap_std_reloc_out, MY_get_section_contents):
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Define.
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(aoutx.h): Include it.
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(MY(swap_std_reloc_{in,out})): New functions.
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Use RELOC_ARM_BITS_NEG_{BIG,LITTLE} to extract negative reloc bit.
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(aoutarm_squirt_out_relocs): Delete.
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From: David Taylor (dtaylor@armltd.co.uk)
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* config/arm[lb]-aout.mt: New files.
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* aout-arm.c: New file.
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* config.bfd: Handle arm{,e[lb]}-*-aout
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* configure.in: Add vetor for aout_arm_{big,little}_vec.
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* reloc.c: New relocation types for the ARM.
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* targets.c (aout_arm_{big,little}_vec): declare.
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Tue May 16 10:29:51 1995 Jim Kingdon <kingdon@deneb.cygnus.com>
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* libbfd.c (bfd_stat): If bfd_cache_lookup returns an error,
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@ -362,7 +362,7 @@ case "${target}" in
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noconfigdirs="$noconfigdirs libg++ libstdc++ libio librx"
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;;
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# end-sanitize-psion
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arm-*-*)
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arm-*-riscix*)
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noconfigdirs="$noconfigdirs ld"
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;;
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h8300*-*-* | \
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102
gas/ChangeLog
102
gas/ChangeLog
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@ -1,3 +1,105 @@
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Thu May 18 04:25:11 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com>
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Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
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* config/tc-arm.c (CP_T_{Pre,UD,WB}): Define, bits in co-processor
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instructions.
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([ls]fm_flags): Correct error in bitmasks.
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(cp_address_required_here): Delete second parameter, FLAGS. All
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callers changed. Remove all dead code referring to FLAGS. If
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address is just "[Reg]" then convert into a PRE-INCREMENT UP format.
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(do_fp_ldmstm): Handle full-descending and empty-ascending stack
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formats explicitly.
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* config/tc-arm.c (internalError): Define.
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(ARM_{1,2,250,3,6,7,7DM,ANY,2UP,ALL,3UP,6UP,LONGMUL}): Define processor
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variants.
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(FPU_{CORE,FPA10,FPA11,NONE,ALL,MEMMULTI}): Define floating point
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variants.
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({CPU,FPU}_DEFAULT): Define.
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(cpu_variant): New variable.
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(asm_flg): Change more_flags to flag_bits.
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Add prototypes for new functions.
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(FLAG_{S,P,B,T,ED,FD,FA,EA,IB,IA,DB,DA,L}): Delete.
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(s_flag[], ldst_flags[], byte_flag[], cmp_flags[], ldm_flags[],
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stm_flags[], lfm_flags[], sfm_flags[], round_flags[], except_flags[],
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cplong_flag[]): New variables.
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(asm_opcode, insns[]): New format, add version support.
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(arm_flg_hsh): Delete.
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(do_mul, do_mla): Remove "Warning" from warning messages.
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(do_arit): Simplify.
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(do_swap): Make error message more appropriate.
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(md_begin): Build hash tables starting at first entry in tables.
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(md_number_to_chars): Cope with big/little-endian selection.
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(md_chars_to_number): New function.
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(md_apply_fix): Rewrite to make endian independent.
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(tc_gen_reloc): Better error messages.
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(md_assemble): Reject opcodes forbidden by the currently selected cpu
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variant. Rewrite handling code for instruction flags.
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(md_shortopts): Add option "m:".
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(md_parse_option): Get the desired cpu/fpu variant.
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From: David Taylor (dtaylor@armltd.co.uk)
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* configure.in (architecture variants): Check for "armeb" and "arm*",
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set endianness accordingly.
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* read.c (read_a_source_file): New hooks md_start_line_hook and
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md_after_pass_hook.
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* config/arm-{big,lit}.mt: New files
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* config/tc-arm.h ({LITTLE,BIG}_ENDIAN, BYTE_ORDER): Define.
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(TARGET_FORMAT): Select depending on endianness and emulation and
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object format.
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(md_after_pass_hook, md_start_line_hook): Define.
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* config/tc-arm.c: Include subsegs.h, symbols.h and listing.h.
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(shift[]): Add uppper case equivalents.
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(CP_T_[XY], TRANS_BIT): Define.
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(conds[]): Delete initial NULL entry, add "lo" entry as synonym for
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"cc".
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(LONGEST_FLAG, flags[]): Delete.
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(arm_psr): New structure.
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(psrs[]): New variable.
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(PSR_ALL): Define.
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(LONGEST_INST): Bump to 5.
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(LITERAL_MASK, COND_MASK, OPCODE_MASK, DATA_OP_SHIFT): Define.
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(OPCODE_{AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,TST,TEQ,CMP,CMN,ORR,MOV,BIC,
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MVN}): Define.
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(insns[]): Add smull, umull, smlal, umlal, ldfm, stfm, msr and mrs
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instructions. Add nop and adr pseudo ops.
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(reg_table): Add APCS register name variants.
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(arm_psr_hsh): New hash table.
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(md_pseudo_table): Add "ltorg", "pool", "extend", "ldouble" and
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"packed".
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(MAX_LITERAL_POOL_SIZE): Define.
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(struct literalS): New structure.
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(literals, next_literal_pool_place, lit_pool_num, current_poolP): New
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variables.
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(add_to_lit_pool, symbol_locate, symbol_make_empty): New functions.
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(validate_immediate): Return FAIL on failure.
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(s_ltorg): New function.
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(psr_required_here, psrf_required_here): New functions.
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(cp_address_required_here): New parameter, flag, all callers changed.
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If flag is non-zero, restrict the legal addressing modes.
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(do_nop, do_mrs, do_msr, do_mull): New functions.
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(negate_data_op): New function.
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(data_op2): accept #x,y meaning x rotated right by y, but only when
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suitable constants. If immediate is not legal, try changing the
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opcode.
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(do_adr): New function.
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(do_ldst): accept "ldr reg, =expr". Put expr in the pool if it can't
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be done as an immediate.
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(do_fp_ldst): Use CP_T_[XY], not immediate values.
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(do_fp_ldmstm): New function.
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(arm_psr_parse): New function.
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(output_inst): Use INSN_SIZE in call to md_number_to_chars.
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(md_assemble): Add hack so that "Label instruction" causes alignment of
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the label.
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(arm_after_pass_hook, arm_start_line_hook, arm_frob_symbol): New
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functions.
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Wed May 17 05:25:16 1995 Michael Meissner <meissner@tiktok.cygnus.com>
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* config/tc-ppc.c (md_show_usage): Add \'s at end of lines in
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strings for non-GCC compilers.
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Tue May 16 19:36:00 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
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* config/obj-ecoff.c (ecoff_pop_insert): New function.
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@ -41,6 +41,8 @@ Things-to-keep:
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aout_gnu.h
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alpha-opcode.h
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arm-big.mt
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arm-lit.mt
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atof-ieee.c
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atof-tahoe.c
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atof-vax.c
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@ -0,0 +1 @@
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TDEFINES=-DTARGET_BYTES_BIG_ENDIAN
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@ -0,0 +1 @@
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TDEFINES=-DTARGET_BYTES_LITTLE_ENDIAN
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@ -1,3 +1,17 @@
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Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
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* arm/arm7dm.s: New file -- tests for ARM7DM instructions.
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* arm/arm6.s: Correct bogus tests.
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* arm/gas.exp (arm6.s): Is now a valid test.
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(arm7dm.s): New test.
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* arm/float.s: Add load/store multiple floating point instruction
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tests.
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Wed May 3 13:14:44 1995 Jeff Law (law@snake.cs.utah.edu)
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* gas/hppa/reloc/longcall.s: New test.
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* gas/hppa/reloc/reloc.exp: Run it.
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Tue May 2 16:37:48 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
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* gas/mips/ld.d: Modified for gas delay-slot fixes.
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@ -27,6 +27,7 @@ Things-to-keep:
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arm3.s
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arm6.s
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arm7dm.s
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copro.s
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float.s
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gas.exp
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@ -0,0 +1,12 @@
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.text
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.align 0
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smull r0, r1, r2, r3
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umull r0, r1, r2, r3
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smlal r0, r1, r2, r3
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umlal r0, r1, r4, r3
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smullne r0, r1, r3, r4
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smulls r1, r0, r9, r11
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umlaleqs r2, r9, r4, r9
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smlalge r14, r10, r8, r14
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@ -1,14 +1,14 @@
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#
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# Some ARM tests
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#
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if [istarget arm-*-riscix*] then {
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if [istarget arm-*-*] then {
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gas_test "inst.s" "" $stdoptlist "Basic instruction set"
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gas_test "arm3.s" "" $stdoptlist "Arm 3 instructions"
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# These instructions aren't supported, and I'm told some are
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# actually invalid.
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gas_test_error "arm6.s" "" "Arm 6 instructions"
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gas_test "arm6.s" "" $stdoptlist "Arm 6 instructions"
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gas_test "arm7dm.s" "" $stdoptlist "Arm 7DM instructions"
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gas_test "copro.s" "" $stdoptlist "Co processor instructions"
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@ -41,6 +41,8 @@ Things-to-keep:
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alpha.mt
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alphaosf.mh
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armb-aout.mt
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arml-aout.mt
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cf-h8300h.mt
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coff-a29k.mt
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coff-h8300.mt
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@ -0,0 +1 @@
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EMUL=armaoutb
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@ -0,0 +1 @@
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EMUL=armaoutl
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@ -42,6 +42,8 @@ Things-to-keep:
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README
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a29k.sh
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alpha.sh
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armaoutb.sh
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armaoutl.sh
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coff_sparc.sh
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ebmon29k.sh
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elf32_sparc.sh
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@ -0,0 +1,7 @@
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SCRIPT_NAME=armaout
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OUTPUT_FORMAT="a.out-arm-big"
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HEADER_START_ADDR=0x8000
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TEXT_START_ADDR=0x8000
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NONPAGED_TEXT_START_ADDRESS=0x8000
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PAGE_SIZE=32768
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ARCH=arm
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@ -0,0 +1,7 @@
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SCRIPT_NAME=armaout
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OUTPUT_FORMAT="a.out-arm-little"
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HEADER_START_ADDR=0x8000
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TEXT_START_ADDR=0x8000
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NONPAGED_TEXT_START_ADDRESS=0x8000
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PAGE_SIZE=32768
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ARCH=arm
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@ -34,6 +34,7 @@ Things-to-keep:
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README
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a29k.sc
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alpha.sc
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armaout.sc
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aout.sc
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ebmon29k.sc
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elf.sc
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@ -0,0 +1,35 @@
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cat <<EOF
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OUTPUT_FORMAT("${OUTPUT_FORMAT}")
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OUTPUT_ARCH(${ARCH})
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${RELOCATING+${LIB_SEARCH_DIRS}}
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${STACKZERO+${RELOCATING+${STACKZERO}}}
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SECTIONS
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{
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.text ${RELOCATING+${TEXT_START_ADDR}} :
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{
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CREATE_OBJECT_SYMBOLS
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${RELOCATING+__stext_ = .;}
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*(.text)
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${PAD_TEXT+${RELOCATING+. = ${DATA_ALIGNMENT};}}
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${RELOCATING+_etext = ${DATA_ALIGNMENT};}
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${RELOCATING+__etext = ${DATA_ALIGNMENT};}
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}
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.data ${RELOCATING+${DATA_ALIGNMENT}} :
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{
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${RELOCATING+__sdata_ = .;}
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*(.data)
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${CONSTRUCTING+CONSTRUCTORS}
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${RELOCATING+_edata = .;}
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${RELOCATING+__edata = .;}
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}
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.bss ${RELOCATING+ SIZEOF(.data) + ADDR (.data)} :
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{
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${RELOCATING+ __bss_start = .};
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*(.bss)
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*(COMMON)
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${RELOCATING+_end = ALIGN(4) };
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${RELOCATING+__end = ALIGN(4) };
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}
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}
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EOF
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|
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@ -1,6 +1,6 @@
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/* Opcode table for the ARM.
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Copyright 1994 Free Software Foundation, Inc.
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Copyright 1994, 1995 Free Software Foundation, Inc.
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|
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -28,7 +28,8 @@ struct arm_opcode {
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%<bitfield>d print the bitfield in decimal
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%<bitfield>x print the bitfield in hex
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%<bitfield>r print as an ARM register
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%<bitfield>f print a floating point constant if >7 else an fp register
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%<bitfield>f print a floating point constant if >7 else a
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floating point register
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%c print condition code (always bits 28-31)
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%P print floating point precision in arithmetic insn
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%Q print floating point precision in ldf/stf insn
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@ -47,11 +48,16 @@ struct arm_opcode {
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%F print the COUNT field of a LFM/SFM instruction.
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*/
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/* Note: There is a partial ordering in this table - it must be searched from
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the top to obtain a correct match. */
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static struct arm_opcode arm_opcodes[] = {
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/* ARM instructions */
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{0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
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{0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
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{0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
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{0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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{0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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{0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
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{0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
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{0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
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|
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@ -72,8 +78,8 @@ static struct arm_opcode arm_opcodes[] = {
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{0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
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{0x04000000, 0x0c100000, "str%c%22'b%t\t%12-15r, %a"},
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{0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
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{0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"},
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{0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"},
|
||||
{0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
|
||||
{0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
|
||||
{0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
|
||||
{0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
|
||||
|
||||
|
|
@ -119,10 +125,6 @@ static struct arm_opcode arm_opcodes[] = {
|
|||
{0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
|
||||
{0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
|
||||
{0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
|
||||
{0x0d000200, 0x0f900fff, "sfm%cfd\t%12-14f, %F, [%16-19r]%21'!"},
|
||||
{0x0c900200, 0x0f900fff, "lfm%cfd\t%12-14f, %F, [%16-19r]%21'!"},
|
||||
{0x0c800200, 0x0f900fff, "sfm%cea\t%12-14f, %F, [%16-19r]%21'!"},
|
||||
{0x0d100200, 0x0f900fff, "lfm%cea\t%12-14f, %F, [%16-19r]%21'!"},
|
||||
{0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
|
||||
{0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
|
||||
|
||||
|
|
@ -130,8 +132,8 @@ static struct arm_opcode arm_opcodes[] = {
|
|||
{0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
|
||||
{0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
|
||||
{0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
|
||||
{0x0c000000, 0x0e100000, "stc%c%22`l\t%8-11d, cr%12-15d, %A"},
|
||||
{0x0c100000, 0x0e100000, "ldc%c%22`l\t%8-11d, cr%12-15d, %A"},
|
||||
{0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
|
||||
{0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
|
||||
/* the rest */
|
||||
{0x00000000, 0x00000000, "undefined instruction %0-31x"},
|
||||
{0x00000000, 0x00000000, 0}
|
||||
|
|
|
|||
Loading…
Reference in New Issue