* arm-tdep.c (arm_scan_prologue): Do not record FPA register saves
if there are no FPA registers. (arm_dwarf_reg_to_regnum): New function. (arm_register_type, arm_register_name): Return minimal values for unsupported registers. (arm_register_sim_regno): Handle iWMMXt registers. (arm_gdbarch_init): Record missing FPA registers if indicated by a target description. Recognize iWMMXt registers. Only register "info float" for FPA. Use ARM_NUM_REGS. Register arm_dwarf_reg_to_regnum. * arm-tdep.h (enum gdb_regnum): Add ARM_NUM_REGS and iWMMXt constants. (struct gdbarch_tdep): Add have_fpa_registers. * features/xscale-iwmmxt.xml: Update capitalization. * regformats/arm-with-iwmmxt.dat: Regenerated. * src/gdb/doc/gdb.texinfo (Standard Target Features): Mention case insensitivity. (ARM Features): Describe org.gnu.gdb.xscale.iwmmxt. * gdb.arch/iwmmxt-regs.c, gdb.arch/iwmmxt-regs.exp: Update register capitalization.
This commit is contained in:
Daniel Jacobowitz
parent
45d3b878ab
commit
ff6f572f8b
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@ -1,3 +1,21 @@
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2007-02-26 Daniel Jacobowitz <dan@codesourcery.com>
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* arm-tdep.c (arm_scan_prologue): Do not record FPA register saves
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if there are no FPA registers.
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(arm_dwarf_reg_to_regnum): New function.
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(arm_register_type, arm_register_name): Return minimal values for
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unsupported registers.
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(arm_register_sim_regno): Handle iWMMXt registers.
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(arm_gdbarch_init): Record missing FPA registers if indicated by
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a target description. Recognize iWMMXt registers. Only register
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"info float" for FPA. Use ARM_NUM_REGS. Register
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arm_dwarf_reg_to_regnum.
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* arm-tdep.h (enum gdb_regnum): Add ARM_NUM_REGS and iWMMXt
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constants.
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(struct gdbarch_tdep): Add have_fpa_registers.
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* features/xscale-iwmmxt.xml: Update capitalization.
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* regformats/arm-with-iwmmxt.dat: Regenerated.
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2007-02-24 Kevin Buettner <kevinb@redhat.com>
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* NEWS (New targets): Add entry for the Toshiba Media Processor.
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107
gdb/arm-tdep.c
107
gdb/arm-tdep.c
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@ -832,13 +832,15 @@ arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cac
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imm = (imm >> rot) | (imm << (32 - rot));
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sp_offset -= imm;
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}
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else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
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else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
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&& gdbarch_tdep (current_gdbarch)->have_fpa_registers)
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{
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sp_offset -= 12;
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regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
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cache->saved_regs[regno].addr = sp_offset;
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}
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else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
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else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
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&& gdbarch_tdep (current_gdbarch)->have_fpa_registers)
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{
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int n_saved_fp_regs;
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unsigned int fp_start_reg, fp_bound_reg;
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@ -1383,10 +1385,48 @@ arm_register_type (struct gdbarch *gdbarch, int regnum)
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return builtin_type_void_data_ptr;
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else if (regnum == ARM_PC_REGNUM)
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return builtin_type_void_func_ptr;
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else if (regnum >= ARRAY_SIZE (arm_register_names))
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/* These registers are only supported on targets which supply
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an XML description. */
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return builtin_type_int0;
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else
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return builtin_type_uint32;
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}
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/* Map a DWARF register REGNUM onto the appropriate GDB register
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number. */
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static int
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arm_dwarf_reg_to_regnum (int reg)
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{
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/* Core integer regs. */
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if (reg >= 0 && reg <= 15)
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return reg;
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/* Legacy FPA encoding. These were once used in a way which
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overlapped with VFP register numbering, so their use is
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discouraged, but GDB doesn't support the ARM toolchain
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which used them for VFP. */
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if (reg >= 16 && reg <= 23)
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return ARM_F0_REGNUM + reg - 16;
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/* New assignments for the FPA registers. */
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if (reg >= 96 && reg <= 103)
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return ARM_F0_REGNUM + reg - 96;
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/* WMMX register assignments. */
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if (reg >= 104 && reg <= 111)
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return ARM_WCGR0_REGNUM + reg - 104;
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if (reg >= 112 && reg <= 127)
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return ARM_WR0_REGNUM + reg - 112;
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if (reg >= 192 && reg <= 199)
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return ARM_WC0_REGNUM + reg - 192;
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return -1;
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}
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/* Map GDB internal REGNUM onto the Arm simulator register numbers. */
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static int
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arm_register_sim_regno (int regnum)
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@ -1394,6 +1434,15 @@ arm_register_sim_regno (int regnum)
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int reg = regnum;
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gdb_assert (reg >= 0 && reg < NUM_REGS);
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if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
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return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
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if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
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return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
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if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
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return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
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if (reg < NUM_GREGS)
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return SIM_ARM_R0_REGNUM + reg;
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reg -= NUM_GREGS;
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@ -2482,6 +2531,11 @@ set_disassembly_style_sfunc (char *args, int from_tty,
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static const char *
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arm_register_name (int i)
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{
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if (i >= ARRAY_SIZE (arm_register_names))
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/* These registers are only supported on targets which supply
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an XML description. */
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return "";
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return arm_register_names[i];
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}
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@ -2597,6 +2651,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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enum arm_float_model fp_model = arm_fp_model;
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struct tdesc_arch_data *tdesc_data = NULL;
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int i;
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int have_fpa_registers = 1;
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/* Check any target description for validity. */
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if (tdesc_has_registers (info.target_desc))
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@ -2653,6 +2708,43 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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return NULL;
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}
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}
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else
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have_fpa_registers = 0;
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feature = tdesc_find_feature (info.target_desc,
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"org.gnu.gdb.xscale.iwmmxt");
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if (feature != NULL)
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{
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static const char *const iwmmxt_names[] = {
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"wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
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"wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
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"wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
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"wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
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};
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valid_p = 1;
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for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
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valid_p
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&= tdesc_numbered_register (feature, tdesc_data, i,
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iwmmxt_names[i - ARM_WR0_REGNUM]);
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/* Check for the control registers, but do not fail if they
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are missing. */
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for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
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tdesc_numbered_register (feature, tdesc_data, i,
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iwmmxt_names[i - ARM_WR0_REGNUM]);
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for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
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valid_p
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&= tdesc_numbered_register (feature, tdesc_data, i,
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iwmmxt_names[i - ARM_WR0_REGNUM]);
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if (!valid_p)
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{
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tdesc_data_cleanup (tdesc_data);
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return NULL;
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}
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}
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}
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/* If we have an object to base this architecture on, try to determine
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@ -2796,6 +2888,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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These are gdbarch discriminators, like the OSABI. */
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tdep->arm_abi = arm_abi;
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tdep->fp_model = fp_model;
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tdep->have_fpa_registers = have_fpa_registers;
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/* Breakpoints. */
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switch (info.byte_order)
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@ -2858,14 +2951,20 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
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/* Information about registers, etc. */
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set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
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set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
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set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
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set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
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set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
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set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
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set_gdbarch_register_type (gdbarch, arm_register_type);
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/* This "info float" is FPA-specific. Use the generic version if we
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do not have FPA. */
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if (gdbarch_tdep (gdbarch)->have_fpa_registers)
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set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
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/* Internal <-> external register number maps. */
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set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
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set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
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set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
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/* Integer registers are 4 bytes. */
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@ -44,6 +44,19 @@ enum gdb_regnum {
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ARM_F7_REGNUM = 23, /* last floating point register */
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ARM_FPS_REGNUM = 24, /* floating point status register */
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ARM_PS_REGNUM = 25, /* Contains processor status */
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ARM_WR0_REGNUM, /* WMMX data registers. */
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ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
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ARM_WC0_REGNUM, /* WMMX control registers. */
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ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
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ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
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ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
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ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
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ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
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ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
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ARM_NUM_REGS,
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/* Other useful registers. */
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ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
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THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
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ARM_NUM_ARG_REGS = 4,
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@ -146,6 +159,8 @@ struct gdbarch_tdep
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enum arm_float_model fp_model; /* Floating point calling conventions. */
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int have_fpa_registers; /* Does the target report the FPA registers? */
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CORE_ADDR lowest_pc; /* Lowest address at which instructions
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will appear. */
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@ -1,3 +1,9 @@
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2007-02-26 Daniel Jacobowitz <dan@codesourcery.com>
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* src/gdb/doc/gdb.texinfo (Standard Target Features): Mention
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case insensitivity.
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(ARM Features): Describe org.gnu.gdb.xscale.iwmmxt.
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2007-02-18 Nick Roberts <nickrob@snap.net.nz>
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* gdb.texinfo (Top): Put Appendix A after numbered sections.
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@ -26082,6 +26082,10 @@ company or organization which selected the name, and the overall
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architecture to which the feature applies; so e.g.@: the feature
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containing ARM core registers is named @samp{org.gnu.gdb.arm.core}.
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The names of registers are not case sensitive for the purpose
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of recognizing standard features, but @value{GDBN} will only display
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registers using the capitalization used in the description.
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@subsection ARM Features
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@cindex target descriptions, ARM features
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@ -26092,6 +26096,10 @@ It should contain registers @samp{r0} through @samp{r13}, @samp{sp},
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The @samp{org.gnu.gdb.arm.fpa} feature is optional. If present, it
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should contain registers @samp{f0} through @samp{f7} and @samp{fps}.
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The @samp{org.gnu.gdb.xscale.iwmmxt} feature is optional. If present,
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it should contain at least registers @samp{wR0} through @samp{wR15} and
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@samp{wCGR0} through @samp{wCGR3}. The @samp{wCID}, @samp{wCon},
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@samp{wCSSF}, and @samp{wCASF} registers are optional.
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@include gpl.texi
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@ -17,28 +17,28 @@
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<field name="u64" type="uint64"/>
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</union>
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<reg name="wr0" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr1" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr2" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr3" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr4" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr5" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr6" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr7" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr8" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr9" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr10" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr11" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr12" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr13" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr14" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wr15" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR0" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR1" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR2" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR3" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR4" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR5" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR6" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR7" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR8" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR9" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR10" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR11" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR12" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR13" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR14" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wR15" bitsize="64" type="iwmmxt_vec64i"/>
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<reg name="wcssf" bitsize="32" type="int" group="vector"/>
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<reg name="wcasf" bitsize="32" type="int" group="vector"/>
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<reg name="wCSSF" bitsize="32" type="int" group="vector"/>
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<reg name="wCASF" bitsize="32" type="int" group="vector"/>
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<reg name="wcgr0" bitsize="32" type="int" group="vector"/>
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<reg name="wcgr1" bitsize="32" type="int" group="vector"/>
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<reg name="wcgr2" bitsize="32" type="int" group="vector"/>
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<reg name="wcgr3" bitsize="32" type="int" group="vector"/>
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<reg name="wCGR0" bitsize="32" type="int" group="vector"/>
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<reg name="wCGR1" bitsize="32" type="int" group="vector"/>
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<reg name="wCGR2" bitsize="32" type="int" group="vector"/>
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<reg name="wCGR3" bitsize="32" type="int" group="vector"/>
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</feature>
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|
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@ -27,25 +27,25 @@ expedite:r11,sp,pc
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0:
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0:
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32:cpsr
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64:wr0
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64:wr1
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64:wr2
|
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64:wr3
|
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64:wr4
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64:wr5
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64:wr6
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64:wr7
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64:wr8
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64:wr9
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64:wr10
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64:wr11
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64:wr12
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64:wr13
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64:wr14
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64:wr15
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32:wcssf
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32:wcasf
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32:wcgr0
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32:wcgr1
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32:wcgr2
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32:wcgr3
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64:wR0
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64:wR1
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64:wR2
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64:wR3
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64:wR4
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64:wR5
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64:wR6
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64:wR7
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64:wR8
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64:wR9
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64:wR10
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64:wR11
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64:wR12
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64:wR13
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64:wR14
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64:wR15
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32:wCSSF
|
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32:wCASF
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32:wCGR0
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32:wCGR1
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32:wCGR2
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32:wCGR3
|
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|
|
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|
|
@ -1,3 +1,8 @@
|
|||
2007-02-26 Daniel Jacobowitz <dan@codesourcery.com>
|
||||
|
||||
* gdb.arch/iwmmxt-regs.c, gdb.arch/iwmmxt-regs.exp: Update
|
||||
register capitalization.
|
||||
|
||||
2007-02-13 Denis Pilat <denis.pilat@st.com>
|
||||
|
||||
* gdb.mi/mi-var-invalidate.exp: New file.
|
||||
|
|
|
|||
|
|
@ -22,57 +22,57 @@
|
|||
void
|
||||
read_regs (unsigned long long regs[16], unsigned long control_regs[6])
|
||||
{
|
||||
asm volatile ("wstrd wr0, %0" : "=m" (regs[0]));
|
||||
asm volatile ("wstrd wr1, %0" : "=m" (regs[1]));
|
||||
asm volatile ("wstrd wr2, %0" : "=m" (regs[2]));
|
||||
asm volatile ("wstrd wr3, %0" : "=m" (regs[3]));
|
||||
asm volatile ("wstrd wr4, %0" : "=m" (regs[4]));
|
||||
asm volatile ("wstrd wr5, %0" : "=m" (regs[5]));
|
||||
asm volatile ("wstrd wr6, %0" : "=m" (regs[6]));
|
||||
asm volatile ("wstrd wr7, %0" : "=m" (regs[7]));
|
||||
asm volatile ("wstrd wr8, %0" : "=m" (regs[8]));
|
||||
asm volatile ("wstrd wr9, %0" : "=m" (regs[9]));
|
||||
asm volatile ("wstrd wr10, %0" : "=m" (regs[10]));
|
||||
asm volatile ("wstrd wr11, %0" : "=m" (regs[11]));
|
||||
asm volatile ("wstrd wr12, %0" : "=m" (regs[12]));
|
||||
asm volatile ("wstrd wr13, %0" : "=m" (regs[13]));
|
||||
asm volatile ("wstrd wr14, %0" : "=m" (regs[14]));
|
||||
asm volatile ("wstrd wr15, %0" : "=m" (regs[15]));
|
||||
asm volatile ("wstrd wR0, %0" : "=m" (regs[0]));
|
||||
asm volatile ("wstrd wR1, %0" : "=m" (regs[1]));
|
||||
asm volatile ("wstrd wR2, %0" : "=m" (regs[2]));
|
||||
asm volatile ("wstrd wR3, %0" : "=m" (regs[3]));
|
||||
asm volatile ("wstrd wR4, %0" : "=m" (regs[4]));
|
||||
asm volatile ("wstrd wR5, %0" : "=m" (regs[5]));
|
||||
asm volatile ("wstrd wR6, %0" : "=m" (regs[6]));
|
||||
asm volatile ("wstrd wR7, %0" : "=m" (regs[7]));
|
||||
asm volatile ("wstrd wR8, %0" : "=m" (regs[8]));
|
||||
asm volatile ("wstrd wR9, %0" : "=m" (regs[9]));
|
||||
asm volatile ("wstrd wR10, %0" : "=m" (regs[10]));
|
||||
asm volatile ("wstrd wR11, %0" : "=m" (regs[11]));
|
||||
asm volatile ("wstrd wR12, %0" : "=m" (regs[12]));
|
||||
asm volatile ("wstrd wR13, %0" : "=m" (regs[13]));
|
||||
asm volatile ("wstrd wR14, %0" : "=m" (regs[14]));
|
||||
asm volatile ("wstrd wR15, %0" : "=m" (regs[15]));
|
||||
|
||||
asm volatile ("wstrw wcssf, %0" : "=m" (control_regs[0]));
|
||||
asm volatile ("wstrw wcasf, %0" : "=m" (control_regs[1]));
|
||||
asm volatile ("wstrw wcgr0, %0" : "=m" (control_regs[2]));
|
||||
asm volatile ("wstrw wcgr1, %0" : "=m" (control_regs[3]));
|
||||
asm volatile ("wstrw wcgr2, %0" : "=m" (control_regs[4]));
|
||||
asm volatile ("wstrw wcgr3, %0" : "=m" (control_regs[5]));
|
||||
asm volatile ("wstrw wCSSF, %0" : "=m" (control_regs[0]));
|
||||
asm volatile ("wstrw wCASF, %0" : "=m" (control_regs[1]));
|
||||
asm volatile ("wstrw wCGR0, %0" : "=m" (control_regs[2]));
|
||||
asm volatile ("wstrw wCGR1, %0" : "=m" (control_regs[3]));
|
||||
asm volatile ("wstrw wCGR2, %0" : "=m" (control_regs[4]));
|
||||
asm volatile ("wstrw wCGR3, %0" : "=m" (control_regs[5]));
|
||||
}
|
||||
|
||||
void
|
||||
write_regs (unsigned long long regs[16], unsigned long control_regs[6])
|
||||
{
|
||||
asm volatile ("wldrd wr0, %0" : : "m" (regs[0]));
|
||||
asm volatile ("wldrd wr1, %0" : : "m" (regs[1]));
|
||||
asm volatile ("wldrd wr2, %0" : : "m" (regs[2]));
|
||||
asm volatile ("wldrd wr3, %0" : : "m" (regs[3]));
|
||||
asm volatile ("wldrd wr4, %0" : : "m" (regs[4]));
|
||||
asm volatile ("wldrd wr5, %0" : : "m" (regs[5]));
|
||||
asm volatile ("wldrd wr6, %0" : : "m" (regs[6]));
|
||||
asm volatile ("wldrd wr7, %0" : : "m" (regs[7]));
|
||||
asm volatile ("wldrd wr8, %0" : : "m" (regs[8]));
|
||||
asm volatile ("wldrd wr9, %0" : : "m" (regs[9]));
|
||||
asm volatile ("wldrd wr10, %0" : : "m" (regs[10]));
|
||||
asm volatile ("wldrd wr11, %0" : : "m" (regs[11]));
|
||||
asm volatile ("wldrd wr12, %0" : : "m" (regs[12]));
|
||||
asm volatile ("wldrd wr13, %0" : : "m" (regs[13]));
|
||||
asm volatile ("wldrd wr14, %0" : : "m" (regs[14]));
|
||||
asm volatile ("wldrd wr15, %0" : : "m" (regs[15]));
|
||||
asm volatile ("wldrd wR0, %0" : : "m" (regs[0]));
|
||||
asm volatile ("wldrd wR1, %0" : : "m" (regs[1]));
|
||||
asm volatile ("wldrd wR2, %0" : : "m" (regs[2]));
|
||||
asm volatile ("wldrd wR3, %0" : : "m" (regs[3]));
|
||||
asm volatile ("wldrd wR4, %0" : : "m" (regs[4]));
|
||||
asm volatile ("wldrd wR5, %0" : : "m" (regs[5]));
|
||||
asm volatile ("wldrd wR6, %0" : : "m" (regs[6]));
|
||||
asm volatile ("wldrd wR7, %0" : : "m" (regs[7]));
|
||||
asm volatile ("wldrd wR8, %0" : : "m" (regs[8]));
|
||||
asm volatile ("wldrd wR9, %0" : : "m" (regs[9]));
|
||||
asm volatile ("wldrd wR10, %0" : : "m" (regs[10]));
|
||||
asm volatile ("wldrd wR11, %0" : : "m" (regs[11]));
|
||||
asm volatile ("wldrd wR12, %0" : : "m" (regs[12]));
|
||||
asm volatile ("wldrd wR13, %0" : : "m" (regs[13]));
|
||||
asm volatile ("wldrd wR14, %0" : : "m" (regs[14]));
|
||||
asm volatile ("wldrd wR15, %0" : : "m" (regs[15]));
|
||||
|
||||
asm volatile ("wldrw wcssf, %0" : : "m" (control_regs[0]));
|
||||
asm volatile ("wldrw wcasf, %0" : : "m" (control_regs[1]));
|
||||
asm volatile ("wldrw wcgr0, %0" : : "m" (control_regs[2]));
|
||||
asm volatile ("wldrw wcgr1, %0" : : "m" (control_regs[3]));
|
||||
asm volatile ("wldrw wcgr2, %0" : : "m" (control_regs[4]));
|
||||
asm volatile ("wldrw wcgr3, %0" : : "m" (control_regs[5]));
|
||||
asm volatile ("wldrw wCSSF, %0" : : "m" (control_regs[0]));
|
||||
asm volatile ("wldrw wCASF, %0" : : "m" (control_regs[1]));
|
||||
asm volatile ("wldrw wCGR0, %0" : : "m" (control_regs[2]));
|
||||
asm volatile ("wldrw wCGR1, %0" : : "m" (control_regs[3]));
|
||||
asm volatile ("wldrw wCGR2, %0" : : "m" (control_regs[4]));
|
||||
asm volatile ("wldrw wCGR3, %0" : : "m" (control_regs[5]));
|
||||
}
|
||||
|
||||
int
|
||||
|
|
|
|||
|
|
@ -47,32 +47,32 @@ if ![runto_main] then {
|
|||
|
||||
# Set all the registers to arbitrary values.
|
||||
for {set i 0} {$i < 16} {incr i 1} {
|
||||
gdb_test "set \$wr$i.u64 = ((${i}LL << 32) | ${i})" "" "set reg wr$i"
|
||||
gdb_test "set \$wR$i.u64 = ((${i}LL << 32) | ${i})" "" "set reg wR$i"
|
||||
}
|
||||
gdb_test "set \$wcssf = 300" "" "set reg wcssf"
|
||||
gdb_test "set \$wcasf = 200" "" "set reg wcasf"
|
||||
gdb_test "set \$wCSSF = 300" "" "set reg wCSSF"
|
||||
gdb_test "set \$wCASF = 200" "" "set reg wCASF"
|
||||
for {set i 0} {$i < 4} {incr i 1} {
|
||||
gdb_test "set \$wcgr$i = 100 + $i" "" "set reg wcgr$i"
|
||||
gdb_test "set \$wCGR$i = 100 + $i" "" "set reg wCGR$i"
|
||||
}
|
||||
|
||||
# See if the sets stuck.
|
||||
gdb_test "next" ".*write_regs.*" "next over read_regs"
|
||||
|
||||
for {set i 0} {$i < 16} {incr i 1} {
|
||||
gdb_test "p \$wr$i.u64 == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test reg wr$i"
|
||||
gdb_test "p \$wR$i.u64 == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test reg wR$i"
|
||||
}
|
||||
# Don't test wcssf.
|
||||
gdb_test "p \$wcasf" "\\\$$decimal = 200" "test reg wcasf"
|
||||
# Don't test wCSSF.
|
||||
gdb_test "p \$wCASF" "\\\$$decimal = 200" "test reg wCASF"
|
||||
for {set i 0} {$i < 4} {incr i 1} {
|
||||
gdb_test "p \$wcgr$i == 100 + $i" "\\\$$decimal = 1" "test reg wcgr$i"
|
||||
gdb_test "p \$wCGR$i == 100 + $i" "\\\$$decimal = 1" "test reg wCGR$i"
|
||||
}
|
||||
|
||||
# Also verify the copies read by the target.
|
||||
for {set i 0} {$i < 16} {incr i 1} {
|
||||
gdb_test "p regs\[$i\] == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test stored wr$i"
|
||||
gdb_test "p regs\[$i\] == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test stored wR$i"
|
||||
}
|
||||
# Don't test wcssf.
|
||||
gdb_test "p control_regs\[1\]" "\\\$$decimal = 200" "test stored wcasf"
|
||||
gdb_test "p control_regs\[1\]" "\\\$$decimal = 200" "test stored wCASF"
|
||||
for {set i 0} {$i < 4} {incr i 1} {
|
||||
gdb_test "p control_regs\[$i + 2\] == 100 + $i" "\\\$$decimal = 1" "test stored wcgr$i"
|
||||
gdb_test "p control_regs\[$i + 2\] == 100 + $i" "\\\$$decimal = 1" "test stored wCGR$i"
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue