* m32r-sim.h (GET_H_SM): New macro.
(UART params): Update to msa2000. * devices.c (device_io_read_buffer): Update to msa2000. * m32r.c (m32rb_h_cr_get,m32rb_h_cr_set): Handle bbpc,bbpsw. (m32rb_h_psw_get,m32rb_h_psw_set): New functions. * arch.c,arch.h,cpu.c,cpu.h,sem-switch.c,sem.c: Regenerate. * m32rx.c (m32rx_h_cr_get,m32rx_h_cr_set): Handle bbpc,bbpsw. (m32rx_h_psw_get,m32rx_h_psw_set): New functions. * cpux.c,cpux.h,readx.c,semx.c: Regenerate. PR 15938.
This commit is contained in:
Doug Evans
parent
5df02296c9
commit
ff8c385ab3
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@ -0,0 +1,108 @@
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/* m32r device support
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Copyright (C) 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sim-main.h"
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#ifdef HAVE_DV_SOCKSER
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#include "dv-sockser.h"
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#endif
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/* Handling the MSPR register is done by creating a device in the core
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mapping that winds up here. */
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device m32r_devices;
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int
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device_io_read_buffer (device *me, void *source, int space,
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address_word addr, unsigned nr_bytes,
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SIM_CPU *cpu, sim_cia cia)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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return nr_bytes;
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#ifdef HAVE_DV_SOCKSER
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if (addr == UART_INCHAR_ADDR)
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{
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int c = dv_sockser_read (sd);
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if (c == -1)
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return 0;
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*(char *) source = c;
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return 1;
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}
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if (addr == UART_STATUS_ADDR)
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{
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int status = dv_sockser_status (sd);
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unsigned char *p = source;
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p[0] = 0;
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p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
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#ifdef UART_INPUT_READY0
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? UART_INPUT_READY : 0)
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#else
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? 0 : UART_INPUT_READY)
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#endif
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+ ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
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return 2;
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}
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#endif
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return nr_bytes;
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}
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int
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device_io_write_buffer (device *me, const void *source, int space,
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address_word addr, unsigned nr_bytes,
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SIM_CPU *cpu, sim_cia cia)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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#if WITH_SCACHE
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/* MSPR support is deprecated but is kept in for upward compatibility
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with existing overlay support. */
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if (addr == MSPR_ADDR)
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{
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if ((*(const char *) source & MSPR_PURGE) != 0)
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scache_flush (sd);
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return nr_bytes;
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}
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if (addr == MCCR_ADDR)
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{
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if ((*(const char *) source & MCCR_CP) != 0)
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scache_flush (sd);
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return nr_bytes;
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}
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#endif
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if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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return nr_bytes;
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#if HAVE_DV_SOCKSER
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if (addr == UART_OUTCHAR_ADDR)
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{
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int rc = dv_sockser_write (sd, *(char *) source);
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return rc == 1;
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}
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#endif
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return nr_bytes;
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}
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void device_error () {}
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@ -716,10 +716,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
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EXTRACT_FMT_RTE_CODE
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/* Fetch the input operands for the semantic handler. */
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OPRND (h_bsm_0) = CPU (h_bsm);
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OPRND (h_bie_0) = CPU (h_bie);
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OPRND (h_bcond_0) = CPU (h_bcond);
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OPRND (h_bpc_0) = CPU (h_bpc);
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OPRND (h_cr_6) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 6));
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OPRND (h_cr_14) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 14));
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OPRND (h_bpsw_0) = CPU (h_bpsw);
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OPRND (h_bbpsw_0) = CPU (h_bbpsw);
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#undef OPRND
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}
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BREAK (read);
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@ -852,7 +852,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
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EXTRACT_FMT_TRAP_CODE
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/* Fetch the input operands for the semantic handler. */
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OPRND (h_cr_0) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 0));
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OPRND (h_cr_6) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 6));
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OPRND (h_bpsw_0) = CPU (h_bpsw);
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OPRND (h_psw_0) = m32rx_h_psw_get (current_cpu);
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OPRND (pc) = CPU (h_pc);
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OPRND (uimm4) = f_uimm4;
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#undef OPRND
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@ -3047,26 +3047,26 @@ SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
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do {
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{
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UBI opval = OPRND (h_bsm_0);
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CPU (h_sm) = opval;
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TRACE_RESULT (current_cpu, "sm-0", 'x', opval);
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}
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{
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UBI opval = OPRND (h_bie_0);
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CPU (h_ie) = opval;
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TRACE_RESULT (current_cpu, "ie-0", 'x', opval);
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}
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{
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UBI opval = OPRND (h_bcond_0);
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CPU (h_cond) = opval;
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TRACE_RESULT (current_cpu, "condbit", 'x', opval);
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}
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{
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USI opval = ANDSI (OPRND (h_bpc_0), -4);
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USI opval = ANDSI (OPRND (h_cr_6), -4);
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BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
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taken_p = 1;
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TRACE_RESULT (current_cpu, "pc", 'x', opval);
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}
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{
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USI opval = OPRND (h_cr_14);
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m32rx_h_cr_set (current_cpu, ((HOSTUINT) 6), opval);
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TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
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}
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{
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UQI opval = OPRND (h_bpsw_0);
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m32rx_h_psw_set (current_cpu, opval);
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TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
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}
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{
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UQI opval = OPRND (h_bbpsw_0);
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CPU (h_bpsw) = opval;
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TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
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}
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} while (0);
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PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
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@ -3842,15 +3842,30 @@ SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
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EXTRACT_FMT_TRAP_CODE
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do {
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{
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USI opval = OPRND (h_cr_6);
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m32rx_h_cr_set (current_cpu, ((HOSTUINT) 14), opval);
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TRACE_RESULT (current_cpu, "cr-14", 'x', opval);
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}
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{
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USI opval = ADDSI (OPRND (pc), 4);
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m32rx_h_cr_set (current_cpu, ((HOSTUINT) 6), opval);
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TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
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}
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{
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USI opval = ANDSI (SLLSI (OPRND (h_cr_0), 8), 65408);
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m32rx_h_cr_set (current_cpu, ((HOSTUINT) 0), opval);
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TRACE_RESULT (current_cpu, "cr-0", 'x', opval);
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UQI opval = OPRND (h_bpsw_0);
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CPU (h_bbpsw) = opval;
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TRACE_RESULT (current_cpu, "bbpsw-0", 'x', opval);
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}
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{
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UQI opval = OPRND (h_psw_0);
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CPU (h_bpsw) = opval;
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TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
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}
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{
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UQI opval = ANDQI (OPRND (h_psw_0), 128);
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m32rx_h_psw_set (current_cpu, opval);
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TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
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}
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{
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SI opval = m32r_trap (current_cpu, OPRND (pc), OPRND (uimm4));
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