Commit Graph

14956 Commits

Author SHA1 Message Date
GDB Administrator fe554d200d Automatic date update in version.in 2018-12-13 00:00:36 +00:00
GDB Administrator 60f9fdc9c2 Automatic date update in version.in 2018-12-12 00:00:28 +00:00
Max Filippov 00863b8e40 bfd: xtensa: ignore overflow in hight part of const16 relocation
32-bit constants loaded by two const16 opcodes that involve relocation
(e.g. calculated as a sum of a symbol and a constant) may overflow,
resulting in linking error with the following message:

  dangerous relocation: const16: cannot encode: (_start+0x70000000)

They should wrap around instead. Limit const16 opcode immediate field to
16 least significant bits to implement this wrap around.

bfd/
2018-12-11  Max Filippov  <jcmvbkbc@gmail.com>

	* elf32-xtensa.c (elf_xtensa_do_reloc): Limit const16 opcode
	immediate field to 16 least significant bits.
2018-12-11 14:21:39 -08:00
H.J. Lu 209d1499de xc16x: Add elf32_xc16x_rtype_to_howto
Add elf32_xc16x_rtype_to_howto to get reloc_howto_type pointer from
ELF32_R_TYPE.

	* elf32-xc16x.c (elf32_xc16x_rtype_to_howto): New function.
	(elf32_xc16x_relocate_section): Call elf32_xc16x_rtype_to_howto
	instead of xc16x_reloc_type_lookup to get reloc_howto_type.
2018-12-11 06:01:46 -08:00
GDB Administrator 5136770380 Automatic date update in version.in 2018-12-11 00:00:36 +00:00
GDB Administrator ecfe6254b5 Automatic date update in version.in 2018-12-10 00:00:44 +00:00
GDB Administrator b5ac78ffc6 Automatic date update in version.in 2018-12-09 00:00:45 +00:00
GDB Administrator 5aee1c38f9 Automatic date update in version.in 2018-12-08 00:00:28 +00:00
H.J. Lu fbcc8bafeb Override the previous definition from IR object
Mark the previous definition from IR object as undefined so that the
generic linker will override it.

bfd/

	PR ld/23958
	* elflink.c (_bfd_elf_add_default_symbol): Override the previous
	definition from IR object.

ld/

	PR ld/23958
	* testsuite/ld-plugin/lto.exp: Run PR ld/23958 test.
	* testsuite/ld-plugin/pr23958.c: New file.
	* testsuite/ld-plugin/pr23958.t: Likewise.
2018-12-07 15:40:02 -08:00
Stafford Horne 42e151bf4c gdb/or1k: Add linux debugging support
Up until now OpenRISC GDB only has supported bare metal debugging.  This
patch adds linux userspace debugging and core dump analysis support.

The changes are loosely based on nios2 and riscv implementations.

This was tested with linux 4.20 core dumps for executables linked
against musl libc.

bfd/ChangeLog:

	* elf32-or1k.c (or1k_grok_prstatus): New function.
	(or1k_grok_psinfo): Likewise.

gdb/ChangeLog:

	* Makefile.in (ALL_TARGET_OBS): Add or1k-linux-tdep.o.
	* configure.tgt: Add or1k*-*-linux*.
	* or1k-linux-tdep.c: New file.
	* or1k-tdep.c (or1k_gdbarch_init): Call gdbarch_init_osabi.
2018-12-08 07:07:36 +09:00
H.J. Lu d2ef37ebd9 elf: Report property change when merging properties
With merging properties, report property change in linker map file, like

Merging program properties

Removed property 0xc0010000 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (0x0) and /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crti.o (0x0)
Removed property 0xc0000002 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (0x3) and x.o (not found)
Removed property 0xc0000000 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (not found) and /usr/lib64/libc_nonshared.a(elf-init.oS) (0x0)
Removed property 0xc0000001 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (not found) and /usr/lib64/libc_nonshared.a(elf-init.oS) (0x0)

bfd/

	* elf-properties.c (elf_find_and_remove_property): Add a
	bfd_boolean argument to indicate if the property should be
	removed.
	(elf_merge_gnu_property_list): Updated.  Report
	property change in linker map file.
	(elf_get_gnu_property_section_size): Skip property_remove
	properties.
	(elf_write_gnu_properties): Likewise.
	(_bfd_elf_link_setup_gnu_properties): Report property merge
	in linker map file.  Pass abfd to elf_merge_gnu_property_list.

include/

	* bfdlink.h (bfd_link_info): Add has_map_file.

ld/

	* NEWS: Updated for property change report.
	* ld.texi: Document property change report.
	* ldmain.c (main): Set link_info.has_map_file to TRUE when
	linker map file is used.
	* testsuite/ld-scripts/rgn-over1.d: Updated.
	* testsuite/ld-scripts/rgn-over2.d: Likewise.
	* testsuite/ld-scripts/rgn-over3.d: Likewise.
	* testsuite/ld-scripts/rgn-over4.d: Likewise.
	* testsuite/ld-scripts/rgn-over5.d: Likewise.
	* testsuite/ld-scripts/rgn-over6.d: Likewise.
	* testsuite/ld-scripts/rgn-over7.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Check linker map
	file.
	* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a.map: New file.
2018-12-07 08:30:43 -08:00
Alan Modra c2f5dc30af PR23952, memory leak in _bfd_generic_read_minisymbols
bfd/
	PR 23952
	* syms.c (_bfd_generic_read_minisymbols): Free syms before
	returning with zero symcount.
binutils/
	* nm.c (display_rel_file): Use xrealloc to increase minisyms
	for synthetic symbols.
2018-12-08 00:11:16 +10:30
GDB Administrator 67bb16f345 Automatic date update in version.in 2018-12-07 00:00:46 +00:00
Alan Modra bb6bf75e7a PowerPC @l, @h and @ha warnings, plus VLE e_li
This patch started off just adding the warnings in tc-ppc.c about
incorrect usage of @l, @h and @ha in instructions that don't have
16-bit D-form fields.  That unfortunately showed up three warnings in
ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like
	e_li r3, IV_table@l+0x00
which was being assembled to
   8:	70 60 00 00 	e_li    r3,0
			a: R_PPC_ADDR16_LO	IV_table
The ADDR16_LO reloc is of course completely bogus on e_li, which has
a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit
in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800.
Applying an ADDR16_LO reloc to the instruction potentially changes
the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i,
e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis,
e_and2is, or some invalid encodings.

Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was
added 2017-09-05 but I can't see code in gas to generate the
relocation.  In any case, VLE_ADDR20 probably doesn't have the correct
semantics for @l since ideally you'd want an @l to pair with @h or @ha
to generate a 32-bit constant.  Thus @l should only produce a 16-bit
value, I think.  So we need some more relocations to handle e_li it
seems, or as I do in this patch, modify the behaviour of existing
relocations when applied to e_li instructions.

include/
	* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
bfd/
	* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct
	mask and shift value.
	(ppc_elf_vle_split16): Use E_OPCODE_MASK.  Handle e_li
	specially.
gas/
	* config/tc-ppc.c (md_assemble): Adjust relocs for VLE before
	TLS tweaks.  Handle e_li.  Warn on unexpected operand field
	for lo16/hi16/ha16 relocs.
2018-12-06 23:01:03 +10:30
GDB Administrator eb7be1abbc Automatic date update in version.in 2018-12-06 00:00:31 +00:00
Sam Tebbs 3a67e1a6b4 [aarch64] Add support for pointer authentication B key
Armv8.3-A has another key used in pointer authentication called the
B-key (other than the A-key that is already supported). In order for
stack unwinders to work it is necessary to be able to identify frames
that have been signed with the B-key rather than the A-key and it was
felt that keeping this as an augmentation character in the CIE was the
best bet. The DWARF extensions for ARM therefore propose to add a new
augmentation character 'B' to the CIE augmentation string and the
corresponding cfi directive ".cfi_b_key_frame". I've made the relevant
changes to GAS and LD to add support for B-key unwinding, which required
modifying LD to check for 'B' in the augmentation string, adding the
".cfi_b_key_frame" directive to GAS and adding a "pauth_key" field to
GAS's fde_entry and cie_entry structs.

The pointer authentication instructions will behave as NOPs on
architectures that don't support them, and so a check for the
architecture being assembled for is not necessary since there will be no
behavioural difference between augmentation strings with and without the
'B' character on such architectures.

2018-12-05  Sam Tebbs  <sam.tebbs@arm.com>

bfd/
	* elf-eh-frame.c (_bfd_elf_parse_eh_frame): Add check for 'B'.

gas/
	* dw2gencfi.c (struct cie_entry): Add tc_cie_entry_extras invocation.
	(alloc_fde_entry): Add tc_fde_entry_init_extra invocation.
	(output_cie): Add tc_output_cie_extra invocation.
	(select_cie_for_fde): Add tc_cie_fde_equivalent_extra and
	tc_cie_entry_init_extra invocation.
	(frch_cfi_data, cfa_save_data): Move to dwgencfi.h.
	* config/tc-aarch64.c (s_aarch64_cfi_b_key_frame): Declare.
	(md_pseudo_table): Add "cfi_b_key_frame".
	* config/tc-aarch64.h (tc_fde_entry_extras, tc_cie_entry_extras,
	tc_fde_entry_init_extra, tc_output_cie_extra,
	tc_cie_fde_equivalent_extra, tc_cie_entry_init_extra): Define.
	* dw2gencfi.h (struct fde_entry): Add tc_fde_entry_extras invocation.
	(pointer_auth_key): Define.
	(frch_cfi_data, cfa_save_data): Move from dwgencfi.c.
	* doc/c-aarch64.texi (.cfi_b_key_frame): Add documentation.
	* testsuite/gas/aarch64/(pac_ab_key.d, pac_ab_key.s): New file.
2018-12-05 18:30:08 +00:00
GDB Administrator 706adc3493 Automatic date update in version.in 2018-12-05 00:00:40 +00:00
H.J. Lu fde51dd189 x86: Don't remove empty GNU_PROPERTY_X86_UINT32_OR_AND properties
For GNU_PROPERTY_X86_COMPAT_ISA_1_USED and GNU_PROPERTY_X86_UINT32_OR_AND
properties, a bit in the output pr_data field is set if it is set in any
relocatable input pr_data fields and this property is present in all
relocatable input files.  A missing property implies that its bits have
unknown values.  When all bits in the the output pr_data field are zero,
this property should not be removed from output to indicate it has zero
in all bits.

bfd/

	PR ld/23372
	* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Don't remove
	empty properties for GNU_PROPERTY_X86_COMPAT_ISA_1_USED and
	GNU_PROPERTY_X86_UINT32_OR_AND.
	(_bfd_x86_elf_link_fixup_gnu_properties): Likewise.

ld/

	PR ld/23372
	* testsuite/ld-i386/pr23372a.d: Updated.
	* testsuite/ld-i386/pr23372c.d: Likewise.
	* testsuite/ld-x86-64/pr23372a-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372a.d: Likewise.
	* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372c.d: Likewise.
2018-12-04 06:01:14 -08:00
GDB Administrator b90514cfb5 Automatic date update in version.in 2018-12-04 00:00:27 +00:00
Jim Wilson 1080bf78c0 RISC-V: Accept version, supervisor ext and more than one NSE for -march.
This patch moves all -march parsing logic into bfd, because we will use this
code in ELF attributes.

	bfd/
	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro.
	(struct riscv_subset_t): New structure.
	(riscv_subset_t): New typedef.
	(riscv_subset_list_t): New structure.
	(riscv_release_subset_list): New prototype.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	* elfxx-riscv.c: Include safe-ctype.h.
	(riscv_parsing_subset_version): New function.
	(riscv_supported_std_ext): Likewise.
	(riscv_parse_std_ext): Likewise.
	(riscv_parse_sv_or_non_std_ext): Likewise.
	(riscv_parse_subset): Likewise.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	gas/
	* config/tc-riscv.c: Include elfxx-riscv.h.
	(struct riscv_subset): Removed.
	(riscv_subsets): Change type to riscv_subset_list_t.
	(riscv_subset_supports): Removed argument: xlen_required and move
	logic into libbfd.
	(riscv_multi_subset_supports): Removed argument: xlen_required.
	(riscv_clear_subsets): Removed.
	(riscv_add_subset): Ditto.
	(riscv_set_arch): Extract parsing logic into libbfd.
	(riscv_ip): Update argument for riscv_multi_subset_supports and
	riscv_subset_supports. Update riscv_subsets due to struct definition
	changed.
	(riscv_after_parse_args): Update riscv_subsets due to struct
	definition changed, update and argument for riscv_subset_supports.
	* testsuite/gas/riscv/empty.s: New.
	* testsuite/gas/riscv/march-fail-rv32ef.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
	* testsuite/gas/riscv/march-ok-g2.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d
	* testsuite/gas/riscv/march-ok-s-with-version.d: Likewise.
	* testsuite/gas/riscv/march-ok-s.d: Likewise.
	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
	include/
	* opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
	unsigned.
	opcodes/
	* riscv-opc.c: Change the type of xlen, because type of
	xlen_requirement changed.
2018-12-03 14:05:17 -08:00
GDB Administrator b570a287cf Automatic date update in version.in 2018-12-03 00:00:31 +00:00
GDB Administrator 3134061ce6 Automatic date update in version.in 2018-12-02 00:01:21 +00:00
H.J. Lu b44ee3a8cf x86: Delay setting the iplt section alignment
Delay setting its alignment until we know it is non-empty.  Otherwise an
empty iplt section may change vma and lma of the following sections, which
triggers moving dot of the following section backwards, resulting in a
warning and section lma not being set properly.  It later leads to a
"File truncated" error.

bfd/

	PR ld/23930
	* elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Update
	the iplt section alignment if it is non-empty.
	(_bfd_x86_elf_link_setup_gnu_properties): Set plt.iplt_alignment
	and delay setting the iplt section alignment.
	* elfxx-x86.h (elf_x86_plt_layout): Add iplt_alignment.

ld/

	PR ld/23930
	* testsuite/ld-i386/i386.exp: Run pr23930.
	* testsuite/ld-i386/pr23930.d: New file.
	* testsuite/ld-x86-64/pr23930-32.t: Likewise.
	* testsuite/ld-x86-64/pr23930-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23930.d: Likewise.
	* testsuite/ld-x86-64/pr23930.t: Likewise.
	* testsuite/ld-x86-64/pr23930a.s: Likewise.
	* testsuite/ld-x86-64/pr23930b.s: Likewise.
	* testsuite/ld-x86-64/x86-64.exp: Run pr23930 and pr23930-x32.
2018-12-01 06:35:03 -08:00
GDB Administrator 35d1b0784a Automatic date update in version.in 2018-12-01 00:00:23 +00:00
Nick Clifton 20a7119479 Add PR number to previous delta to the bfd/ directory. 2018-11-30 17:45:07 +00:00
Nick Clifton 5f60af5d24 Fix a memory exhaustion bug when attempting to allocate room for an impossible number of program headers.
* elfcode.h (elf_object_p): Check for corrupt input files with
	more program headers than can actually fit in the file.
2018-11-30 11:45:33 +00:00
Nick Clifton beab453223 Remove an abort in the bfd library and add a check for an integer overflow when mapping sections to segments.
PR 23932
	* elf.c (IS_CONTAINED_BY_LMA): Add a check for a negative section
	size.
	(rewrite_elf_program_header): If no sections are mapped into a
	segment return an error.
2018-11-30 11:43:12 +00:00
Alan Modra ba85c15dab PR23937, powerpc64le local ifunc IRELATIVE relocs are wrong
IFUNC resolvers must always be called via their global entry point.
They will be called from ld.so rather than from the local executable.

	PR 23937
bfd/
	* elf64-ppc.c (write_plt_relocs_for_local_syms): Don't add local
	entry offset for ifuncs.
ld/
	* testsuite/ld-powerpc/pr23937.d,
	* testsuite/ld-powerpc/pr23937.s: New test.
	* testsuite/ld-powerpc/powerpc.exp: Run it.
2018-11-30 16:18:58 +10:30
GDB Administrator f746c08f26 Automatic date update in version.in 2018-11-30 00:00:41 +00:00
H.J. Lu ffd9e4d022 elf: Don't merge .note.gnu.property section in IR
.note.gnu.property section in IR inputs should be ignored.  Don't
merge them.

	PR ld/23929
	* elf-properties.c (_bfd_elf_link_setup_gnu_properties): Don't
	merge .note.gnu.property section in IR inputs.
2018-11-29 04:45:16 -08:00
GDB Administrator 27e8f8efca Automatic date update in version.in 2018-11-29 00:00:26 +00:00
GDB Administrator f68d3e0053 Automatic date update in version.in 2018-11-28 00:00:18 +00:00
Thomas Preud'homme b5ab31636d [ARM] Update knowledge of bfd architectures
Commit c0c468d562 updated bfd's knowledge
of Arm architectures to Armv5TEJ and later but missed the list of CPUs
recognized by objdump -d -m<cpu>.

.note.gnu.arm.ident related code is intentionally not updated as build
attributes are a better mechanism to express the ISA in a file. However
this patch adds tests for the existing code since no existing testcase
cover those codepaths. Since I've only ever managed for
bfd_arm_get_mach_from_notes () to have an effect by using objcopy on
a file with a note but no Arm build attribute, the tests make use of
both objcopy actions supported by run_dump_test which requires to have a
ld line as well.

Note that the CPU list in bfd/cpu-arm.c was simply copied over from
GAS' CPU list but sorted alphabetically as already done for existing
entries.

2018-11-27  Thomas Preud'homme  <thomas.preudhomme@linaro.org>

bfd/
	* cpu-arm.c (processors): Add processors known to GAS but missing here
	and reindent.
	(bfd_arm_update_notes): Add comment explaining why the list of
	architectures in the switch should not be updated.
	(architectures): Likewise.

gas/
	* testsuite/gas/arm/cpu-arm1020.d: New testcase.
	* testsuite/gas/arm/cpu-arm1020e.d: Likewise.
	* testsuite/gas/arm/cpu-arm1020t.d: Likewise.
	* testsuite/gas/arm/cpu-arm1022e.d: Likewise.
	* testsuite/gas/arm/cpu-arm1026ej-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm1026ejs.d: Likewise.
	* testsuite/gas/arm/cpu-arm10e.d: Likewise.
	* testsuite/gas/arm/cpu-arm10t.d: Likewise.
	* testsuite/gas/arm/cpu-arm10tdmi.d: Likewise.
	* testsuite/gas/arm/cpu-arm1136j-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm1136jf-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm1136jfs.d: Likewise.
	* testsuite/gas/arm/cpu-arm1136js.d: Likewise.
	* testsuite/gas/arm/cpu-arm1156t2-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm1156t2f-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm1176jz-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm1176jzf-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm2.d: Likewise.
	* testsuite/gas/arm/cpu-arm250.d: Likewise.
	* testsuite/gas/arm/cpu-arm3.d: Likewise.
	* testsuite/gas/arm/cpu-arm6.d: Likewise.
	* testsuite/gas/arm/cpu-arm60.d: Likewise.
	* testsuite/gas/arm/cpu-arm600.d: Likewise.
	* testsuite/gas/arm/cpu-arm610.d: Likewise.
	* testsuite/gas/arm/cpu-arm620.d: Likewise.
	* testsuite/gas/arm/cpu-arm7.d: Likewise.
	* testsuite/gas/arm/cpu-arm70.d: Likewise.
	* testsuite/gas/arm/cpu-arm700.d: Likewise.
	* testsuite/gas/arm/cpu-arm700i.d: Likewise.
	* testsuite/gas/arm/cpu-arm710.d: Likewise.
	* testsuite/gas/arm/cpu-arm7100.d: Likewise.
	* testsuite/gas/arm/cpu-arm710c.d: Likewise.
	* testsuite/gas/arm/cpu-arm710t.d: Likewise.
	* testsuite/gas/arm/cpu-arm720.d: Likewise.
	* testsuite/gas/arm/cpu-arm720t.d: Likewise.
	* testsuite/gas/arm/cpu-arm740t.d: Likewise.
	* testsuite/gas/arm/cpu-arm7500.d: Likewise.
	* testsuite/gas/arm/cpu-arm7500fe.d: Likewise.
	* testsuite/gas/arm/cpu-arm7d.d: Likewise.
	* testsuite/gas/arm/cpu-arm7di.d: Likewise.
	* testsuite/gas/arm/cpu-arm7dm.d: Likewise.
	* testsuite/gas/arm/cpu-arm7dmi.d: Likewise.
	* testsuite/gas/arm/cpu-arm7m.d: Likewise.
	* testsuite/gas/arm/cpu-arm7t.d: Likewise.
	* testsuite/gas/arm/cpu-arm7tdmi-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm7tdmi.d: Likewise.
	* testsuite/gas/arm/cpu-arm8.d: Likewise.
	* testsuite/gas/arm/cpu-arm810.d: Likewise.
	* testsuite/gas/arm/cpu-arm9.d: Likewise.
	* testsuite/gas/arm/cpu-arm920.d: Likewise.
	* testsuite/gas/arm/cpu-arm920t.d: Likewise.
	* testsuite/gas/arm/cpu-arm922t.d: Likewise.
	* testsuite/gas/arm/cpu-arm926ej-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm926ej.d: Likewise.
	* testsuite/gas/arm/cpu-arm926ejs.d: Likewise.
	* testsuite/gas/arm/cpu-arm940t.d: Likewise.
	* testsuite/gas/arm/cpu-arm946e-r0.d: Likewise.
	* testsuite/gas/arm/cpu-arm946e-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm946e.d: Likewise.
	* testsuite/gas/arm/cpu-arm966e-r0.d: Likewise.
	* testsuite/gas/arm/cpu-arm966e-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm966e.d: Likewise.
	* testsuite/gas/arm/cpu-arm968e-s.d: Likewise.
	* testsuite/gas/arm/cpu-arm9e-r0.d: Likewise.
	* testsuite/gas/arm/cpu-arm9e.d: Likewise.
	* testsuite/gas/arm/cpu-arm9tdmi.d: Likewise.
	* testsuite/gas/arm/cpu-arm_any.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a12.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a15.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a17.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a32.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a35.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a5.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a53.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a55.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a57.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a7.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a72.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a73.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a75.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a76.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a8.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-a9.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m0.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m0plus.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m1.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m23.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m3.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m33.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m4.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-m7.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-r4.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-r4f.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-r5.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-r52.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-r7.d: Likewise.
	* testsuite/gas/arm/cpu-cortex-r8.d: Likewise.
	* testsuite/gas/arm/cpu-ep9312.d: Likewise.
	* testsuite/gas/arm/cpu-exynos-m1.d: Likewise.
	* testsuite/gas/arm/cpu-fa526.d: Likewise.
	* testsuite/gas/arm/cpu-fa606te.d: Likewise.
	* testsuite/gas/arm/cpu-fa616te.d: Likewise.
	* testsuite/gas/arm/cpu-fa626.d: Likewise.
	* testsuite/gas/arm/cpu-fa626te.d: Likewise.
	* testsuite/gas/arm/cpu-fa726te.d: Likewise.
	* testsuite/gas/arm/cpu-fmp626.d: Likewise.
	* testsuite/gas/arm/cpu-i80200.d: Likewise.
	* testsuite/gas/arm/cpu-iwmmxt.d: Likewise.
	* testsuite/gas/arm/cpu-iwmmxt2.d: Likewise.
	* testsuite/gas/arm/cpu-marvell-pj4.d: Likewise.
	* testsuite/gas/arm/cpu-marvell-whitney.d: Likewise.
	* testsuite/gas/arm/cpu-mpcore.d: Likewise.
	* testsuite/gas/arm/cpu-mpcorenovfp.d: Likewise.
	* testsuite/gas/arm/cpu-sa1.d: Likewise.
	* testsuite/gas/arm/cpu-strongarm.d: Likewise.
	* testsuite/gas/arm/cpu-strongarm1.d: Likewise.
	* testsuite/gas/arm/cpu-strongarm110.d: Likewise.
	* testsuite/gas/arm/cpu-strongarm1100.d: Likewise.
	* testsuite/gas/arm/cpu-strongarm1110.d: Likewise.
	* testsuite/gas/arm/cpu-xgene1.d: Likewise.
	* testsuite/gas/arm/cpu-xgene2.d: Likewise.
	* testsuite/gas/arm/cpu-xscale.d: Likewise.
	* testsuite/gas/arm/nop-asm.s: Likewise.
	* testsuite/gas/arm/note-march-armv2.d: Likewise.
	* testsuite/gas/arm/note-march-armv2.s: Likewise.
	* testsuite/gas/arm/note-march-armv2a.d: Likewise.
	* testsuite/gas/arm/note-march-armv2a.s: Likewise.
	* testsuite/gas/arm/note-march-armv3.d: Likewise.
	* testsuite/gas/arm/note-march-armv3.s: Likewise.
	* testsuite/gas/arm/note-march-armv3m.d: Likewise.
	* testsuite/gas/arm/note-march-armv3m.s: Likewise.
	* testsuite/gas/arm/note-march-armv4.d: Likewise.
	* testsuite/gas/arm/note-march-armv4.s: Likewise.
	* testsuite/gas/arm/note-march-armv4t.d: Likewise.
	* testsuite/gas/arm/note-march-armv4t.s: Likewise.
	* testsuite/gas/arm/note-march-armv5.d: Likewise.
	* testsuite/gas/arm/note-march-armv5.s: Likewise.
	* testsuite/gas/arm/note-march-armv5t.d: Likewise.
	* testsuite/gas/arm/note-march-armv5t.s: Likewise.
	* testsuite/gas/arm/note-march-armv5te.d: Likewise.
	* testsuite/gas/arm/note-march-armv5te.d: Likewise.
	* testsuite/gas/arm/note-march-ep9312.d: Likewise.
	* testsuite/gas/arm/note-march-ep9312.s: Likewise.
	* testsuite/gas/arm/note-march-iwmmxt.d: Likewise.
	* testsuite/gas/arm/note-march-iwmmxt.s: Likewise.
	* testsuite/gas/arm/note-march-iwmmxt2.d: Likewise.
	* testsuite/gas/arm/note-march-iwmmxt2.s: Likewise.
	* testsuite/gas/arm/note-march-xscale.d: Likewise.
	* testsuite/gas/arm/note-march-xscale.s: Likewise.
2018-11-27 18:28:35 +00:00
Maciej W. Rozycki 3c7687b9cd MIPS/LD: Accept high-part relocations in PIC code with absolute symbols
Accept R_MIPS_HI16, R_MIPS_HIGHER and R_MIPS_HIGHEST relocations and
their compressed counterparts in PIC code where the symbol referred is
absolute.  Such an operation is meaningful, because an absolute symbol
effectively is a constant the calculation of the value of which has been
deferred to the static link time, and which is not going to change any
further at the dynamic load time.  Therefore there is no need ever to
refuse the use of these relocations with such symbols, as the resulting
run-time value observed by the program will be correct even in PIC code.

This is not the case with R_MIPS_26 and its compressed counterparts,
because the run-time value calculated by the instructions these
relocations are used with depends on the address of the instruction
itself, and that can change according to the base address used by the
dynamic loader.  Therefore these relocations have to continue being
rejected in PIC code even with absolute symbols.

This allows successful linking of code that relies on previous linker
behavior up to commit 861fb55ab5 ("Defer allocation of R_MIPS_REL32
GOT slots"), <https://sourceware.org/ml/binutils/2008-08/msg00096.html>,
which introduced the problematic check missing this special exception
for absolute symbols.

	bfd/
	* elfxx-mips.c (_bfd_mips_elf_check_relocs) <R_MIPS16_HI16>
	<R_MIPS_HI16, R_MIPS_HIGHER, R_MIPS_HIGHEST, R_MICROMIPS_HI16>
	<R_MICROMIPS_HIGHER, R_MICROMIPS_HIGHEST>: Also accept an
	absolute symbol in PIC code.

	ld/
	* testsuite/ld-mips-elf/pic-reloc-0.d: New test.
	* testsuite/ld-mips-elf/pic-reloc-1.d: New test.
	* testsuite/ld-mips-elf/pic-reloc-2.d: New test.
	* testsuite/ld-mips-elf/pic-reloc-3.d: New test.
	* testsuite/ld-mips-elf/pic-reloc-4.d: New test.
	* testsuite/ld-mips-elf/pic-reloc-absolute-hi.ld: New test
	linker script.
	* testsuite/ld-mips-elf/pic-reloc-absolute-lo.ld: New test
	linker script.
	* testsuite/ld-mips-elf/pic-reloc-ordinary.ld: New test linker
	script.
	* testsuite/ld-mips-elf/pic-reloc-j.s: New test source.
	* testsuite/ld-mips-elf/pic-reloc-lui.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2018-11-27 16:34:03 +00:00
Maciej W. Rozycki aff68bd041 MIPS/LD: Continue processing with refused relocations in PIC code
Switch from `_bfd_error_handler' to `info->callbacks->einfo' with error
reporting concerning the use of position-dependent relocations such as
R_MIPS_HI16 or R_MIPS_26 in PIC code and continue processing so that any
subsequent link errors are also shown rather than the linker terminating
right away.  This can reduce user frustration where correcting one error
only reveals another one; instead all are shown together making them all
possible to investigate at once.  The use of the `%X' specifier causes
the linker to terminate unsuccessfully at the end of processing.

Also fix the message to say `cannot' rather than `can not'.

	bfd/
	* elfxx-mips.c (_bfd_mips_elf_check_relocs) <R_MIPS16_26>
	<R_MIPS_26, R_MICROMIPS_26_S1>: Use `info->callbacks->einfo'
	rather than `_bfd_error_handler' to report refused relocations
	in PIC code and continue processing.  Fix error message: `can
	not' -> `cannot'.
2018-11-27 16:34:03 +00:00
H.J. Lu 131a5a648d Initialize *uncompressed_align_pow_p to 0
Initialize *uncompressed_align_pow_p to 0 since *uncompressed_align_pow_p
is passed to bfd_is_section_compressed_with_header as uninitialized,

	PR binutils/23919
	* compress.c (bfd_is_section_compressed_with_header): Initialize
	*uncompressed_align_pow_p to 0.
2018-11-27 06:02:36 -08:00
Tamar Christina 9fca35fc34 AArch64: Fix regression in Cortex A53 erratum when PIE. (PR ld/23904)
The fix for PR ld/22263 causes TLS relocations using ADRP to be relaxed
into MOVZ, however this causes issues for the erratum code.

The erratum code scans the input sections looking for ADRP instructions
and notes their location in the stream.

It then later tries to find them again in order to generate the linker
stubs.  Due to the relaxation it instead finds a MOVZ and hard aborts.

Since this relaxation is a valid one, and in which case the erratum no
longer applies, it shouldn't abort but instead just continue.

This changes the TLS relaxation code such that when it finds an ADRP and
it relaxes it, it removes the erratum entry from the work list by changing
the stub type into none so the stub is ignored.

The entry is not actually removed as removal is a more expensive operation
and we have already allocated the memory anyway.

The clearing is done for IE->LE and GD->LE relaxations, and a testcase is
added for the IE case. The GD case I believe to be impossible to get together
with the erratum sequence due to the required BL which would break the sequence.
However to cover all basis I have added the guard there as well.

build on native hardware and regtested on
  aarch64-none-elf, aarch64-none-elf (32 bit host),
  aarch64-none-linux-gnu, aarch64-none-linux-gnu (32 bit host)

Cross-compiled and regtested on
  aarch64-none-linux-gnu, aarch64_be-none-linux-gnu

Testcase in PR23940 tested and works as expected now and benchmarks ran on A53
showing no regressions and no issues.

bfd/ChangeLog:

	PR ld/23904
	* elfnn-aarch64.c (_bfd_aarch64_adrp_p): Use existing constants.
	(_bfd_aarch64_erratum_843419_branch_to_stub): Use _bfd_aarch64_adrp_p.
	(struct erratum_835769_branch_to_stub_clear_data): New.
	(_bfd_aarch64_erratum_843419_clear_stub): New.
	(clear_erratum_843419_entry): New.
	(elfNN_aarch64_tls_relax): Use it.
	(elfNN_aarch64_relocate_section): Pass input_section.
	(aarch64_map_one_stub): Handle branch type none as valid.

ld/ChangeLog:

	PR ld/23904
	* testsuite/ld-aarch64/aarch64-elf.exp: Add erratum843419_tls_ie.
	* testsuite/ld-aarch64/erratum843419_tls_ie.d: New test.
	* testsuite/ld-aarch64/erratum843419_tls_ie.s: New test.
2018-11-27 12:42:22 +00:00
Mark Wielaard 4207142d6a Handle ELF compressed header alignment correctly by setting up the section alignment correctly for the Elf32_Chdr or Elf64_Chdr type and respect the ch_addralign field when decompressing the section data.
PR binutils/23919
binutils* readelf.c (dump_sections_as_strings): Remove bogus addralign check.
	(dump_sections_as_bytes): Likewise.
	(load_specific_debug_sections): Likewise.
	* testsuite/binutils-all/dw2-3.rS: Adjust alignment.
	* testsuite/binutils-all/dw2-3.rt: Likewise.

bfd	* bfd.c (bfd_update_compression_header): Explicitly set alignment.
	(bfd_check_compression_header): Add uncompressed_alignment_power
	argument. Check ch_addralign is a power of 2.
	* bfd-in2.h: Regenerated.
	* compress.c (bfd_compress_section_contents): Get and set
	orig_uncompressed_alignment_pow if section is decompressed.
	(bfd_is_section_compressed_with_header): Add and get
	uncompressed_align_pow_p argument.
	(bfd_is_section_compressed): Add uncompressed_align_power argument
	to bfd_is_section_compressed_with_header call.
	(bfd_init_section_decompress_status): Get and set
	uncompressed_alignment_power.
	* elf.c (_bfd_elf_make_section_from_shdr): Add
	uncompressed_align_power argument to
	bfd_is_section_compressed_with_header call.
2018-11-27 11:59:10 +00:00
GDB Administrator 6a75ea85b1 Automatic date update in version.in 2018-11-27 00:00:24 +00:00
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Jozef Lawrynowicz ca94519e70 Fix linking MSP430 files created by gcc's LTO optimizer.
When invoking GCC with "-g -flto", the compiler will create LTO objects
with debug information. The objects created are "simple ELF" objects (see
libiberty/simple-object-elf.c) and do not have target-specific sections.

When the MSP430 linker sees one of these objects without a .MSP430.attributes
section it errors:

> error: /tmp/cc4LhbEI.ltrans0.ltrans.o uses MSP430X instructions but /tmp/ccynqIwudebugobj uses unknown
> error: /tmp/cc4LhbEI.ltrans0.ltrans.o uses the small code model whereas /tmp/ccynqIwudebugobj uses the unknown code model
> error: /tmp/cc4LhbEI.ltrans0.ltrans.o uses the small data model whereas /tmp/ccynqIwudebugobj uses the unknown data model
> error: /tmp/cc4LhbEI.ltrans0.ltrans.o uses the small code model but /tmp/ccynqIwudebugobj uses the unknown data model
> failed to merge target specific data of file /tmp/cc4LhbEI.ltrans0.ltrans.o

The following patch allows these debug LTO objects to be linked with other
MSP430 objects even if they do not have a .MSP430.attributes section.

bfd	* elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Do not
	error when .MSP430.attributes section is missing from objects
	created by LTO.
2018-11-21 16:21:25 +00:00
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