This fix keeps the section with the highest alignment when folding sections with ICF.
PR gold/17704
* icf.cc (match_sections): Add new parameter section_addraligns.
Check section alignment and keep the section with the strictest
alignment.
(find_identical_sections): New local variable section_addraligns.
Store each section's alignment.
* testsuite/pr17704a_test.s: New file.
* testsuite/Makefile.am (pr17704a_test): New test.
* testsuite/Makefile.in: Regenerate.
Build the test objects with the in-tree assembler. Also fix some cascading
error messages caused by not resetting the skip_call_tls_get_addr_ flag
after printing the error.
gold/
* i386.cc (Target_i386): Reset skip_call_tls_get_addr_ after printing
error message.
* testsuite/Makefile.am (pr20216a): Add missing dependencies.
(pr20308a): Add -Bgcctestdir/ to compile rules.
* testsuite/Makefile.in: Regenerate.
With some versions of gas, the call to tls_get_addr uses a GOTPCREL
relocation instead of a GOTPCRELX relocation. We should allow for that
when skip_call_tls_get_addr_ is true. We should also build the test
objects with the in-tree assembler.
This patch also fixes some cascading error messages caused by not
resetting the skip_call_tls_get_addr_ flag after printing the error.
gold/
PR gold/20216
* x86_64.cc (Target_x86_64::Relocate::relocate): Add check for
R_X86_64_GOTPCREL. Reset skip_call_tls_get_addr_ after printing
error message.
* testsuite/Makefile.am (pr20216_gd.o): Add -Bgcctestdir/.
(pr20216_ld.o): Likewise.
* testsuite/Makefile.in: Regenerate.
This CL implemented the following relocs for AArch64 target.
- R_AARCH64_MOVW_UABS_G*
- R_AARCH64_MOVW_SABS_G* relocations
gold/ChangeLog
2016-07-26 Igor Kudrin <ikudrin@accesssoftek.com>
* aarch64-reloc-property.cc (Rvalue_bit_select_impl): New class.
(rvalue_bit_select): Use Rvalue_bit_select_impl.
* aarch64-reloc.def (MOVW_UABS_G0, MOVW_UABS_G0_NC,
MOVW_UABS_G1,
MOVW_UABS_G1_NC, MOVW_UABS_G2, MOVW_UABS_G2_NC, MOVW_UABS_G3,
MOVW_SABS_G0, MOVW_SABS_G1, MOVW_SABS_G2): New relocations.
* aarch64.cc (Target_aarch64::Scan::local): Add cases for new
MOVW_UABS_* and MOVW_SABS_* relocations.
(Target_aarch64::Scan::global): Likewise.
(Target_aarch64::Relocate::relocate): Add cases and handlings
for new MOVW_UABS_* and MOVW_SABS_* relocations.
* testsuite/Makefile.am (aarch64_relocs): New test.
* testsuite/Makefile.in: Regenerate.
* testsuite/aarch64_globals.s: New test source file.
* testsuite/aarch64_relocs.s: Likewise.
* testsuite/aarch64_relocs.sh: New test script.
With GCC 6 when not using -static-libstdc++, the operator delete(void*)
function is defined in the shared C++ support library, rather than in
the main program. The test script is too aggressive in checking for
this symbol's presence among the exported symbols. This patch removes
the check for that symbol.
gold/
PR gold/20310
* testsuite/dynamic_list.sh: Remove check for _ZdlPv.
There are extensions to 386 psABI:
https://groups.google.com/forum/#!topic/ia32-abi/awsRSvJOJfs
to call tls_get_addr via GOT:
call *___tls_get_addr@GOT(%reg)
where EBX register isn't required as GOT base.
Since direct call is 4-byte long and indirect call, is 5-byte long, the
extra one byte must be handled properly.
For general dynamic model, 7-byte lea instruction before call
instruction is replaced by 6-byte one to make room for indirect call.
For local dynamic model, we simply use 5-byte indirect call.
TLS linker optimization is updated to recognize new instruction
patterns. For local dynamic model to local exec model transition,
we generate a 6-byte lea instruction as nop, instead of a 1-byte nop
plus a 4-byte lea instruction.
PR gold/20308
* i386.cc (Target_i386::Relocate::relocate): Allow
R_386_GOT32X relocation against ___tls_get_addr.
(Target_i386::Relocate::tls_gd_to_ie): Support indirect
call to __tls_get_addr.
(Target_i386::Relocate::tls_gd_to_le): Likewise.
(Target_i386::Relocate::tls_ld_to_le): Likewise.
* testsuite/Makefile.am (check_PROGRAMS): Add pr20308a_test,
pr20308b_test, pr20308c_test, pr20308d_test, pr20308e_test.
(pr20308a_test_SOURCES): New.
(pr20308a_test_DEPENDENCIES): Likewise.
(pr20308a_test_CFLAGS): Likewise.
(pr20308a_test_LDFLAGS): Likewise.
(pr20308a_test_LDADD): Likewise.
(pr20308b_test_SOURCES): Likewise.
(pr20308b_test_DEPENDENCIES): Likewise.
(pr20308b_test_CFLAGS): Likewise.
(pr20308b_test_LDFLAGS): Likewise.
(pr20308b_test_LDADD): Likewise.
(pr20308c_test_SOURCES): Likewise.
(pr20308c_test_DEPENDENCIES): Likewise.
(pr20308c_test_CFLAGS): Likewise.
(pr20308c_test_LDFLAGS): Likewise.
(pr20308c_test_LDADD): Likewise.
(pr20308d_test_SOURCES): Likewise.
(pr20308d_test_DEPENDENCIES): Likewise.
(pr20308d_test_CFLAGS): Likewise.
(pr20308d_test_LDFLAGS): Likewise.
(pr20308d_test_LDADD): Likewise.
(pr20308e_test_SOURCES): Likewise.
(pr20308e_test_DEPENDENCIES): Likewise.
(pr20308e_test_CFLAGS): Likewise.
(pr20308e_test_LDFLAGS): Likewise.
(pr20308e_test_LDADD): Likewise.
(pr20308a.so): Likewise.
(pr20308b.so): Likewise.
(pr20308_gd.o): Likewise.
(pr20308_ld.o): Likewise.
(MOSTLYCLEANFILES): Add pr20308a.so pr20308b.so.
* testsuite/Makefile.in: Regenerated.
* testsuite/pr20308_def.c: New file.
* testsuite/pr20308_gd.S: Likewise.
* testsuite/pr20308_ld.S: Likewise.
* testsuite/pr20308_main.c: Likewise.
There are extensions to x86-64 psABI:
https://groups.google.com/forum/#!topic/x86-64-abi/de5_KnLHxtI
to call tls_get_addr via GOT:
call *__tls_get_addr@GOTPCREL(%rip)
Since direct call is 4-byte long and indirect call, is 5-byte long, the
extra one byte must be handled properly.
For general dynamic model, one 0x66 prefix before call instruction is
removed to make room for indirect call. For local dynamic model, we
simply use 5-byte indirect call.
TLS linker optimization is updated to recognize new instruction
patterns. For local dynamic model to local exec model transition, we
generate 4 0x66 prefixes, instead of 3, before mov instruction in 64-bit
and generate a 5-byte nop, instead of 4-byte, before mov instruction in
32-bit.
PR gold/20216
* configure.ac (DEFAULT_TARGET_X86_64_OR_X32): New
AM_CONDITIONAL.
* configure: Regenerated.
* x86_64.cc (Target_x86_64<size>::Relocate::relocate): Allow
R_X86_64_GOTPCRELX relocation against __tls_get_addr.
(Target_x86_64<size>::Relocate::tls_gd_to_ie): Support indirect
call to __tls_get_addr.
(Target_x86_64<size>::Relocate::tls_gd_to_le): Likewise.
(Target_x86_64<size>::Relocate::tls_ld_to_le): Likewise.
* testsuite/Makefile.am (check_PROGRAMS): Add pr20216a_test,
pr20216b_test, pr20216c_test, pr20216d_test, pr20216e_test.
(pr20216a_test_SOURCES): New.
(pr20216a_test_DEPENDENCIES): Likewise.
(pr20216a_test_CFLAGS): Likewise.
(pr20216a_test_LDFLAGS): Likewise.
(pr20216a_test_LDADD): Likewise.
(pr20216b_test_SOURCES): Likewise.
(pr20216b_test_DEPENDENCIES): Likewise.
(pr20216b_test_CFLAGS): Likewise.
(pr20216b_test_LDFLAGS): Likewise.
(pr20216b_test_LDADD): Likewise.
(pr20216c_test_SOURCES): Likewise.
(pr20216c_test_DEPENDENCIES): Likewise.
(pr20216c_test_CFLAGS): Likewise.
(pr20216c_test_LDFLAGS): Likewise.
(pr20216c_test_LDADD): Likewise.
(pr20216d_test_SOURCES): Likewise.
(pr20216d_test_DEPENDENCIES): Likewise.
(pr20216d_test_CFLAGS): Likewise.
(pr20216d_test_LDFLAGS): Likewise.
(pr20216d_test_LDADD): Likewise.
(pr20216e_test_SOURCES): Likewise.
(pr20216e_test_DEPENDENCIES): Likewise.
(pr20216e_test_CFLAGS): Likewise.
(pr20216e_test_LDFLAGS): Likewise.
(pr20216e_test_LDADD): Likewise.
(pr20216a.so): Likewise.
(pr20216b.so): Likewise.
(pr20216_gd.o): Likewise.
(pr20216_ld.o): Likewise.
(MOSTLYCLEANFILES): Add pr20216a.so pr20216b.so.
* testsuite/Makefile.in: Regenerated.
* testsuite/pr20216_def.c: New file.
* testsuite/pr20216_gd.S: Likewise.
* testsuite/pr20216_ld.S: Likewise.
* testsuite/pr20216_main.c: Likewise.
PowerPC gcc aligns char arrays to a word which results in the test
failing since it expects a char alignment. As the test already uses
gcc attributes to assign variables to sections, we may as well use an
attribute to align too.
* testsuite/plugin_layout_with_alignment.c: Explicitly align all
variables.
A target like powerpc64 that is PIC by default doesn't need copy relocs.
* testsuite/Makefile.am (copy_test_protected): Disable for powerpc.
* testsuite/Makefile.in: Regenerate.
According to "ELF for the ARM(r) 64-bit Architecture (AArch64)",
this relocation can be used "to prevent removal of sections that
might otherwise appear to be unused."
gold/
* aarch64-reloc.def (NONE): New relocation.
* aarch64.cc (Target_aarch64::Scan::local): Handle R_AARCH64_NONE.
(Target_aarch64::Scan::global): Likewise.
* testsuite/Makefile.am (aarch64_reloc_none): New test.
* testsuite/Makefile.in: Regenerate.
* testsuite/aarch64_reloc_none.s: New test source file.
* testsuite/aarch64_reloc_none.sh: New test script.
Please see patch discussion:
https://www.sourceware.org/ml/binutils/2016-05/msg00322.html
2016-06-28 Sriraman Tallam <tmsriram@google.com>
* x86_64.cc (Lazy_view): New class.
(can_convert_mov_to_lea): Templatize function. Make the function
check for appropriate relocation types and use the view parameter
to get section contents.
(can_convert_callq_to_direct): New function.
(Target_x86_64<size>::Scan::global): Refactor.
(Target_x86_64<size>::Relocate::relocate): Refactor. Change any indirect
call via GOT that can be converted.
* testsuite/Makefile.am (x86_64_indirect_call_to_direct.sh): New test.
* testsuite/Makefile.in: Regenerate.
* testsuite/x86_64_indirect_call_to_direct1.s: New file.
* testsuite/x86_64_indirect_jump_to_direct1.s: New file.
The fix for PR 15370 did not correctly check all patterns in a group,
but instead threw all unassigned sections into the group. This patch
fixes that.
2016-06-23 Cary Coutant <ccoutant@gmail.com>
Igor Kudrin <ikudrin@accesssoftek.com>
gold/
PR gold/15370
* script-sections.cc
(Output_section_element_input::set_section_addresses): Keep bin_count
separate from input_pattern_count.
* testsuite/script_test_12.t: Add another section .x4.
* testsuite/script_test_12i.t: Likewise.
* testsuite/script_test_12a.c: Likewise.
* testsuite/script_test_12b.c: Likewise.
The .got.plt section must be placed right after the .got section.
Otherwise, GOT offset will be wrong.
PR gold/20246
* testsuite/script_test_2.t: Add .got.plt after .got.
During LTO, if (1) an IR file contains a COMDAT group that is kept,
(2) a later non-claimed file contains the same group, which we discard,
and (3) the plugin fails to provide a definition of the symbols in that
COMDAT group, gold silently resolves any references to those symbols
to 0.
This patch adds a check for a placeholder symbol when deciding
whether to issue an undefined symbol error. It also adds an extra
note after any undefined placeholder symbol error that explains
that a definition was expected from the plugin.
gold/
PR gold/19842
* errors.cc (Errors::undefined_symbol): Add info message when
symbol should have been provided by a plugin.
* target-reloc.h (issue_undefined_symbol_error): Check for
placeholder symbols defined in discarded sections.
* testsuite/Makefile.am (plugin_test_9b): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/plugin_test_9b_elf.cc: New test source file.
* testsuite/plugin_test_9b_ir.cc: New test source file.
When running ld -r on objects that have comdat groups, when gold
deduplicates a function in a comdat group, it removes the relocations
from the EH information that referred to the dropped copy of the function.
When running a final link using the result of the -r link, the missing
relocation cause it to fail to recognize the FDE for the dropped
function.
This patch improves gold's FDE scanning to take into account the
possibility that an FDE corresponds to a dropped function, and drops
that FDE as well.
Gnu ld, on the other hand, leaves the relocations in the ld -r output,
but makes them R_NONE with an r_sym field of 0. This was sufficient to
let both linkers recognize the FDE properly.
With this fix, if you do an ld -r with gold, then do the final link with
Gnu ld, the .eh_frame_hdr section will not be generated. To make it work
with Gnu ld, we would have to leave the R_NONE relocations in, but I
think it's better to drop the relocations entirely. I'd hope that if
you're doing a -r link with gold, you'll also do the final link with
gold.
gold/
PR gold/19002
* ehframe.cc (Eh_frame::read_fde): Check for dropped functions.
* testsuite/Makefile.am (eh_test_2): New test.
* testsuite/Makefile.in: Regenerate.
* testsuite/eh_test_2.sh: New test script.
* testsuite/eh_test_a.cc (bar): Make it comdat.
* testsuite/eh_test_b.cc (bar): Add a duplicate copy.
G++ in GCC 4.2 silently ignores
---
__attribute__ ((section(".rodata.v1_a2")))
const short rodata_item1 = 101;
---
which leads to plugin_layout_with_alignment test failure with
Expected 12 sections, found 8 sections
since 4 .rodata sections are missing. As a workaround, this patch
changes plugin_layout_with_alignment test from C++ to C.
* testsuite/plugin_layout_with_alignment.cc: Renamed to ..
* testsuite/plugin_layout_with_alignment.c: This.
* testsuite/Makefile.am (plugin_layout_with_alignment.o): Updated.
(plugin_layout_with_alignment): Likewise.
* testsuite/Makefile.in: Regenerated.
GCC 6 does not generate constructors for two of gold's test cases.
This patch simply removes the checks for them.
gold/
PR 19751
* testsuite/Makefile.am (retain_symbols_file_test): Remove check
for constructor.
* testsuite/Makefile.in: Regenerate.
* testsuite/dynamic_list.sh: Likewise.
* testsuite/retain_symbols_file_test.sh: Likewise.
include/
2016-03-03 Than McIntosh <thanm@google.com>
* plugin-api.h: Add new hooks to the plugin transfer vector to
to support querying section alignment and section size.
(ld_plugin_get_input_section_alignment): New hook.
(ld_plugin_get_input_section_size): New hook.
(ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
and LDPT_GET_INPUT_SECTION_SIZE.
(ld_plugin_tv): Add tv_get_input_section_alignment and
tv_get_input_section_size.
gold/
2016-03-03 Than McIntosh <thanm@google.com>
* plugin.cc (Plugin::load): Include hooks for get_input_section_size
and get_input_section_alignment in transfer vector.
(get_input_section_alignment): New function.
(get_input_section_size): New function.
* testsuite/Makefile.am: Add plugin_layout_with_alignment.sh test.
* testsuite/Makefile.in: [Regenerate.]
* testsuite/plugin_section_alignment.cc: New test file.
* testsuite/plugin_layout_with_alignment.cc: New test file.
* testsuite/plugin_layout_with_alignment.sh: New test file.
Let the plugin know that a file is not being included in the link by
returning LDPS_NO_SYMS from get_symbols().
include/
* plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
gold/
* plugin.h (Pluginobj::get_symbol_resolution_info): Add version
parameter.
* plugin.cc (get_symbols_v3): New function.
(Plugin::load): Add LDPT_GET_SYMBOLS_V3.
(Pluginobj::get_symbol_resolution_info): Return LDPS_NO_SYMS when using
new version.
x86_64_mov_to_lea5.o and x86_64_mov_to_lea6.o must be assembled with
-mrelax-relocations=yes since when assembler is configured with
--disable-x86-relax-relocations, R_X86_64_GOTPCRELX relocation won't
be generated. This linker optimization requires R_X86_64_GOTPCRELX
relocation.
This patch also removed the duplicated x86_64_overflow_pc32.o target.
* testsuite/Makefile.am (x86_64_mov_to_lea5.o): Pass
-mrelax-relocations=yes to $(TEST_AS).
(x86_64_mov_to_lea6.o): Likewise.
(x86_64_overflow_pc32.o): Remove duplicated target.
* testsuite/Makefile.in: Regenerated.
gold/ChangeLog:
* s390.cc (Target_s390::match_view_u): New helper method.
(Target_s390::do_is_call_to_non_split): New method.
(Target_s390::ss_code_st_r14): New const.
(Target_s390::ss_code_l_r14): New const.
(Target_s390::ss_code_bras_8): New const.
(Target_s390::ss_code_l_basr): New const.
(Target_s390::ss_code_a_basr): New const.
(Target_s390::ss_code_ear): New const.
(Target_s390::ss_code_c): New const.
(Target_s390::ss_code_larl): New const.
(Target_s390::ss_code_brasl): New const.
(Target_s390::ss_code_jg): New const.
(Target_s390::ss_code_jgl): New const.
(Target_s390::ss_match_mcount): New helper method.
(Target_s390::ss_match_l): New helper method.
(Target_s390::ss_match_ahi): New helper method.
(Target_s390::ss_match_alfi): New helper method.
(Target_s390::ss_match_cr): New helper method.
(Target_s390::do_calls_non_split): New method.
* testsuite/Makefile.am: Added new tests.
* testsuite/split_s390.sh: New test.
* testsuite/split_s390_1_a1.s: New test.
* testsuite/split_s390_1_a2.s: New test.
* testsuite/split_s390_1_n1.s: New test.
* testsuite/split_s390_1_n2.s: New test.
* testsuite/split_s390_1_z1.s: New test.
* testsuite/split_s390_1_z2.s: New test.
* testsuite/split_s390_1_z3.s: New test.
* testsuite/split_s390_1_z4.s: New test.
* testsuite/split_s390_2_ns.s: New test.
* testsuite/split_s390_2_s.s: New test.
* testsuite/split_s390x_1_a1.s: New test.
* testsuite/split_s390x_1_a2.s: New test.
* testsuite/split_s390x_1_n1.s: New test.
* testsuite/split_s390x_1_n2.s: New test.
* testsuite/split_s390x_1_z1.s: New test.
* testsuite/split_s390x_1_z2.s: New test.
* testsuite/split_s390x_1_z3.s: New test.
* testsuite/split_s390x_1_z4.s: New test.
* testsuite/split_s390x_2_ns.s: New test.
* testsuite/split_s390x_2_s.s: New test.
The problem here is that x32 is really using 64-bit addressing,
while pretending to be 32-bit. Even though the object file format
is 32-bit, we need to do the overflow checking with 64-bit
arithmetic (because that's what the hardware will be using).
This patch overrides the pcrela32_check functions in reloc.h
with target-specific versions that do 64-bit checking.
I've also updated the test case to use -Tdata instead of adding
a huge .space directive, to reduce the size of the .o files.
gold/
PR gold/19567
* reloc.h (Relocate_functions::Overflow_check): Add comments.
* x86_64.cc (X86_64_relocate_functions): New class.
(Target_x86_64::Relocate::relocate): Use the new class.
* testsuite/Makefile.am (x86_64_overflow_pc32): Add -Tdata option.
(x32_overflow_pc32): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/x32_overflow_pc32.sh: New script.
* testsuite/x86_64_overflow_pc32.s: Remove .space directive.
For MIPS-64, the r_info field in the relocation format is
replaced by several individual fields, including r_sym and
r_type. To enable support for this format, I've refactored
target-independent code to remove almost all uses of the r_info
field. (I've left alone a couple of routines used only for
incremental linking, which I can update if/when the MIPS target
adds support for incremental linking.)
For routines that are already templated on a Classify_reloc class
(namely, gc_process_relocs, relocate_section, and
relocate_relocs), I've extended the Classify_reloc interface to
include sh_type (which no longer needs to be a separate template
parameter) as well as get_r_sym() and get_r_type() methods for
extracting the r_sym and r_type fields. For
scan_relocatable_relocs, I've extended the
Default_scan_relocatable_relocs class by converting it to a class
template with Classify_reloc as a template parameter. For the
remaining routines that need to access r_sym, I've added a
virtual Target::get_r_sym() method with an override for the MIPS
target.
In elfcpp, I've added Mips64_rel, etc., accessor classes and
corresponding internal data structures. The MIPS target uses
these new classes within its own Mips_classify_reloc class.
The Mips64_ accessor classes also expose the r_ssym, r_type2,
and r_type3 fields from the relocation.
These changes should be functionally the same for all but the
MIPS target.
elfcpp/
* elfcpp.h (Mips64_rel, Mips64_rel_write): New classes.
(Mips64_rela, Mips64_rela_write): New classes.
* elfcpp_internal.h (Mips64_rel_data, Mips64_rela_data): New structs.
gold/
* gc.h (get_embedded_addend_size): Remove sh_type parameter.
(gc_process_relocs): Remove sh_type template parameter.
Use Classify_reloc to access r_sym, r_type, and r_addend fields.
* object.h (Sized_relobj_file::split_stack_adjust): Add target
parameter.
(Sized_relobj_file::split_stack_adjust_reltype): Likewise.
* reloc-types.h (Reloc_types::copy_reloc_addend): (SHT_REL and SHT_RELA
specializations) Remove.
* reloc.cc (Emit_relocs_strategy): Rename and move to target-reloc.h.
(Sized_relobj_file::emit_relocs_scan): Call Target::emit_relocs_scan().
(Sized_relobj_file::emit_relocs_scan_reltype): Remove.
(Sized_relobj_file::split_stack_adjust): Add target parameter.
Adjust all callers.
(Sized_relobj_file::split_stack_adjust_reltype): Likewise. Call
Target::get_r_sym() to get r_sym field from relocations.
(Track_relocs::next_symndx): Call Target::get_r_sym().
* target-reloc.h (scan_relocs): Remove sh_type template parameter;
add Classify_reloc template parameter. Use for accessing r_sym and
r_type.
(relocate_section): Likewise.
(Default_classify_reloc): New class (renamed and moved from reloc.cc).
(Default_scan_relocatable_relocs): Remove sh_type template parameter.
(Default_scan_relocatable_relocs::Reltype): New typedef.
(Default_scan_relocatable_relocs::reloc_size): New const.
(Default_scan_relocatable_relocs::sh_type): New const.
(Default_scan_relocatable_relocs::get_r_sym): New method.
(Default_scan_relocatable_relocs::get_r_type): New method.
(Default_emit_relocs_strategy): New class.
(scan_relocatable_relocs): Replace sh_type template parameter with
Scan_relocatable_relocs class. Use it to access r_sym and r_type
fields.
(relocate_relocs): Replace sh_type template parameter with
Classify_reloc class. Use it to access r_sym and r_type fields.
* target.h (Target::is_call_to_non_split): Replace r_type parameter
with pointer to relocation. Adjust all callers.
(Target::do_is_call_to_non_split): Likewise.
(Target::emit_relocs_scan): New virtual method.
(Sized_target::get_r_sym): New virtual method.
* target.cc (Target::do_is_call_to_non_split): Replace r_type parameter
with pointer to relocation.
* aarch64.cc (Target_aarch64::emit_relocs_scan): New method.
(Target_aarch64::Relocatable_size_for_reloc): Remove.
(Target_aarch64::gc_process_relocs): Use Default_classify_reloc.
(Target_aarch64::scan_relocs): Likewise.
(Target_aarch64::relocate_section): Likewise.
(Target_aarch64::Relocatable_size_for_reloc::get_size_for_reloc):
Remove.
(Target_aarch64::scan_relocatable_relocs): Use Default_classify_reloc.
(Target_aarch64::relocate_relocs): Use Default_classify_reloc.
* arm.cc (Target_arm::Arm_scan_relocatable_relocs): Remove sh_type
template parameter.
(Target_arm::emit_relocs_scan): New method.
(Target_arm::Relocatable_size_for_reloc): Replace with...
(Target_arm::Classify_reloc): ...this.
(Target_arm::gc_process_relocs): Use Classify_reloc.
(Target_arm::scan_relocs): Likewise.
(Target_arm::relocate_section): Likewise.
(Target_arm::scan_relocatable_relocs): Likewise.
(Target_arm::relocate_relocs): Likewise.
* i386.cc (Target_i386::emit_relocs_scan): New method.
(Target_i386::Relocatable_size_for_reloc): Replace with...
(Target_i386::Classify_reloc): ...this.
(Target_i386::gc_process_relocs): Use Classify_reloc.
(Target_i386::scan_relocs): Likewise.
(Target_i386::relocate_section): Likewise.
(Target_i386::scan_relocatable_relocs): Likewise.
(Target_i386::relocate_relocs): Likewise.
* mips.cc (Mips_scan_relocatable_relocs): Remove sh_type template
parameter.
(Mips_reloc_types): New class template.
(Mips_classify_reloc): New class template.
(Target_mips::Reltype): New typedef.
(Target_mips::Relatype): New typedef.
(Target_mips::emit_relocs_scan): New method.
(Target_mips::get_r_sym): New method.
(Target_mips::Relocatable_size_for_reloc): Replace with
Mips_classify_reloc.
(Target_mips::copy_reloc): Use Mips_classify_reloc.
(Target_mips::gc_process_relocs): Likewise.
(Target_mips::scan_relocs): Likewise.
(Target_mips::relocate_section): Likewise.
(Target_mips::scan_relocatable_relocs): Likewise.
(Target_mips::relocate_relocs): Likewise.
(mips_get_size_for_reloc): New function, factored out from
Relocatable_size_for_reloc::get_size_for_reloc.
(Target_mips::Scan::local): Use Mips_classify_reloc.
(Target_mips::Scan::global): Likewise.
(Target_mips::Relocate::relocate): Likewise.
* powerpc.cc (Target_powerpc::emit_relocs_scan): New method.
(Target_powerpc::Relocatable_size_for_reloc): Remove.
(Target_powerpc::gc_process_relocs): Use Default_classify_reloc.
(Target_powerpc::scan_relocs): Likewise.
(Target_powerpc::relocate_section): Likewise.
(Powerpc_scan_relocatable_reloc): Convert to class template.
(Powerpc_scan_relocatable_reloc::Reltype): New typedef.
(Powerpc_scan_relocatable_reloc::reloc_size): New const.
(Powerpc_scan_relocatable_reloc::sh_type): New const.
(Powerpc_scan_relocatable_reloc::get_r_sym): New method.
(Powerpc_scan_relocatable_reloc::get_r_type): New method.
(Target_powerpc::scan_relocatable_relocs): Use
Powerpc_scan_relocatable_reloc.
(Target_powerpc::relocate_relocs): Use Default_classify_reloc.
* s390.cc (Target_s390::emit_relocs_scan): New method.
(Target_s390::Relocatable_size_for_reloc): Remove.
(Target_s390::gc_process_relocs): Use Default_classify_reloc.
(Target_s390::scan_relocs): Likewise.
(Target_s390::relocate_section): Likewise.
(Target_s390::Relocatable_size_for_reloc::get_size_for_reloc):
Remove.
(Target_s390::scan_relocatable_relocs): Use Default_classify_reloc.
(Target_s390::relocate_relocs): Use Default_classify_reloc.
* sparc.cc (Target_sparc::emit_relocs_scan): New method.
(Target_sparc::Relocatable_size_for_reloc): Remove.
(Target_sparc::gc_process_relocs): Use Default_classify_reloc.
(Target_sparc::scan_relocs): Likewise.
(Target_sparc::relocate_section): Likewise.
(Target_sparc::Relocatable_size_for_reloc::get_size_for_reloc):
Remove.
(Target_sparc::scan_relocatable_relocs): Use Default_classify_reloc.
(Target_sparc::relocate_relocs): Use Default_classify_reloc.
* tilegx.cc (Target_tilegx::emit_relocs_scan): New method.
(Target_tilegx::Relocatable_size_for_reloc): Remove.
(Target_tilegx::gc_process_relocs): Use Default_classify_reloc.
(Target_tilegx::scan_relocs): Likewise.
(Target_tilegx::relocate_section): Likewise.
(Target_tilegx::Relocatable_size_for_reloc::get_size_for_reloc):
Remove.
(Target_tilegx::scan_relocatable_relocs): Use Default_classify_reloc.
(Target_tilegx::relocate_relocs): Use Default_classify_reloc.
* x86_64.cc (Target_x86_64::emit_relocs_scan): New method.
(Target_x86_64::Relocatable_size_for_reloc): Remove.
(Target_x86_64::gc_process_relocs): Use Default_classify_reloc.
(Target_x86_64::scan_relocs): Likewise.
(Target_x86_64::relocate_section): Likewise.
(Target_x86_64::Relocatable_size_for_reloc::get_size_for_reloc):
Remove.
(Target_x86_64::scan_relocatable_relocs): Use Default_classify_reloc.
(Target_x86_64::relocate_relocs): Use Default_classify_reloc.
* testsuite/testfile.cc (Target_test::emit_relocs_scan): New method.
Some linker code editing needs to change multiple insns. In some
cases multiple relocations are involved and it is not sufficient to
make the changes independently as relocations are processed, because
doing so might lead to a partial edit. So in order to safely edit we
need all the relocations available in relocate(). Also, to emit
edited relocs corresponding to the edited code sequence we need some
way to pass information from relocate() to relocate_relocs(),
particularly if the edit depends on insns. We can't modify input
relocs in relocate() as they are mmapped PROT_READ, nor it is
particularly clean to write relocs to the output at that stage. So
add a Relocatable_relocs* field to relinfo to mark edited relocs.
Given that relocate is passed the raw reloc pointer, it makes sense to
remove the rel/rela parameter and r_type too. However, that means the
mips relocate() needs to know whether SHT_REL or SHT_RELA relocs are
being processed. So add a rel_type for mips, which also has the
benefit of removing relocate() overloading there.
This patch adds the infrastructure without making use of it.
Note that relinfo->rr will be NULL if not outputting relocations.
* object.h (struct Relocate_info): Add "rr".
* reloc.h (Relocatable_relocs::set_strategy): New accessor.
* reloc.cc (Sized_relobj_file::do_relocate_sections): Init
relinfo.rr for relocate_section and relocate_relocs.
* powerpc.cc (relocate): Add rel_type and preloc parameters.
Delete rela and r_type params, instead recalculate these from
preloc.
(relocate_relocs): Delete Relocatable_relocs* param, instead
use relinfo->rr.
* aarch64.cc: Likewise.
* arm.cc: Likewise.
* i386.cc: Likewise.
* mips.cc: Likewise.
* s390.cc: Likewise.
* sparc.cc: Likewise.
* target.h: Likewise.
* tilegx.cc: Likewise.
* x86_64.cc: Likewise.
* testsuite/testfile.cc: Likewise.
* target-reloc.h (relocate_section): Adjust to suit.
(apply_relocation, relocate_relocs): Likewise.
x86_64_mov_to_lea1.o is a 64-bit x86-64 object and x86_64_mov_to_lea2.o
is a 32-bit x86-64 object. x86_64_mov_to_lea11 should use
x86_64_mov_to_lea2.o and x86_64_mov_to_lea12 should use
x86_64_mov_to_lea1.o.
* testsuite/Makefile.am (x86_64_mov_to_lea11): Replace
x86_64_mov_to_lea1.o with x86_64_mov_to_lea2.o.
(x86_64_mov_to_lea12): Replace x86_64_mov_to_lea2.o with
x86_64_mov_to_lea1.o.
* testsuite/Makefile.in: Regenerated.
If a symbol is defined with ".symver foo,foo@VER", the assembler
creates two symbols in the object: one unversioned, and one with
the (non-default) version "VER". If foo is listed in a version
script, gold would then make the first of those symbols the
default version, and would ignore the second symbol as a
duplicate, without making it a non-default version. While this is
arguably reasonable behavior, it doesn't match Gnu ld behavior,
so this patch fixes that by allowing the second definition to
override the first by resetting the "default version" indication.
Several test cases from the Gnu ld testsuite also exposed another
related problem, where a symbol defined with ".symver foo,foo@",
placed into a shared library, is not handled properly by gold.
This patch also fixes that case, binding the symbol to the base
version.
gold/
PR gold/18703
* dynobj.cc (Versions::record_version): Handle symbol defined with
base version.
(Versions::symbol_section_contents): Likewise.
* symtab.h (Symbol::set_is_not_default): New class method.
(Symbol_table::resolve): Add is_default_version parameter.
(Symbol_table::should_override): Likewise.
* resolve.cc (Symbol_table::resolve): Add is_default_version parameter,
and pass to should_override. Adjust all callers and explicit
instantiations.
(Symbol_table::should_override): Add is_default_value parameter;
allow default version in a dynamic object to override existing
definition from same object.
* symtab.cc (Symbol_table::add_from_object): Handle case where same
symbol is defined as unversioned and non-default version in the same
object.
* testsuite/Makefile.am (ver_test_13): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/ver_test_4.cc: Add test for symbol with base version.
* testsuite/ver_test_4.sh: Likewise.
* testsuite/ver_test_13.c: New source file.
* testsuite/ver_test_13.script: New version script.
* testsuite/ver_test_13.sh: New test case.
GCC 5 will fold symbol address comparison, assuming each symbol has a
different address, which leads to abort. We should use separate
functions to compare symbol address.
PR gold/18663
* testsuite/Makefile.am (script_test_1_SOURCES): Set to
script_test_1a.cc script_test_1b.cc.
(script_test_11_r.o): Replace script_test_11.o with
script_test_11a.o script_test_11b.o.
(script_test_11.o): Removed.
(script_test_11a.o): New.
(script_test_11b.o): Likewise.
* testsuite/Makefile.in: Regenerated.
* testsuite/script_test_1.h: New file.
* testsuite/script_test_1b.cc: Likewise.
* testsuite/script_test_11.h: Likewise.
* testsuite/script_test_11b.c: Likewise.
* testsuite/script_test_1.cc: Renamed to ...
* testsuite/script_test_1a.cc: This.
Include "script_test_1.h".
(main): Call check_int and check_ptr.
* testsuite/script_test_11.c: Renamed to ...
* testsuite/script_test_11a.c: This.
Include "script_test_11.h".
(main): Call ptr_equal.
GCC 5 will generate a relocation for protected symbol:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65248
when compiling for a shared library. It is undefined to access protected
symbol in IFUNC selector function inside a shared library.
PR gold/18628
* testsuite/ifuncdep2.c (global): Change protected to hidden.
* testsuite/ifuncmod1.c (global): Likewise.
* testsuite/ifuncmod5.c (global): Likewise.
